FSL337LRN [ONSEMI]
绿色模式安森美半导体降压开关;
| 型号： | FSL337LRN |
| 厂家： | 
ONSEMI |
| 描述： | 绿色模式安森美半导体降压开关 开关 半导体 |
| 文件： | 总14页 (文件大小：912K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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August 2016
FSL337LR
Green Mode Fairchild Buck Switch
Features
Description
.
.
.
Built-in Avalanche-Rugged SenseFET: 700 V
The FSL337LR integrated Pulse Width Modulator
(PWM) and SenseFET is specifically designed for high-
performance offline buck, buck-boost, and non-isolation
flyback Switched Mode Power Supplies (SMPS) with
minimal external components. This device integrates a
high-voltage power regulator that enables operation
Fixed Operating Frequency: 50 kHz
No-Load Power Consumption:
<25 mW at 230 VAC with External Bias;
<120 mW at 230 VAC without External Bias
without
transconductance
components for the feedback compensation circuit.
auxiliary
bias
amplifier
winding.
An
internal
external
.
.
.
.
.
.
.
.
No Need for Auxiliary Bias Winding
Frequency Modulation for Attenuating EMI
Pulse-by-Pulse Current Limiting
reduces
The integrated PWM controller includes: 10 V regulator
for no external bias circuit, Under-Voltage Lockout
(UVLO), Leading-Edge Blanking (LEB), an optimized
gate turn-on / turn-off driver, EMI attenuator, Thermal
Shutdown (TSD), temperature-compensated precision
current sources for loop compensation, and fault-
protection circuitry. Protections include: Overload
Protection (OLP), Over-Voltage Protection (OVP), and
Feedback Open Loop Protection (FB_OLP). FSL337LR
offers good soft-start performance during startup.
Ultra-Low Operating Current: 250 µA
Built-in Soft-Start and Startup Circuit
Adjustable Peak Current Limit
Built-in Transconductance (Error) Amplifier
Various Protections: Overload Protection (OLP),
Over-Voltage Protection (OVP), Feedback
Open-Loop Protection (FB_OLP), Thermal
Shutdown (TSD)
The internal high-voltage startup switch and the Burst-
Mode operation with very low operating current reduce
the power loss in Standby Mode. As the result, it is
possible to reach power loss of 120 mW without
external bias and 25 mW with external bias when input
.
Fixed 650 ms Restart Time for Safe Auto-Restart
of All Protections
Applications
voltage is 230 VAC
.
.
SMPS for Home Appliances and Industrial
Applications
.
.
SMPS for Auxiliary Power
E-meter Power Supply
Ordering Information
Typical Output Power(1)
85 VAC ~ 265 VAC
Operating
Part
Packing
Method
Junction
Temperature
PKG
& Open Frame(2)
Current
Limit
Number
RDS(ON),MAX
Buck
Flyback
Application(1) Application
1.8 A
4 Ω
9 W
20 W
FSL337LRN
Notes:
1. The junction temperature can limit the maximum output power.
2. Maximum practical continuous power in an open-frame design at 50°C ambient.
-40°C ~125°C
7-DIP
Rail
3. Based on 15 V output voltage condition. Output voltage can limit the maximum output power.
© 2016 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSL337LR • Rev.1.0
Application Diagrams
+
+
DC
OUT
_
VCOMP
Drain
VFB
HV-DC
INPUT
ILIMIT
VCC
Drain GND
HV-DC
INPUT
DC
OUT
_
Figure 1. Buck Converter Application
Figure 2. Non-Isolation Flyback Converter
Application
Block Diagram
Drain
6, 7
VCC
2
10V HVREG
VCC Good
Internal
Bias
VBIAS
VSTART
/ VSTOP
Transconductance
Amplifier
VFB
4
VBURH/VBURL
Green-
Mode
OSC
Controller
VBIAS
VREF
Q
Q
S
R
IPK
Gate
Driver
3R
R
PWM
Soft-
Start
LEB
ILIMIT
3
5
650ms
Protection
Timing Control
RSENSE
VCOMP
40ms
Delay
1
GND
VOLP
VCC
TSD
VFB
VOVP
VFB_OLP
Figure 3. Internal Block Diagram
© 2016 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSL337LR • Rev.1.0
2
Pin Configuration
Drain
Drain
GND
VCC
7DIP
ILIMIT
VFB
Vcomp
Figure 4. Pin Configuration
Pin Definitions
Pin #
Name
Description
Ground. SenseFET source terminal on the primary side and internal control ground.
1
GND
Positive Supply Voltage Input. This pin is the positive supply input that provides the internal
operating current for startup and steady-state operation. This pin voltage is regulated to 10 V,
without the external bias circuit, via an internal switch (see Figure 3). When the external bias
voltage is >10 V, it disables the internal high-voltage regulator to reduce power consumption.
2
3
VCC
Peak Current Limit. Adjusts the peak current limit of the SenseFET. The internal 50 µA
current source is diverted to the parallel combination of an internal 46 kΩ (3R + R) resistor and
any external resistor to GND on this pin to determine the peak current limit.
ILIMIT
Feedback Voltage. Inverting input of the transconductance amplifier. This pin controls the
converter output voltage by outputting a current proportional to the difference between the
reference voltage and the output voltage divided by external resistors.
4
5
VFB
Comp Voltage. Output of the transconductance amplifier. The compensation networks are
placed between the VCOMP and GND pins to achieve stability and good dynamic performance.
VCOMP
Drain. High-voltage power SenseFET drain connection. In addition, during startup and steady-
state operation; the internal high-voltage current source supplies internal bias and charges the
external capacitor connected to the VCC pin. Once VCC reaches 8 V, all internal blocks are
activated. The internal high-voltage current source is enabled until VCC reaches 10 V. After
that, the internal high-voltage regulator turns on and off regularly to maintain VCC at 10 V.
6, 7
Drain
© 2016 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSL337LR • Rev.1.0
3
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only. TA = 25 °C, unless otherwise specified.
Symbol
Parameter
Drain Pin Voltage
Min.
Max.
Unit
VDS
VCC
VCOMP
VFB
-0.3
-0.3
-0.3
-0.3
-0.3
700.0
V
V
Supply Voltage
26.0
VCOMP Pin Voltage
Internally Clamped Voltage(4)
V
Feedback Voltage
12.0
12.0
12
V
ILIMIT
IDM
Current Limit Pin Voltage
Drain Current Pulsed(5)
Single Pulsed Avalanche Energy(6)
Total Power Dissipation
Operating Junction Temperature(7)
Maximum Junction Temperature
Storage Temperature
V
A
EAS
230
1.25
125
150
150
mJ
W
°C
°C
°C
PD
-40
-55
TJ
TSTG
Notes:
4. VCOMP is clamped by internal clamping diode (11 V, ICLAMP_MAX < 100 μA)
5. Repetitive rating: pulse width is limited by maximum junction temperature.
6. L=51 mH, starting TJ=25C.
7. Although this parameter guarantees IC operation, it does not guarantee all electrical characteristics.
Thermal Impedance
TA=25°C unless otherwise specified.
Symbol
Parameter
Value
Unit
θJA
Junction-to-Ambient Thermal Impedance(8)
100
°C/W
Notes:
8. JEDEC recommended environment, JESD51-2, and test board, JESD51-3, with minimum land pattern.
ESD Capability
Symbol
Parameter
Human Body Model, ANSI/ESDA/JEDEC JS-001-2012(9)
Charged Device Model, JESD22-C101(9)
Value
Unit
4
2
ESD
kV
Note:
9. Meets JEDEC standards ANSI/ESDA/JEDEC JS-001-2012 and JESD 22-C101.
© 2016 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSL337LR • Rev.1.0
4
Electrical Characteristics
TA = 25C unless otherwise specified.
Symbol
Parameter
Conditions
Min. Typ. Max. Unit
SenseFET Section
BVDSS Drain-Source Breakdown Voltage
IDSS Zero Gate Voltage Drain Current
RDS(ON) Drain-Source On-State Resistance
VCC = 0 V, ID = 250 µA
700
V
VDS = 520 V, TA = 125°C
VGS = 10 V, ID = 1 A
250
µA
Ω
4.0
315
47
9
4.75
CISS
COSS
CRSS
tr
Input Capacitances
Output Capacitance
Reverse Transfer Capacitance
Rise Time
VGS = 0 V, VDS = 25 V, f = 1 MHz
VGS = 0 V, VDS = 25 V, f = 1 MHz
VGS = 0 V, VDS = 25 V, f = 1 MHz
VDD = 350 V, ID = 3.5 A
pF
pF
pF
ns
ns
34
32
tf
Fall Time
VDD = 350 V, ID = 3.5 A
Control Section
fOSC Switching Frequency
fM
Frequency Modulation(10)
VCOMP = 2.5 V
45
50
±3
55
kHz
kHz
µs
VCOMP = 2.5 V, Randomly
VCOMP = 2.5 V
ton.max Maximum Turn-On Time
11.2
7.2
6.3
35
13.3
8.0
7.0
50
15.4
8.8
7.7
65
VSTART
VCOMP = 0 V, VCC Sweep
After Turn On
V
UVLO Threshold Voltage
VSTOP
V
IPK
tSS
Current Limit Source Current
Soft-Start Time
VCOMP = 2.5 V
µA
ms
VCOMP = 2.5 V
7
10
13
Burst Mode Section
VBURH Burst-Mode HIGH Threshold Voltage VCC = 15 V, VCOMP Increase
VBURL Burst-Mode LOW Threshold Voltage VCC = 15 V, VCOMP Decrease
HYSBUR Burst-Mode Hysteresis
0.58
0.52
0.65
0.59
60
0.72
0.66
V
V
mV
Protection Section
ILIM
tCLD
VOLP
tLEB
Peak Current Limit
Current Limit Delay(10)
VCOMP = 2.5 V, di/dt = 1.2 A/µs
VCOMP Increase
1.6
2.7
1.8
200
3.0
200
0.5
2.0
3.3
A
ns
V
Overload Protection
Leading-Edge Blanking Time(10)
ns
V
VFB_OLP FB Open-Loop Protection
VFB Decrease
VCC Increase
0.4
23.0
125
0.6
26.0
150
VOVP
TSD
Over-Voltage Protection
Thermal Shutdown Temperature(10)
24.5
135
60
V
°C
°C
ms
ms
HYSTSD TSD Hysteresis Temperature(10)
tDELAY Overload Protection Delay(10)
tRESTART Restart Time After Protection(10)
VCOMP > 3 V
40
650
Transconductance Amplifier Section
Gm
Transconductance of Error Amplifier
Voltage Feedback Reference
Output Sourcing Current
380
480
2.50
-12
12
580 µmho
VREF
IEA.SR
IEA.SK
2.45
2.55
V
VFB = VREF - 0.025 V
VFB = VREF + 0.025 V
µA
µA
Output Sink Current
Continued on the following page…
© 2016 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSL337LR • Rev.1.0
5
Electrical Characteristics
TA = 25C unless otherwise specified.
Symbol
Parameter
Conditions
Min. Typ. Max. Unit
High-Voltage Regulator Section
VHVREG HV Regulator Voltage
Total Device Section
VCOMP = 0 V, VDRAIN = 40 V
9
10
11
V
Operating Supply Current (Control
IOP1
0 V < VCOMP < VBURL
VBURL < VCOMP < VOLP
0.25
0.8
0.35
1.3
mA
mA
Part Only, without Switching)
Operating Supply Current
IOP2
(While Switching)
ICH
Startup Charging Current
VCC = 0 V, VDRAIN > 40 V
6
mA
µA
V
ISTART Startup Current
VDRAIN Minimum Drain Supply Voltage
Note:
VCC = Before VSTART, VCOMP = 0 V
VCC = VCOMP = 0 V, VDRAIN Increase
120
35
155
10. Though guaranteed by design; not 100% tested in production.
© 2016 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSL337LR • Rev.1.0
6
Typical Performance Characteristics
Switching Frequency (fOSC
)
HV Regulator Voltage (VHVREG)
1.15
1.10
1.05
1.00
0.95
0.90
0.85
1.15
1.10
1.05
1.00
0.95
0.90
0.85
-40
-20
0
25
50
75
100 125
-40
-20
0
25
50
75
100 125
Temperature (℃)
Figure 5. Operating Frequency vs. Temperature
Temperature (℃)
Figure 6. HV Regulator Voltage vs. Temperature
Start Threshold Voltage (VSTART
)
Stop Threshold Voltage (VSTOP)
1.15
1.10
1.05
1.00
0.95
0.90
0.85
1.15
1.10
1.05
1.00
0.95
0.90
0.85
-40
-20
0
25
50
75
100 125
-40
-20
0
25
50
75
100 125
Temperature (℃)
Figure 7. Start Threshold Voltage vs. Temperature
Temperature (℃)
Figure 8. Stop Threshold Voltage vs. Temperature
Burst Mode High Voltage (VBURH
)
Burst Mode Low Voltage (VBURL)
1.15
1.10
1.05
1.00
0.95
0.90
0.85
1.15
1.10
1.05
1.00
0.95
0.90
0.85
-40
-20
0
25
50
75
100 125
-40
-20
0
25
50
75
100 125
Temperature (℃)
Temperature (℃)
Figure 9. Burst Mode High Voltage vs. Temperature Figure 10. Burst Mode Low Voltage vs. Temperature
© 2016 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSL337LR • Rev.1.0
7
Typical Performance Characteristics (Continued)
Operating Supply Current (IOP1
)
Feedback Voltage Reference (VREF)
1.15
1.10
1.05
1.00
0.95
0.90
0.85
1.15
1.10
1.05
1.00
0.95
0.90
0.85
-40
-20
0
25
50
75
100 125
-40
-20
0
25
50
75
100 125
Temperature (℃)
Temperature (℃)
Figure 11. Operating Supply Current 1
Figure 12. Feedback Voltage Reference
vs. Temperature
vs. Temperature
Transconductance of gm amp (Gm)
FB Open Loop Protection (VFB_OLP)
1.15
1.10
1.05
1.00
0.95
0.90
0.85
1.15
1.10
1.05
1.00
0.95
0.90
0.85
-40'C -20'C 0'C 25'C 50'C 75'C 100'C 120'C
-40
-20
0
25
50
75
100 125
Temperature (℃)
Temperature (℃)
Figure 13. Transconductance of gm Amplifier
Figure 14. FB Open-Loop Protection Voltage
vs. Temperature
vs. Temperature
Overload Protection (VOLP
)
Over-Voltage Protection (VOVP)
1.15
1.10
1.05
1.00
0.95
0.90
0.85
1.15
1.10
1.05
1.00
0.95
0.90
0.85
-40
-20
0
25
50
75
100 125
-40
-20
0
25
50
75
100 125
Temperature (℃)
Temperature (℃)
Figure 15. Overload Protection vs. Temperature
Figure 16. Over-Voltage Protection vs. Temperature
© 2016 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSL337LR • Rev.1.0
8
Functional Description
1. Startup and High-Voltage Regulator
3. Feedback Control
During startup, an internal high-voltage current source
(ICH) of the high-voltage regulator supplies the internal
bias current (ISTART) and charges the external capacitor
(CA) connected to the VCC pin, as illustrated in Figure
17. This internal high-voltage current source is enabled
until VCC reaches 10 V. During steady-state operation,
this internal high-voltage regulator (HVREG) maintains
The FSL337LR employs current-mode control with a
transconductance amplifier for feedback control, as
shown in Figure 19. Two resistors are typically used on
the VFB pin to sense output voltage. An external
compensation circuit is recommended on the VCOMP pin to
control output voltage.
A built-in transconductance
amplifier accurately controls output voltage without
external components, such as Zener diode and transistor.
the VCC with 10 V and provides operating current (IOP
)
for all internal circuits. Therefore, no external bias circuit
is necessary. The high-voltage regulator is disabled
when the external bias is higher than 10 V.
Drain
6,7
Green-
Mode
Controller
OSC
VOUT
VBIAS
Transconductance
Amplifier
VDC.link
IPK
VFB
3R
4
5
PWM
LEB
Drain
6, 7
Gate
Driver
VREF
D1
D2
R
VCC
ICH
VCOMP
RSENSE
3
10V HVREG
CC1
RC1
ISTART (during startup)
Iop (during steady-state operation)
CC2
CA
Figure 19. Pulse Width Modulation (PWM) Circuit
VBIAS
UVLO
3.1
Transconductance Amplifier (gm Amplifier)
The output of the transconductance amplifier sources
and sinks the current, respectively, to and from the
compensation circuit connected on the VCOMP pin (see
Figure 20). This compensated VCOMP pin voltage
controls the switching duty cycle by comparing with the
voltage across the RSENSE. When the feedback pin
voltage exceeds the internal reference voltage (VREF) of
2.5 V; the transconductance amplifier sinks the current
from the compensation circuit, VCOMP is pulled down,
and the duty cycle is reduced. This typically occurs
when input voltage is increased or output load is
decreased. A two-pole and one-zero compensation
network is recommended for optimal output voltage
control and AC dynamics. Typically 220 nF, 75 k, and
220 pF are used for CC1, RC1, and CC2; respectively.
Figure 17. Startup and HVREG Block
2. Oscillator Block
The oscillator frequency is set internally with a random
frequency fluctuation function. Fluctuation of the
switching frequency can reduce Electro-Magnetic
Induction (EMI) by spreading the energy over a wider
frequency range than the bandwidth measured by the
EMI test equipment. The amount of EMI reduction is
directly related to the range of the frequency variation.
The range of frequency variation is fixed internally;
however, its selection is randomly chosen by the
combination of an external feedback voltage and an
internal free-running oscillator. This randomly chosen
switching frequency effectively spreads the EMI noise
near switching frequency and allows the use of a cost-
effective inductor instead of an AC input line filter to
satisfy world-wide EMI requirements.
IEA [A]
Sinking current 12µA at
2.525V
+24µA
-24µA
IDS
several
mseconds
tSW=1/fSW
Sourcing current 12µA at
2.475V
tSW
t
Dt
Gm [µmho]
fSW
MAX
960µmho
480µmho
fSW+1/2DfSW
MAX
no repetition
fSW-1/2DfSW
VFB
2.45V
2.55V
VFB
several
miliseconds
VREF
(2.5V)
Figure 20. Characteristics of gm Amplifier
t
Figure 18. Frequency Fluctuation Waveform
© 2016 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSL337LR • Rev.1.0
9
consumes more than this maximum power, the output
voltage (VO) decreases below its rated voltage. This
reduces feedback pin voltage, which increases the
output current of the internal transconductance
amplifier. Eventually VCOMP is increased. When VCOMP
reaches 3 V, the internal fixed OLP delay (40 ms) is
activated. After this delay, the switching operation is
terminated, as shown in Figure 22.
3.2
Pulse-by-Pulse Current Limit
Because current-mode control is employed, the peak
current flowing through the SenseFET is limited by the
inverting input of PWM comparator, as shown in Figure
19. Assuming that 50 µA current source flows only
through the internal resistors (3R + R = 46 kΩ), the
cathode voltage of diode D2 is about 2.4 V. Since D1 is
blocked when VCOMP exceeds 2.4 V, the maximum
voltage of the cathode of D2 is clamped at this voltage.
Therefore, the peak value of the current of the
SenseFET is limited.
OSC
OLP
Q
Q
S
R
3R
PWM
Gate
Driver
LEB
3.3
Leading Edge Blanking (LEB)
R
At the instant the internal SenseFET is turned on, a
high-current spike through the SenseFET is typically
caused by: primary-side capacitance and secondary-
side rectifier diode reverse recovery of flyback
application, the freewheeling diode reverse recovery,
and other parasitic capacitance of buck application.
VCOMP
RSENSE
5
40ms
Delay
OLP
VOLP
Figure 21. Overload Protection Internal Circuit
Excessive voltage across the sensing resistor (RSENSE
)
VCC
leads to incorrect feedback operation in the current-
mode control. To counter this effect, the FSL337LR has
a Leading-Edge Blanking (LEB) circuit (see Figure 19).
This circuit inhibits the PWM comparator for a short time
(tLEB) after the SenseFET is turned on.
HVREG
VSTART
VSTOP
20ms
IDS
40ms 650ms
Overloading
Normal
with SS
SS 40ms 650ms
4. Protection Circuits
The protective functions include Overload Protection
(OLP), Over-Voltage Protection (OVP), Under-Voltage
Lockout (UVLO), Feedback Open-Loop Protection
(FB_OLP), and Thermal Shutdown (TSD). All of the
protections operate in Auto-Restart Mode. Since these
protection circuits are fully integrated within the IC
without external components, reliability is improved
without increasing cost or PCB space. If a fault condition
occurs, switching is terminated and the SenseFET
remains off. At the same time, internal protection timing
control is activated to decrease power consumption and
stress on passive and active components during Auto-
Restart Mode. When internal protection timing control is
activated, VCC is regulated with 10 V through the internal
high-voltage regulator until switching is terminated. This
internal protection timing control continues until the
restart time (650 ms) expires. After 650 ms, the internal
high-voltage regulator is disabled and VCC is decreased.
When VCC reaches the UVLO stop voltage VSTOP (7 V),
the protection is reset and the internal high-voltage
current source charges the VCC capacitor via the drain
pin again. When VCC reaches the UVLO start voltage,
VSTART (8 V), normal operation resumes. In this manner,
Auto-Restart Mode can alternately enable and disable
the switching of the power SenseFET until the fault
condition is eliminated.
Power on
Overloading Overloading
Stops
Overloading
Stops
Figure 22. Overload Protection (OLP) Waveform
4.2
Thermal Shutdown (TSD)
The SenseFET and control IC integrated on the same
package makes it easier to detect the temperature of
the SenseFET. When the junction temperature exceeds
135°C, thermal shutdown is activated. The FSL337LR is
restarted after the temperature decreases to 60°C.
4.3
Over-Voltage Protection (OVP)
If any feedback loop components fail due to a soldering
defect, VCOMP climbs up in manner similar to the
overload situation, forcing the preset maximum current
to be supplied to the SMPS until the OLP is triggered. In
this case, excessive energy is provided to the output
and the output voltage may exceed the rated voltage
before the OLP is activated. To prevent this situation, an
Over-Voltage Protection (OVP) circuit is employed. In
general, output voltage can be monitored through VCC
and, when VCC exceeds 24.5 V, OVP is triggered,
resulting in termination of switching operation. To avoid
undesired activation of OVP during normal operation,
VCC should be designed below 24.5 V (see Figure 23).
OSC
OVP
4.1
Overload Protection (OLP)
Q
Q
S
R
Overload is defined as the load current exceeding a pre-
set level due to an unexpected event. In this situation,
the protection circuit should be activated to protect the
SMPS. However, when the SMPS operates normally,
the OLP circuit can be enabled during load transition or
startup. To avoid this undesired operation, an internal
fixed delay (40 ms) circuit determines whether it is a
transient situation or a true overload situation (see
Figure 21). The current-mode feedback path limits the
maximum power current and, when the output
3R
PWM
OVP
Gate
driver
LEB
R
VCC
RSENSE
2
VOVP
Figure 23. Over-Voltage Protection Circuit
© 2016 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSL337LR • Rev.1.0
10
VO
Voset
4.4
Feedback Open Loop Protection (FB_OLP)
In the event of a feedback loop failure, especially a
shorted lower-side resistor of the feedback pin; not only
does VCOMP rise in a similar manner to the overload
situation, but VFB starts to drop to IC ground level.
Although OLP and OVP also can protect the SMPS in
this situation, FB_OLP can reduce stress on SenseFET.
If there is no FB_OLP, output voltage is much higher
than the rated voltage before OLP or OVP triggers.
When VFB drops below 0.5 V, FB_OLP is activated,
switching off. To avoid undesired activation during
startup, this function is disabled during soft-start time.
VCOMP
VBURH
VBURL
IDS
VDS
OSC
FB_OLP
Q
Q
S
R
3R
PWM
VOUT
Gate
Driver
time
LEB
R
Switching
disabled
Switching
disabled
RH
t1
t2 t3
t4
VFB
RSENSE
4
Figure 26. Burst Mode Operation
FB_OLP
RL
VFB_OLP
7. Green Mode Operation
As output load condition is reduced, the switching loss
becomes the largest power loss factor. FSL306LR uses
the VCOMP pin voltage to monitor output load condition.
As output load decreases, VCOMP decreases and
switching frequency declines, as shown in Figure 27.
Once VCOMP falls to 0.8 V, the switching frequency
varies between 21 kHz and 23 kHz before Burst Mode
operation. At Burst Mode operation, random frequency
fluctuation still functions.
Figure 24. Feedback Open-Loop Protection Circuit
5. Soft-Start
The internal soft-start circuit slowly increases the
SenseFET current after it starts. The typical soft-start
time is 10 ms, as shown in Figure 25, where progressive
increments of the SenseFET current are allowed during
startup. The pulse width to the power switching device is
progressively increased to establish the correct working
conditions for transformers, inductors, and capacitors.
The voltage on the output capacitors is gradually
increased to smoothly establish the required output
voltage. Soft-start also helps to prevent transformer
saturation and reduces stress on the secondary diode.
Random Frequency
modulation range
Switching frequency
53 kHz
47 kHz
1.25ms
ILIM
23 kHz
21 kHz
1.9V
VCOMP
VBURL VBURH 0.8V
Soft-start envelope
Figure 27. Green Mode Operation
8. Adjusting Current Limit
As shown in Figure 28, a combined 46 kΩ internal
resistance (3R + R) is connected to the inverting lead on
the PWM comparator. An external resistance of Rx on
the ILIMIT pin forms a parallel resistance with the 46 kΩ
when the internal diodes are biased by the main current
source of 50 µA. For example, FSL337LR has a typical
SenseFET peak current limit of 1.8 A. Current limit can
be adjusted to 1.2 A by inserting RX between the ILIMIT
pin and the ground. The value of the RX can be
estimated by the following equation:
0.2ILIM
Drain Current
8-Steps
t
Figure 25. Internal Soft-Start
6. Burst Mode Operation
To minimize power dissipation in Standby Mode, the
FSL337LR enters Burst Mode. As the load decreases,
the COMP pin voltage (VCOMP) decreases. As shown in
Figure 26, the device automatically enters Burst Mode
when the feedback voltage drops below VBURL. At this
point, switching stops and the output voltages start to
drop at a rate dependent on the standby current load.
1.8 A : 1.2 A = (46 kΩ + RX) : RX
(1)
Transconductance
Amplifier
VFB
4
VBIAS
VREF
This causes VCOMP to rise. Once it passes VBURH
,
IPK
switching resumes. VCOMP then falls and the process
repeats. Burst Mode alternately enables and disables
switching of the SenseFET and reduces switching loss
in Standby Mode.
3R
PWM
VCOMP
5
3
R
ILIMIT
VSENSE
RX
Figure 28. Current Limit Adjustment
© 2016 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSL337LR • Rev.1.0
11
9.779
9.525
A
7
5
B
6.477
6.223
PIN #1
(0.787)
4
1
TOP VIEW
7.874
7.620
12°
2.54
12°
3.937
3.683
3.429
3.175
0.381
0.203
3.556
3.048
C
0.508 MIN
SEATING
PLANE
7.53
1.651
1.397
9.398
7.874
0.508
0.406
M
0.10
C
FRONT VIEW
SIDE VIEW
NOTES:
A. REFERENCE JEDEC MS-001, VARIATION BA
EXCEPT FOR NUMBER OF LEADS.
B. DIMENSIONS ARE IN MILLIMETERS
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 2009
D. DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH AND TIE BAR EXTRUSIONS.
E. DRAWING FILENAME: MKT-NA07Drev2
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