FSL4110LRLX [ONSEMI]
1000V 集成电源开关，带线路 OVP，无偏置绕组，用于 9W 离线反激转换器;
| 型号： | FSL4110LRLX |
| 厂家： | 
ONSEMI |
| 描述： | 1000V 集成电源开关，带线路 OVP，无偏置绕组，用于 9W 离线反激转换器 开关 电源开关 转换器 |
| 文件： | 总16页 (文件大小：620K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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1000ꢀVꢀSenseFETꢀ↖ꢁꢀ⁰ꢂꢃ
FSL4110LR
PDIP−7 (PDIP−8 LESS PIN 6)
(7−DIP)
CASE 626A
ꢄᫀ
FSL4110LRꢀ᠏ꢀᏰჯꢁඝꢂЖ (PWM)ꢀᖇЖ
ࡈ
٬
1000 Vꢃ༉ ꢄ✈ SenseFET，ꢁ✈ꢂ᮸ꢃꢄᣠŔ▨ᩣꢅꢀիҋএჯრ͓
ᰁჯꢀ⁰ (SMPS)。V ꢀ
᪗ៀᩕ҉ȯիথঔŔꢀᏰჯ▨իꢀ CC
⁰ꢂ
ࡈ
Żꢀ。 PDIP7 MINUS PIN 6 GW
(7−LSOP)
ꢀᏰჯ PWMꢀᖇЖ
ࡈ
ӥᓌࣚ
ൺ⍡╧ᔏัࡈ
、ᴀիῑൺ (UVLO)、 ЭẟὨⅠ (LEB)、øӶŔ᧥ᥡ╁҈
ࡈ
、ͥ᮸ᨿ؏҈、✈ꢂ▏ᢿ ጵɟŔꢁႆጵɟ
ގ
ඦꢀἡ⁰٬
פ
ҝƽᒄꢀᢿ。 CASE 707AA
⛾Ϧ֛ჯ MOSFETꢀ
٬
PWMꢀᖇЖࡈ
ᒳΓយᨨLjᶴ，FSL4110L Rꢀ
ईℝĮማᏰᤌ、ꢃꢄᝐ、PCBꢀบෘÅ֪ᲝᲟŔ
៖ᖰ▨ᜨ ╧、⛿
╧٬
ߋ
য
∰ሇ。ᚵࡈ
ꢄᖰŻf⛰ꢆᤌŔၓא
， ר
ᚎᙱ▨ሇ×ᶴŔ֭↠ჯᨼᕂࡈ
。 MARKING DIAGRAM
$Y&Z&2&K
L4110LR
ꢅ
$Y&Z&2&K
L4110LR
•ꢇͥਾꢃ༉ꢄ✈ 1000 V SenseFET
•ꢇ
ގ
̾Ŕࣚ
ൺ࿅ļ⍡╧：50 kHz •ꢇV
Თ✈ȯիথঔၴȯਾŻꢀ CC
FSL4110LRN
FSL4110LRLX
•ꢇᨿᴧᰁჯᚭļ
ᣠଇӛႆℝĮ⋃⍡ ࡊ
⋃ •ꢇꢀΑၒᑐ෯Ŕ⅟ᤚ⍡╧Ể҈
•ꢇꢁΒ℠ἡ
•ꢇ
פ
ҝƽᒄѿ்：᪗ᩍƽᒄ (OLP)、᪗իƽᒄ (OVP)、ტဘ᪗ἡƽ ᒄ (AOCP)、ဆ₾
ࢾ
ѿ்Ŕͥ᮸⋍͓ឍ (TSD)。ဆ₾ࢾ
ѿ்Ŕᴀ իῑൺ (UVLO)
٬এ
ᢿ᪗իƽᒄ (LOVP)。 $Y
&Z
&2
&K
= Logo
= Assembly Plant Code
= 2−Digit Date Code
= 2−Digits Lot Run Traceability Code
L4110LR = Specific Device Code
•ꢇͥਾͥ᮸
؏҈٬
ᨿ؏҈ꢀᢿ •ꢇෙꢂᐠᣩƽᒄѿ்Ŕ൩͈҈Ო؏ᰁჯ，
ࣚ
ൺᲝ؏៖ꢈ1.6 s • These are Pb−Free Devices
ORDERING INFORMATION
See detailed ordering and shipping information on page 13 of
this data sheet.
ꢆ✈
•ꢇ✈ꢂꢀ்ᙱᲟŔ SMPS
•ꢇ✈ꢂ3 Ljᩣꢅ࿅✊
ߋ
যŔᩕ҉ꢀ⁰ © Semiconductor Components Industries, LLC, 2014
1
Publication Order Number:
April, 2022 − Rev. 2
FSL4110LRCN/D
FSL4110LR
ꢇꢈꢆ✈ꢀᢿ
V
OUT
R
STR
(ꢀ 1)
V
STR
R1
R2
FSL4110LR
Drain
GND
V
IN
PWM
V
CC
FB
R
(ꢀ 2)
DLY
C
C
VCC
FB
ꢀꢁ:
1. RSTR：ᛇ֢ᒑꢀ்ᛄ ؏ꢁꢂ▨իᛓ
ࡈ
。 2. RDLY：ᛇ֢ᒑꢀ்ᛄ ᪗ᩍƽᒄ (OLP)。
ꢉ 1. ꢇꢈꢆ✈ꢀᢿ
ꢊ᮸ᨦꢉ
VCC
2
VSTR
5
Drain
6, 7
HVREG
VCC Good
+
−
Internal
Bias
VSTART
/VSTOP
VREF
−
+
Soft
Burst
VBURH
/VBURL
VCC
Random
OSC
VREF
IFB
Q
Q
S
R
RDLY
Gate
Driver
FB
3R
PWM
3
4
−
−
+
Soft−
Start
R
Line
Comp.
LEB
CFB
RSENSE
+
−
1.6 s Auto Restart
Timing Control
100 ms
Delay
1
GND
VIN
VOLP
+
−
+
−
VINH
VAOCP
VCC
+
−
TSD
VOVP
ꢉ 2. ꢊ᮸ᨦꢉ
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2
FSL4110LR
ꢋ௪ᰝਾ
1
Drain
Drain
7
6
GND
VCC
FB
2
3
4
5
V
IN
VSTR
ꢉ 3. ꢋ௪ᰝਾ (ꢌᒖꢉ)
ꢋ௪ꢍꢎ
ꢋ௪ꢏ
ꢐӀ
ꢄᫀ
1
2
GND
ᖅऐ。Ͻ
ॷֿ٬
ͥ᮸ PWM ᖇЖऐ⛺Ŕ SenseFET ⁰ᥡֿ。 V
CC
ꢂ⁰ꢂիᩣͅ。ᚵჵ௪ꢃꢂ⁰ᵃᩣͅ，ꢃ؏ꢁ
٬ꢃꢄꢅꢆꢇ
Żͥ᮸ꢈļꢂꢉ。ᚵꢂիꢊ؏ꢁ᪗ꢋꢄꢌͥ᮸▨իᛓ )ꢅꢇŻ(֢ᒑꢎ 2)。ꢏꢐ᮸ȯի▨n10 Vꢅꢑ，ꢒꢓͥ᮸▨իᛓ
ࡈ
。ꢔꢊꢕꢖ்ꢗꢘꢙჵ௪
ࡈ
ꢍ᪗ჵ௪ 5 (V STR
٬ჵ௪
1 (GND)ꢅ+ꢚꢛꢜ⛰ꢆꢝꢞꢂꢟ。ꢠꢡꢢꢣꢤn3 mm。 3
FB
ꢥꢦ。ꢙჵ௪®ͥ᮸ꢧᖅꢨ PWMꢅꢩꢪ
ࡈ
Ŕꢥꢫᩣͅ。ꢙჵ௪Ŕͥ᮸ꢂꢉ⁰ꢃ100ĂmA。̩ꢂꢬꢭࡈ
Ŕꢮꢂᥡꢍꢯ ꢧᖅꢨꢙჵ௪。
ꢰꢊꢙჵ௪٬
GNDꢅ+ꢚꢛꢜ⛰ꢆꢂꢟ。ꢰꢊꢙჵ௪٬ჵ௪
2 (V )ꢅ+ꢚꢧᖅ⛰ꢆꢂꢱ，Åꢊ᪗ᩍ CC
ƽᒄꢲꢳꢑꢚͥꢴꢵꢲꢳꢂꢉ (I
)。ꢂꢱŔꢶꢷꢰȯꢜ⛽ꢸꢹ᪗ 5 MW。
DELAY
4
5
V
ꢺꢻꢼ᪗իᩣͅ。ꢙჵ௪ꢃϦꢺꢂիŔᩣͅჵ௪。ꢌꢂꢱꢽꢆϦի。ꢏꢙꢂի▨n2 Vꢅꢑ，FSL4110LRꢅ⛽ꢅꢆ。
ꢾꢿꢙჵ௪ꣀşꢓ，ϹꢰꢧᖅАऐ。
IN
V
STR
؏ꢁ。ꢧᖅꢨꣁꢉꣂŔ ACꢅꢺꣃꢂի⁰。؏ꢁꢑ，ͥ᮸꣄͓ꢇŻͥ᮸ȯիꣅĭnV ꢅ
ჵ௪٬ᖅऐꢚŔꢐ᮸
ʈ CC
ꢂꢟꢽꢆ̥ꢂ。⛰ V ꢅА12 V，ͥ᮸꣎꣏꣐꣑。꣒꣄ꣅ͓꣓ͥ᮸▨իᛓ
ࡈ
，Åꢊ꣔꣕҉ȯի꣖꣗ CC
Ŕ꣘Ε⛻꣙ V ꢅƽꢃ10 V。
CC
6, 7
Drain
ᥡ。ꢓnᖅꢧᖅꢨի
ࡈ
ŔϽॷჵ௪，꣄͓ꢂիꢃ1000 V。ꢋ꣠ऐ꣡꣢꣣{ჵ௪ꢂիࡈ
Ŕꢧᖅ꣤ ꢺ꣥꣠，Åίꢤ꣦。
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3
FSL4110LR
ভꢑꢒꢓ⍭ꢍꢔ
ꢏ ꢕꢖ
ꢒꢗꢔ
ꢒꢓꢔ
700
1000
27
ꢘꢙ
V
V
STR
V
STR
ჵ௪ꢂի
−
−
V
ᥡჵ௪ꢂի
ჵ௪ꢂի
V
DS
CC
V
V
−
V
CC
V
ꢥꢦჵ௪ꢂի (ꢀ 3)
ჵ௪ꢂի (ꢀ 3)
−0.3
−0.3
−
12.0
12.0
4
V
FB
V
V
IN
V
IN
I
꣧Βᥡꢂꢉ
A
DM
I
ꢧ꣄͓꣨ᥡꢂꢉ (ꢀ 4)
T
T
= 25°C
−
1
A
DS
C
= 100°C
−
0.6
A
C
E
꣩꣧Β்꣪꣫꣬ (ꢀ 5)
−
51
mJ
W
°C
°C
°C
AS
P
꣭ꢀ꣮ (T = 25°C) (ꢀ 6)
−
1.5
D
C
T
−
150
+125
+150
꣯꣰
J
ꢈļ꣯꣰ (ꢀ 7)
ʈ꣰꣠
−40
−55
TSTG
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
(֢꣱ꣲꣳ)
ꢾꢿꢂիꢹ᪗ꣴꣵȜꣶꢄϷϚŔȜꣷ꣸，
ࡈ
Öꢖ்ú꣹꣺。ꢾꢿꢹ᪗Ûĵ꣣{ꣻȜ，꣙꣔꣼ƽꣽࡈ
Öꢀ்，ꢖ்úꣾꣿࡈ
Ö꣹꣺，꤀꤁ ꢖꢗ꤂。
3. V
٬
V ꢌͥ᮸꤃ĭlᥡ꤄ꢽꢆ꤃ĭ(11 V、I < 100 mA)。 CLAMP_MAX
FB
IN
4. ȧꣵ꣦꤂꤅ᩍꢑ꤆꤇꤈Ȝ꣄͓ꢂꢉ：꤉ꤊꤋꢩ (D
5. I = 3.2 A、L = 10 mH、؏ꢁT = 25°C。
= 0.73)
٬꣯꣰Ŕꣻ
Ж(֢ᒑꢎ 4)。 MAX
AS
J
6. ꣔ꣻΗꤌꤍÖ(ᛇ֢ᒑ SEMI G30-88)。
7. ꤎꤏꢙ֢ꤐƽꣽ IC ꢈļ，Ħ⛽ƽꣽꢂꤑꤒ꤂。
IDS
DMAX
f S
ꢉ 4. Ოꢚꢛꢔꢂꢃꢀἡ
⋍ℋ
ꢏ ꢕꢖ
ꢖꢔ
ꢘꢙ
q
꣯ꢨꤓꤔꤕꢱ (ꢀ 8)
85
°C/W
JA
8. JEDEC ꤖꤗꤓꤔ，JESD51-2
٬ꤘꤙꤚ
JESD51-3，͗ꢤꤛꤜꤝꤞ。 ∩ꢀꢜꢀ (ESD) ்ꢝ
ꢏ ꢕꢖ
ijꤟ，ANSI/ESDA/JEDEC JS-001-2012
̣Ö̥ꢂꤟ，JESD22-C101
ꢖꢔ
5.0
ꢘꢙ
ESD
KV
2.0
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4
FSL4110LR
ꢂꤑꤒ꤂ (T = −40°C ꢨ 125°C，ꤠꤡꤢꤣꣵ)
J
ꢏ ꢕꢖ
࿅ļÖ
ꢒꢗꢔ ꢇꢈꢔ ꢒꢓꢔ
ꢘꢙ
SenseFET ᮸Ϧ
BV
⁰ᥡϛꤤꢂի (ꢀ 9)
V
V
V
V
= 0 V, I = 250 mA
1000
−
−
−
250
10
477
48.8
−
V
DSS
GS
DS
GS
DS
D
I
ꤥꤦᥡꢂիꢂꢉ (ꢀ 9)
⁰ᥡꣾꢍꢂꢱ (ꢀ 9)
ᩣͅꢂꢟ (ꢀ 9) (ꢀ 10)
ᩣϚꢂꢟ (ꢀ 9) (ꢀ 10)
ꣾꢍꢲꢳꢑꢚ (ꢀ 9)
⛺ꤧꢑꢚ (ꢀ 9)
= 1000 V, V = 0 V
−
−
−
−
−
−
−
−
mA
W
DSS
GS
R
DS(ON)
= 10 V, I = 1.0 A
−
D
C
ISS
= 25 V, V = 0 V,
367
37.5
13.7
14
pF
pF
ns
ns
ns
ns
GS
f = 1 MHz
C
OSS
d(on)
t
V
DD
V
GS
= 500 V, I = 1.0 A,
D
= 10 V, R = 25 W
g
t
−
r
t
͓ꤨꢲꢳꢑꢚ (ꢀ 9)
⛻ꤩꢑꢚ (ꢀ 9)
33
−
d(off)
t
45
−
f
ᖇЖ᮸Ϧ
f
꣄͓ꤪ꤫ (ꢀ 9)
ꤪ꤫ᛓЖ(ꢀ 10)
ꤊꤋꢩ
V
= 14 V, V = 4 V
46.5
−
50.0
1.5
67
53.5
−
kHz
kHz
%
S
CC
FB
f
M
D
V
CC
V
FB
V
FB
= 14 V, V = 4 V
61
70
11
7
73
130
13
9
MAX
FB
I
FB
ꢥꢦ⁰ꢂꢉ (ꢀ 9)
UVLO ꤬Ȝꢂի
= 0 V
100
12
mA
V
V
= 0 V, V ꤭꤮
CC
START
V
ꣾꢍꣂ, V = 0 V
8
STOP
FB
t
ͥ᮸꤯؏ꢁꢑꢚ
V
STR
= 40 V, V ꤭꤮
−
20
−
ms
S/S
CC
ᴧᰁჯ᮸Ϧ
V
ꢚꤰꤱꢂի (ꢀ 9)
V
CC
= 14 V, V ꤭꤮
0.45
0.35
−
0.50
0.40
100
0.55
0.45
−
V
V
BURH
FB
V
BURL
V
mV
HYS
ƽᒄ᮸Ϧ
I
꤈Ȝᥡꣻꢉ (ꢀ 9)
᪗ᩍƽᒄ (ꢀ 9)
di/dt = 240 mA/ms
0.45
4.0
−
0.52
4.4
1.0
250
−
0.59
4.8
−
A
V
LIM
V
V
CC
= 14 V, V ꤭꤮
OLP
FB
V
AOCP
ꤲꢯ᪗ꢉƽᒄ (ꢀ 10)
Эꤳꤴꤵꢑꢚ (ꢀ 10) (ꢀ 11)
ꢂꢉꣻЖꢲꢳꢑꢚ (ꢀ 10)
᪗իƽᒄ
V
t
−
−
ns
ns
V
LEB
t
−
200
26.0
2.1
−
CLD
V
V
CC
V
CC
V
CC
Sweep
23.0
1.9
−
24.5
2.0
100
100
1.6
140
60
OVP
V
ꢺꣃ᪗իƽᒄ꤬Ȝꢂի
ꢺꣃ᪗իƽᒄꤶꤷ (ꢀ 9)
᪗ᩍƽᒄꢲꢳ
= 14 V, V ꤭꤮
V
INH
IN
V
= 14 V, V ꤭꤮
mV
ms
s
INHYS
DELAY
IN
t
−
−
t
ƽᒄꣂ꤆؏ꢑꢚ (ꢀ 10)
ꤕ͓ꤨ꣰꣠ (ꢀ 10)
−
−
RESTART
TSD
͓ꤨ꣰꣠
130
−
150
−
°C
T
HYS
ꤶꤷ (FSL4110LRN)
ꤶꤷ (FSL4110LRLX)
−
30
−
▨իᛓ
ࡈ
᮸Ϧ ▨իᛓ
ࡈ
ꢂի V
V
FB
= 0 V, V = 40 V
STR
9
10
11
V
HVREG
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5
FSL4110LR
ꢂꤑꤒ꤂ (T = −40°C ꢨ 125°C，ꤠꤡꤢꤣꣵ) (꣨)
J
ꢏ ꢕꢖ
࿅ļÖ
ꢒꢗꢔ ꢇꢈꢔ ꢒꢓꢔ
ꢘꢙ
ማ
ࡈ
Ö᮸Ϧ I
ꢈļꢂ⁰ꢂꢉ，(ꢚꤰꤱꢄŔᖇЖ᮸Ϧ) (ꢀ 9)
V
V
= 14 V, V = 0 V
−
−
0.40
1.00
0.50
1.35
mA
mA
OP
CC
FB
I
ꢈļ꣄͓ꢂꢉ，(ᖇЖ᮸Ϧ
٬
SenseFET ᮸Ϧ) (ꢀ 9)
= 14 V, V = 2 V
FB
OPS
CC
I
؏ꢁꢂꢉ (ꢀ 9)
V
CC
= 11 V (V ꤭ꤪ V
−
160
240
mA
START
CC
START
+Э)
= V = 0 V, V = 40 V
STR
I
؏ꢁ̥ꢂꢂꢉ (ꢀ 9)
V
CC
1.5
−
2.0
−
−
mA
V
CH
FB
V
STR
ꢤ V
ꢂ⁰ꢂի
C
VCC
= 0.1 mF, V ꤭ꤪ
STR
26
STR
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
(֢꣱ꣲꣳ)
ꤠꤡꤢᛄ，“ꢂꤑꤒ꤂”ꣶꤸꢄϷϚŔꤹϷꤘꤙꤍÖ⛻Ŕꤺ꤂்֢ꤐ。ꢾꢿꢊ⛽ꤻꤍÖ⛻ꢅꢆ，ꤺ꤂்ꢖ்ꢂ“ꢂꤑꤒ꤂”ꣶꤸ
ꢄϷ꤂்֢ꤐ⛽⛰ꣿ。
9. T = 25°C。
J
10.꣣{֢ꤐꢕ꤄ꢸАƽꣽ，Ħꣅꤡ 100% ꤼ᪗ꢴꤘꤙ。
11.t
ӥꤽꤦᥡꣾꢍꢑꢚ。
LEB
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6
FSL4110LR
ꢇꢈꢅ்ᅡ
(ꤒ꤂ꢎꢊ T = 25°C ꢑꤾΦӶ。)
A
Operating Supply Current (I
)
Operating Switching Current (I
)
OPS
OP
1.15
1.1
1.15
1.1
1.05
1
1.05
1
0.95
0.9
0.95
0.9
0.85
0.85
−40°C −25°C 0°C 25°C 50°C 85°C 100°C 125°C
Temperature (°C)
−40°C −25°C 0°C 25°C 50°C 85°C 100°C 125°C
Temperature (°C)
ꢉ 5. ࿅ļꢀ⁰ꢀἡ (IOP) ⛾TA
ꢉ 6. ࿅ļꢂꢃꢀἡ (IOPS) ⛾TA
Startup Charging Current (I
)
Peak Drain Current Limit (I
)
CH
LIM
1.15
1.1
1.15
1.1
1.05
1
1.05
1
0.95
0.9
0.95
0.9
0.85
0.85
−40°C −25°C 0°C 25°C 50°C 85°C 100°C 125°C
Temperature (°C)
−40°C −25°C 0°C 25°C 50°C 85°C 100°C 125°C
Temperature (°C)
ꢉ 7. ؏҈̥ꢀꢀἡ (ICH) ⛾TA
ꢉ 8. ꢛꢔ⃯ᥡ℠ἡ (ILIM) ⛾TA
Feedback Source Current (I
)
Startup Charging Current (V
)
HVREG
FB
1.15
1.1
1.15
1.1
1.05
1
1.05
1
0.95
0.9
0.95
0.9
0.85
0.85
−40°C −25°C 0°C 25°C 50°C 85°C 100°C 125°C
Temperature (°C)
−40°C −25°C 0°C 25°C 50°C 85°C 100°C 125°C
Temperature (°C)
ꢉ 9. ֭ꢀἡ⁰ (IFB) ⛾TA
ꢉ 10. ▨իᛓ
ࡈ
ꢀի(VHVREG) ⛾TA www.onsemi.cn
7
FSL4110LR
ꢇꢈꢅ்ᅡ(ᖅ⛺ꤿ)
(ꤒ꤂ꢎꢊ T = 25°C ꢑꤾΦӶ。)
A
UVLO Threshold Voltage (V
)
UVLO Threshold Voltage (V
)
START
STOP
1.15
1.1
1.15
1.1
1.05
1
1.05
1
0.95
0.9
0.95
0.9
0.85
0.85
−40°C −25°C 0°C 25°C 50°C 85°C 100°C 125°C
Temperature (°C)
−40°C −25°C 0°C 25°C 50°C 85°C 100°C 125°C
Temperature (°C)
ꢉ 11. UVLO ⃘ꢔꢀի(VSTART) ⛾TA
ꢉ 12. UVLO ⃘ꢔꢀի(VSTOP) ⛾TA
OLP Feedback Voltage (V
)
Over−Voltage Protection (V
)
OLP
OVP
1.15
1.1
1.15
1.1
1.05
1
1.05
1
0.95
0.9
0.95
0.9
0.85
0.85
−40°C −25°C 0°C 25°C 50°C 85°C 100°C 125°C
Temperature (°C)
−40°C −25°C 0°C 25°C 50°C 85°C 100°C 125°C
Temperature (°C)
ꢉ 13. OLP ֭ꢀի(VOLP) ⛾TA
ꢉ 14. ᪗իƽᒄ(VOVP) ⛾TA
Switching Frequency (f )
Maximum Duty Ratio (D
)
S
MAX
1.15
1.1
1.15
1.1
1.05
1
1.05
1
0.95
0.9
0.95
0.9
0.85
0.85
−40°C −25°C 0°C 25°C 50°C 85°C 100°C 125°C
Temperature (°C)
−40°C −25°C 0°C 25°C 50°C 85°C 100°C 125°C
Temperature (°C)
ꢉ 15. ꢂꢃ⍡╧ (fS) ⛾TA
ꢉ 16. ꢒꢓꢞՊᶴ (DMAX) ⛾TA
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8
FSL4110LR
ꢟ்ᛄꢠ
؏҈⛾▨իᛓ
ࡈ
ᐠÅD2ꢀŔᣠଇ℄ᥡꢀի෦
٭
ĭईᵄꢀիȜ。ࣀ
ᵄ， ؏҈，▨իꢂ
ࡈ
(HV )ꢀŔͥ᮸▨իꢀἡ⁰
SenseFET Ŕꢀἡ໐Ȝ෦℠Жꢈ：
REG
(ICH)ᖰŻͥ᮸ȯਾꢀἡ (I
)，ၖ
ױ
ᖅೃꢀV ჵ
CC
START
2.4 V
Sense Ratio
RSENSE
௪Ŕ᮸ꢀꢀ(C
իꢀἡ⁰⛰DŽꢂş்⒖ᇡ，DŽೃꢀV АꢀV
)ꢀ̥ꢀ，ୢ
ࣞ
ꢀ17ꢀᐠЊ。ᚵͥ᮸▨ VCC
(eq. 2)
CC
START
(12 V) 。ԃ ᇡ ᪠ ጜ ᪗ ӛ ꢉ， ᵄ ͥ ᮸ ▨ ի ꢂ
ࡈ
(HV ) ෦ꢀV ƽᓡईꢀ10 V，ၖ
ױ
ᐠᣩͥ᮸ꢀᢿᖰŻ Drain
6, 7
VCC
VREF
REG
CC
OSC
IDLY
RDLY
FB
IFB
࿅ļრ͓ꢀἡꢀ(I
)。
ࣀ
ᵄ，FSL4110LR ៀ⇐᮸ȯ VOUT
OPS
3R
PWM
3
Gate
Driver
FOD817
ਾꢀᢿ。᮸ȯիᖰŻŔVCC ▨ꢂꢀ10 V ៖，ё✈ᚵ
▨իꢂ
ࡈ
。ĦୢᲗ✈ၴȯਾ，Ϲѿ૧෦ᖰ ▨。
D1
D2
R
CFB
Line
Comp.
LEB
RSENSE
OLP
AOCP
VOLP
1
GND
KA431
VAOCP
Rectified
Line Input
RSTR
(VDC
)
CINH
R1
R2
ꢉ 18. ꢣᛓЖꢀᢿ
CINL
CVCC
ЭẟὨⅠ (LEB)
ͥ᮸ SenseFETꢀොŔ᭳⛰Л，
Ͻॷֿꢀ٬ᴁॷ
ֿ ἡ
ࡈ
Ŕ ֭ ױ
ቂ ૭ ဘ ො ೄ ▨ ꢀ ἡ ໐ ᪗ VSTR
VCC
2
5
ICH
HVREG
ISTART or IOPS
SenseFET。R
ꢀꢀℋꢊֿŔ᪗ଇꢀիúොೄꢀἡ
SENSE
Internal
Bias
ᰁჯ PWMꢀᖇЖꢉϚ▐⛽ᵃ̾Ŕ֭᪠ጜ⒖Ε。ꢈf
ᒕὨ᪩ҝᜨၴ，FSL4110LRꢀᲗ✈ЭẟὨⅠ (LEB)ꢀꢀ
VSTART
/ VSTOP
VCC Good
VREF
ᢿ。SenseFETꢀො
，ᵄꢀᢿ෦ई t Ж PWMꢀᶴᩓ
ࡈ
。 (250 ns)ꢀͥᑱ
LEB
ꢉ 17. ؏҈ꢡHVREG ᰁꢢ
ƽᒄꢀᢿ
؏҈ꢀℋ (R )
᪗⛻ჯ (1) ᙱ٧ᅷϚ
。 STR
ƽᒄѿ்ӥᓌ᪗ᩍƽᒄ (OLP)、᪗իƽᒄ (OVP)、
ᴀիῑൺ (UVLO)、ტဘ᪗ἡƽᒄ (AOCP)ꢀÅ֪⋍͓
ឍ (TSD)。ᐠᣩ᪩{ƽᒄѿ்ᯍई҈Ო؏ᰁჯ⛻࿅
ļ，ୢ
ࣞ
19ꢀᐠЊ。ꢂꢂ᪩{ƽᒄꢀᢿᯍ൬͈ꢀᏰई ICꢀꢉ，ៀ⇐Ûĵ᮸ꢃꢄ，
ࣀ
ᵄ்૿ई⛽ҀᏰᤌ٬
PCBꢀՊŔእΕ⛻ᖰ▨
∰ሇ。ୢϚ▐ᜥⅬእΕ， რ͓෦ঘᵂ，✄SenseFETꢀƽᓡ͓ឍ。
៖，᪨ú↠ Ἓͥ᮸ƽᒄᙱ៖ᖇЖ，ÅℝĮ҈Ო؏᪗ӛꢉ
ៀ⁰٬
ᣩ⁰
ࡈ
ꢄ⛺Ŕѿ૧٬ၴѻ
。ͥ᮸ƽᒄᙱ៖ᖇЖ↠Ἓ VDC_MIN * VSTART
RSTR
v
(eq. 1)
ICH
͖ꢉ，I
< I < 2 mA，R
+ R1 = R2 + R3
OPS
CH
STR
֭ᖇЖ
FSL4110LRꢀᲗ✈ꢀἡᰁჯᖇЖយᨨ。ဘ✈ᴁॷֿ
Ŕ̩ꢀ
ࡈר
ꢀ(ୢꢀFOD817) ٬ၖ
ତꢂࡈ
ꢀ(ୢꢀKA431) ঔᏰ֭ਡব。෦֭ꢀի⛾R
ꢀℋꢊֿŔꢀ
SENSE
ի᪫ጜᶴᩓ，
ൾ▐რ͓ՀՊᶴŔᖇЖ。ᄳᩣꢅꢀի ᖰ▨ᩣϚᩍℝĮ៖，Ϧիꢂ
ࡈ
Ŕ֢ᩣꢅꢀի ᖰ▨。ୢᵄꢀիᡕ᪗Ϧիꢂ
ࡈ
Ŕͥ᮸֢ꢀի， ̩ꢀ
ࡈר
Ŕ̩ꢀlᥡٱ
ꢀἡҀ，®ᒩĮ֭ꢀ իၖί⃯ᥡꢀἡ。
៖，V ꢀ෦᪗ͥ᮸▨իꢂ
ࡈ
ꢂꢈ10 V，DŽАঘ CC
ᵂრ͓。᪩ҝͥ᮸ƽᒄᙱ៖ᖇЖú⛰DŽᓡঽАᲝ؏៖
(1.6 s)ꢀণ。ᙱᝐА 1.6 sꢀ៖，෦ё✈ͥ᮸▨իꢂ
ࡈ
ၖℝĮV 。ᄳ V ꢀА UVLOꢀȼᵂꢀի V STOP
CC
CC
(8 V)ꢀ៖，෦૭ĭƽᒄѿ்，ͥ᮸▨իꢀἡ⁰ͭᴁ᪗
▨ի؏҈ჵ௪ (V )ꢀ
ױ
V ꢀꢀ̥ꢀ。ᄳ V ꢀА STR
CC
CC
Β℠ἡ
ꢂꢂᲗ✈ꢀἡᰁჯᖇЖ，
ࣀ
ᵄ᪗ꢀPWM ᶴᩓࡈ
Ŕ ֭Ljᩣꢅ℠ЖfἡটꢀSenseFET Ŕ໐Ȝꢀἡ，ୢ
ࣞ
ꢀ18 UVLOꢀ؏҈ꢀի V
(12 V)ꢀ៖，FSL4110LRꢀቂ૭
START
ᵃဘᚭļ。᪗᪩ҝយჯ，҈Ო؏ѿ்
Åᣟş ்
٬ё✈ѿ╧
SenseFETꢀŔრ͓，DŽАὨℴᜥⅬ ꢄ。
ᐠЊ。ȧᚎ 100 mA Ŕ⁰ꢀἡꢀ(I )
ἡটͥ᮸ꢀℋ FB
(3R + R = 24 kW)，Ϲlᥡ
ٱ
D2ꢀŔ℄ᥡꢀիॶꢈ 2.4 V。ꢂꢂ֭ꢀի (V )ꢀᡕ᪗ 2.4 Vꢀ៖ D1ꢀַℋ，
FB
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9
FSL4110LR
Drain
6, 7
Fault
occurs
Fault
removed
Power
on
VDS
VCC
VREF
IFB
OSC
LEB
IDLY
RDLY
Q
Q
S
R
3R
PWM
3
Gate
Driver
D1
D2
FB
CFB
R
Line
Comp.
t
RSENSE
100 ms
Delay
OLP
VCC
1
GND
VOLP
VAUX
VSTART
VHVREG
VSTOP
ꢉ 21. OLP ꢀᢿ
ᖈภŔ R ꢀȜईၴȯਾꢉ෯ꢂ5 MW。ზ៖
DLY
t
Fault condition
Restart time (1.6 s)
(t
)ꢀ
᪗⛻ჯ (3)ꢀᙱ٧
。 Normal
operation
Normal
operation
DLY
2
lnǒ1 *
Ǔ
tDLY + *RDLY CFB
ꢉ 19. ҈Ო؏ƽᒄỂꢤ
(eq. 3)
VCC * 2.4
᪗ᩍƽᒄ (OLP)
Њū：
᪗ᩍൺ)ꢈ
ࣀ
ዯტဘkꢄොೄᡕ᪗͖ᵃဘꢀၓŔ ᩍꢀἡ。ई᪩ҝእΕ⛻，ၴᒶֱƽᒄꢀᢿÅƽᒄ
SMPS。⌖，ՓşSMPSꢀईᵃဘ᪠ጜꢉ，?
்ई ᩍ᪗ꢃ᪗ӛꢉᒶֱ᪗ᩍƽᒄꢀᢿ。ꢈf̭Ϛ▐᪩
ҝ⛽ᆥᑑŔ࿅ļ⒖Ε，᪗ᩍƽᒄꢀᢿᚎᙱꢈ¥ई⛰ൺ
៖
ᒶֱ，Å̾ൺ᪩᠏ɼᇡእΕ᪨᠏ǯᵃŔ᪗ᩍእ Ε。ꢂꢂꢁΒ℠ἡѿ்，ἡট SenseFETꢀŔᣠଇ໐
Ȝꢀἡַ℠。ୢᩣϚѿ૧ᡕ᪗ᵄᣠଇѿ╧，ᩣϚꢀ
ի෦ℝೃᚎൺꢀիÅ⛻。᪩ί෯f᪗̩ꢀlᥡ
ٱ
Ŕ ꢀἡ，?ί෯f̩ꢀ
ࡈר
ꢀℋꢀἡ，®ᖰ▨f֭ ᄳ R
= 3 MW、C = 68 nF、V = 15 V、
FB CC
= 35 ms
DLY
t
DLY
\ OLP Ŕማზ៖：135 ms
ტဘ᪗ἡƽᒄ (AOCP)
ᄳᴁॷἡlᥡ
ٱ
ָիࡈ
ჵ௪ʽᢿ៖，͗ᣩᥡ▨ di/dtŔℱुꢀἡ
ईᣠ෯ො៖ͥἡট SenseFET。 ई᪩ҝტဘእΕ⛻，᪗ᩍƽᒄ⛽ᢃÅƽᒄ FSL4110LR
(֢ᒑ
ࣞ
22)；ࣀ
ꢈईᒶֱ OLPꢀ+Э，úᣩᅨଇŔꢀἡ ၴѻឝҀА SenseFETꢀ⛺。ͥ᮸ AOCPꢀꢀᢿୢ
ࣞ
23ꢀᐠ Њ。ᄳ
ױ
ѿ╧ SenseFETꢀၴ✈ᖰŻꢀℋŔꢀἡ。ꢀℋ ꢊֿŔꢀի⛾ꢅᚎ AOCPꢀꢀၓ᪫ጜᶴᩓ。ୢዿἫꢀ
ℋꢀիଇꢂAOCPꢀꢀၓ，෦
ױ
NORꢀ᧥ᥡᩣꢅᖰŻ▨ ǁ
ח
，ොೄ SMPSꢀ͓ឍ。 ꢀի (V )。ୢ V ꢀᡕϚ 2.4 V，ͥ᮸lᥡ
ٱ
D1 FB
FB
ַℋ，✄R ꢀŔꢀἡ (I
)რෙ C ꢀ̥ꢀ。ୢ
FB
DLY
DLY
֭ꢀիА 4.4 V，ͥ᮸
ࣚ
ൺზ៖ (t )ꢀრ
DELAY
ᙱᝐ。ୢ֭ꢀիई t
(100 ms)ꢀ
ৄᓡईᡕ DELAY
᪗ 4.4 VꢀŔȜ，რ͓ᚭļ෦ঘᵂ (֢ᒑ
ࣞ
20)。ͥ᮸ OLP ꢀᢿୢ
ࣞ
21ᐠЊ。 VCC
VAUX
VSTART
VHVREG
VCC
VAUX
VSTART
VHVREG
VSTOP
tRESTART
VSTOP
tDELAY
t
IDS
t
VFB
tDLY
4.4 V
2.4 V
tRESTART
t
t
IDS
AOCP
AOCP
Occurrence
Disappear
ꢉ 22. AOCP Ểꢤ
t
Overload
Overload
Disappear
Occurrence
ꢉ 20. OLP Ểꢤ
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10
FSL4110LR
Drain
6, 7
t
ᢿୢ
ࣞ
26ꢀᐠЊ。 ꢀͥℝೃॶ 1.9 V (֢ᒑ
ࣞ
25)。ͥ᮸ LOVPꢀꢀ RESTART
VREF
IFB
OSC
LEB
Q
Q
S
R
3R
PWM
FB
3
VCC
Gate
Driver
D1
D2
R
VAUX
VSTART
VHVREG
VSTOP
Line
Comp.
AOCP
RSENSE
tRESTART
AOCP
1
GND
VAOCP
t
IDS
ꢉ 23. AOCP ꢀᢿ
᪗իƽᒄ (OVP)
ୢᴁॷֿ֭ꢀᢿϚ▐ᜥⅬ⋪ᖅꢆꢇොೄ֭
t
ᢿᅤრᢿ，᪗̩ꢀ
ࡈר
ᡖijٱ
Ŕꢀἡπ.ָꢈ ꢈ。⌖
，V ꢀ෦Å
Ĝꢂ᪗ᩍእΕŔយჯᛠԧ，® LOVP
Disappear
LOVP
Occurrence
FB
ꢉşꢅᚎᣠଇ⃯ꢀἡἡ҈，DŽАᒶֱ᪗ᩍƽᒄ。ꢂ
ꢂ
ױ
ᩣϚֿᖰŻfᶴᐠ⇐்ᲟᣔૺŔ்Ჟ，ईᒶֱ᪗ ᩍƽᒄ+Э，ᩣϚꢀի
்ฑᡕϚfꢊൺꢀի，® ොೄᴁॷֿ
ࡈ
ꢄϛՏ。ꢈꢋᵂ᪩ҝእΕ，Თ✈fꢀOVP ꢉ 25. LOVP Ểꢤ
Rectified Line
Drain
6, 7
Input (VDC
)
VREF
IFB
OSC
ꢀ ᢿ 。 ဘ ， V ꢀ⛾ᩣ Ϛ ꢀ ի Ᏸ ᵃ ᶴ ， ၖ ✄
CC
Q
Q
S
R
3R
FSL4110LRꢀᲗ✈ꢀV ，⛽᠏DŽᖅơᖇᩣϚꢀի。ୢ
CC
PWM
FB
3
Gate
Driver
D1
D2
R
R1
ꢀV ꢀᡕ᪗ꢀ24ꢋ5ꢀV，ϹᒶֱꢀOVPꢀꢀᢿ，ොೄრ͓ᚭļঘ
CC
ᵂ。ꢈ̭ई ᵃဘ ࿅ļ ɖ⌖ ↠Ἓ ꢀOVP， V
Line
Comp.
LEB
LOVP
VIN
CC
ၴᚎᙱꢈईᵃဘእΕ⛻Įꢂꢀ24ꢋ5ꢀV。ͥ᮸ꢀOVPꢀꢀᢿୢ
ࣞ
24 ᐠЊ。 4
RSENSE
LOVP
R2
1
VINH
GND
CVIN
Drain
6, 7
ꢉ 26. LOVP ꢀᢿ
VREF
OSC
IFB
Q
Q
S
R
3R
PWM
យӛჯ (4) ᙱ
٧
ᩣꢅ᪗իꢀၓ RMS Ȝ。 FB
3
2
Gate
Driver
D1
D2
R
VINH R1
Line
Comp.
LEB
OVP
R2 +
(eq. 4)
VDC * VINH
RSENSE
VCC
OVP
ᨙᕎ⇐ᑑꢂϦիꢀℋŔℋȜ。ꢑᩍእΕ⛻，ᩓ ෯ŔℋȜúොೄLjෙᩓଇŔᅥᤚѿ૧。ꢈf̭᪩ҝ
እΕ，ᖈภş✈⛰ꢆπ MWꢀŔꢀℋ
ࡈ
。ꢈƽᓡԃൺ᪠ 1
GND
VOVP
ꢉ 24. OVP ꢀᢿ
ጜ，ş✈ℋȜꢈπ MWꢀŔꢀℋ
ࡈ
៖，ၴ
៖ई V IN
ჵ௪
٬
GND+ᖅ⛰ꢆȜꢈπŎ pFꢀŔꢀ (C )。
VIN
⋍͓ឍ (TSD)
SenseFET
٬ᖇЖ
IC ꢀᏰई
⛰ꢌꢉយƟf᪠Ἣ SenseFETꢀŔꢁႆ。ᄳণꢁᡕ᪗ 140°Cꢀ៖，෦↠Ἓ⋍͓
ឍ。ᄳꢁႆई t
FSL4110LR。
ꢥั
ࡈ
ᰁꢢ (1.6 s) ͥℝೃ 60°C ៖，෦Ო؏
RESTART
ᔏั
ࡈ
⍡╧ईͥ᮸ᚎਾ，✄FSL4110LRꢀ͗ᣩ⅟ᤚ⍡ ╧Ể҈ѿ்，ୢ
ࣞ
27ꢀᐠЊ。რ͓⍡╧ŔỂ҈෦்ᲟϦ ईᶴ EMIꢀἫꢒᚎ૧ἫᅷŔဆඝᣔඝŔ⍡╧ꢓ
ࣔ
ͥ， ࣀ
்૿ί EMI。⍡╧ָӶꢓࣔ
ईͥ᮸ࣚ
ൺ； ⌖，⍡╧ꢓ
ࣔ
Ŕꢔᓉꢂ᮸֭ꢀի٬ͥ
᮸↠ᔏ ั
ࡈ
͑
⅟ᤚΓൺ。⅟ᤚꢔᓉŔრ͓⍡╧෦ EMIꢀࡊ
ૐ ᣩᜨऐϦईრ͓⍡╧ꢕꢖ，ၖ̡ꢗş✈͗ᣩᏰᤌᜨ
ƚŔꢀዿ
ࡈ
，⛽᠏ἡᩣꢅꢀ⁰Ểࡈ
，᥅ᢃ͈ ◣ EMIꢀᑑḢ。
এᢿ᪗իƽᒄ (LOVP)
ୢএᢿᩣꢅꢀիҀ᪗▨，▨এᢿᩣꢅꢀիई
ꢆ
ߋ
য⛺⛿▨իၴѻ。ꢈƽᒄ SMPSꢀ⛽ֱ⛿᪩ҝტ ဘእΕ，ӥᓌfLOVPꢀѿ்。ӥᓌᲗ✈Ϧիꢀℋ᪠Ἣ
V ꢀꢀի。ᄳ V ꢀꢀի▨ꢂ2.0 Vꢀ៖，᪩ҝእΕꢍꢎ
IN
IN
ꢈϚ▐ტဘꢏꢐ，PWMꢀრ͓͓ឍ，DŽೃ V ꢀꢀիई
IN
www.onsemi.cn
11
FSL4110LR
VO
IDS
several
mseconds
tS = 1/fS
tS
t
t
VFB
t
Dt
fS
0.5 V
0.4 V
fSW
MAX
+ 1/2DfS
IDS
MAX
no repetition
− 1/2DfS
fS
several
miliseconds
t
t
ꢉ 27. ⍡╧Ể҈Ểꢤ
VDS
ᨿ؏҈
ͥ᮸ᨿ؏҈ꢀᢿ؏҈
，úꢘፂᖰ▨ SenseFETꢀꢀ ἡ。͘५ᨿ؏҈៖ꢈ20 ms，ୢ
ࣞ
28ꢀᐠЊ，؏҈᪗ ӛꢉ̡ꢗ SenseFETꢀꢀἡꢙ。ᩣꢅѿ╧რ͓
ࡈ
ꢄŔꢁඝҀ，®ლ֛
ר
ָիࡈ
、ꢀዿࡈ
٬
ꢀ
ࡈ
Ŕᵃ̾࿅ļꢄ。ᩣϚꢀࡈ
⛺Ŕꢀի Ҁ，®ꢚꢄऐლ֛ᐠ⇐ŔᩣϚꢀի。ᨿ؏҈?ᣩ҉
ꢂꢋᵂָի
ࡈ
ꢛ٬
，ၖℝĮᴁॷlᥡٱ
⛺Ŕၴѻ。 t
Switching
disabled
Switching
disabled
ꢉ 29. ᴧᰁჯ࿅ļ
এᢿጵꢦ
ᐠᣩრ͓
ࡈ
ꢄᯍᣩ͖ࣚ
ᣩŔĀᚍზ。ᵄĀᚍზ ෦ොೄൺ)ꢈt ꢀŔꢀἡ℠Жზ。ꢂꢂꢀἡ℠Жზ
2.5 ms
CLD
，
ࣀ
ᵄĮᩣꢅꢀի٬
▨ᩣꢅꢀի+സईꢀἡ t
CLD
ILIM
໐Ȝ࿎ტ。ꢀἡ໐Ȝ࿎ტ⛾ᩣꢅꢀի+Ŕ࿎ტLj
͓，ᩣꢅꢀիꢉŔꢝꢞඝ，ꢀἡ໐ȜŔ࿎ტꢞଇ。
⛽ꢟᩣꢅꢀի᠏ૺ，ꢈƽᓡ⛰ꢆԃൺŔꢀἡ໐
Ȝ，⇐᪫ጜএᢿጵɟ。FSL4110LRꢀ͗ᣩএᢿጵɟ，
ࣀ
ᵄ▨ᩣꢅꢀիŔǯൾ໐Ȝ
ĜꢂĮᩣꢅꢀիŔǯൾ໐ Soft start envelope
Ȝ。t ꢀᜨၴ
ꢍᇝ5，ୢࣞ
30ꢀᐠЊ。 CLD
Drain Current
t
8−Steps
ꢉ 28. ꢊ᮸ᨿ؏҈
ᴧᰁჯ࿅ļ
ꢈᣠଇӛႆऐℝĮᅥᤚᰁჯ⛻Ŕѿ૧，FSL4110LR
ú᪫ꢅՑֱᰁჯ。⅟ȐᩍℝĮ，֭ꢀի?úℝ
Į。ᄳ֭ꢀիℝೃ V
(400 mV)ꢀÅ⛻៖，
ࡈ
ꢄ BURL
IDRAIN(460 VAC): 100 mA/div
҈᪫ꢅᴧᰁჯ，ୢ
ࣞ
29ꢀᐠЊ。ᵄ៖，რ͓ᚭļ෦ ȼᵂ，ᩣϚꢀիრℝĮ，ℝĮŔꢜ╧ֶΓꢂᅥᤚꢀ
ἡᩍ。᪩úොೄ֭ꢀի⛺ԧ。⛰ំᵄȜᡕ᪗
VBURH (500 mV)，რ͓ᚭļ෦ቂ૭。֭ꢀի⅟+
ℝĮ，ᵄ᪗ӛᲝ૭。ᴧᰁჯúᣟş்
٬
ё✈ SenseFETꢀŔრ͓ᚭļ，®ℝĮᅥᤚᰁჯ⛻Ŕრ͓ᔿ
૧。
׆
，᪨ίf
،ࡊ
ૐᨿᴧ。 500 ns/div
ꢉ 30. ILIMIT Ểꢤ(85 VAC ⛾460 VAC
)
www.onsemi.cn
12
FSL4110LR
ᙲꢧꢨ
ࡈ
Ö০ꢏ ᩣꢪꢟ╧ጸ (ꢀꢁ 12)
45~460 V 85~460 V
R
AC
AC
DS(ON)
†
(ꢀꢁ 13)
(ꢀꢁ 13)
(ꢒꢓꢔ)
ꢩ᎕
࿅ļণꢁ
℠ἡ
Shipping
FSL4110LRN PDIP−7 (PDIP−8 LESS PIN 6) −40°C~125°C
0.52 A
10 W
4 W (ꢀꢁ 14) 9 W (ꢀꢁ 14) 3000 Units /
(7−DIP)
Tube
(Pb−Free)
FSL4110LRLX
PDIP7 MINUS PIN 6 GW
(7−LSOP)
1000 / Tape
& Reel
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
12.꣯꣰ꢖꣻЖᩣϚꢀ꤫。
13.50°C ꤓꤔ꣰꣠⛻꣄ꥀꤱꥁꥂꢄŔꥃꥄ꣨ꢀ꤫。
14.ȯի꣖꣗ꢑ。
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13
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PDIP−7 (PDIP−8 LESS PIN 6)
CASE 626A
ISSUE C
DATE 22 APR 2015
SCALE 1:1
NOTES:
D
A
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
E
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACK-
AGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
H
8
5
4
E1
1
6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE
LEADS UNCONSTRAINED.
7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
LEADS, WHERE THE LEADS EXIT THE BODY.
8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
NOTE 8
c
b2
B
END VIEW
WITH LEADS CONSTRAINED
NOTE 5
TOP VIEW
INCHES
DIM MIN MAX
−−−−
A1 0.015
MILLIMETERS
A2
A
MIN
−−−
0.38
2.92
0.35
MAX
5.33
−−−
4.95
0.56
e/2
A
0.210
−−−−
NOTE 3
A2 0.115 0.195
L
b
b2
C
0.014 0.022
0.060 TYP
0.008 0.014
1.52 TYP
0.20
9.02
0.13
7.62
6.10
0.36
10.16
−−−
8.26
7.11
D
0.355 0.400
SEATING
PLANE
D1 0.005
0.300 0.325
E1 0.240 0.280
−−−−
A1
D1
E
C
M
e
eB
L
0.100 BSC
−−−− 0.430
0.115 0.150
−−−− 10°
2.54 BSC
−−−
2.92
−−−
10.92
3.81
10°
e
eB
8X
b
END VIEW
M
NOTE 6
M
M
M
0.010
C A
B
SIDE VIEW
GENERIC
MARKING DIAGRAM*
XXXXXXXXX
AWL
YYWWG
XXXX = Specific Device Code
A
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
WL
YY
WW
G
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON11774D
PDIP−7 (PDIP−8 LESS PIN 6)
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PDIP7 MINUS PIN 6 GW
CASE 707AA
ISSUE O
DATE 31 JAN 2017
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13755G
PDIP7 MINUS PIN 6 GW
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
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, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
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