FSQ0365RN [ONSEMI]
650V 集成电源开关，带谷开关控制，用于 19W 离线反激转换器;
| 型号： | FSQ0365RN |
| 厂家： | 
ONSEMI |
| 描述： | 650V 集成电源开关，带谷开关控制，用于 19W 离线反激转换器 开关 电源开关 光电二极管 转换器 |
| 文件： | 总21页 (文件大小：709K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Green Mode Power Switch
for Valley Switching
Converter - Low EMI and
High Efficiency
FSQ0365, FSQ0265,
FSQ0165, FSQ321
www.onsemi.com
Description
A Valley Switching Converter generally shows lower EMI and
higher power conversion efficiency than a conventional
hard−switched converter with a fixed switching frequency. The
FSQ−series is an integrated Pulse−Width Modulation (PWM)
®
PDIP−8
CASE 626−05
PDIP8 GW
CASE 709AJ
controller and SENSEFET specifically designed for valley switching
operation with minimal external components. The PWM controller
includes an integrated fixed−frequency oscillator, under−voltage
lockout, Leading−Edge Blanking (LEB), optimized gate driver,
internal soft−start, temperature−compensated precise current sources
for loop compensation, and self−protection circuitry.
Compared with discrete MOSFET and PWM controller solutions,
the FSQ−series reduces total cost, component count, size and weight;
while simultaneously increasing efficiency, productivity, and system
reliability. This device provides a basic platform for cost−effective
designs of valley switching fly−back converters.
MARKING DIAGRAM
$Y&E&Z&2&K
FSQxxxx
$Y
&E
&Z
= ON Semiconductor Logo
= Designated Space
= Assembly Plant Code
Features
&2
&K
FSQxxxx
= 2−Digit Date code format
= 2−Digits Lot Run Traceability Code
= Specific Device Code Data
• Optimized for Valley Switching Converter (VSC)
• Low EMI through Variable Frequency Control and Inherent
Frequency Modulation
• High Efficiency through Minimum Voltage Switching
• Narrow Frequency Variation Range Over Wide Load and Input
Voltage Variation
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
• Advanced Burst−Mode Operation for Low Standby Power
Consumption
Applications
• Pulse−by−Pulse Current Limit
• Protection Functions: Overload Protection (OLP), Over−Voltage
Protection (OVP), Abnormal Over−Current Protection (AOCP),
Internal Thermal Shutdown (TSD)
• Power Supplies for DVD Player,
DVD Recorder, Set−Top Box
• Adapter
• Under−Voltage Lockout (UVLO) with Hysteresis
• Auxiliary Power Supply for PC, LCD TV,
• Internal Startup Circuit
and PDP TV
• Internal High−Voltage SENSEFET: 650 V
• Built−in Soft−Start: 15 ms
Related Application Notes
• http://www.onsemi.com/pub/Collateral/AN−4137.pdf.pdf
• http://www.onsemi.com/pub/Collateral/AN−4141.pdf.pdf
• http://www.onsemi.com/pub/Collateral/AN−4150.pdf.pdf
• https://www.onsemi.com/pub/Collateral/AN−4134.PDF
© Semiconductor Components Industries, LLC, 2017
1
Publication Order Number:
December, 2020 − Rev. 3
FSQ0365/D
FSQ0365, FSQ0265, FSQ0165, FSQ321
Table 1. ORDERING INFORMATION
(1)
Maximum Output Table
(2)
230 V + 15%
85 − 265 V
AC
AC
Open
Frame
Open
Frame
Operating
Temperature
Current
Limit
R
DS(ON)
(Max.) Adapter
(4)
(4)
(3)
(3)
†
Adapter
Part Number
FSQ321
Package
Shipping
3000 / Tube
PDIP−8
−40 to +85°C
−40 to +85°C
−40 to +85°C
−40 to +85°C
0.6 A
0.9 A
1.2 A
1.5 A
19 W
10 W
6 W
8W
12W
7W
10W
FSQ321LX
FSQ0165RN
PDIP8 GW 1000 / Tape & Reel
PDIP−8 3000 / Tube
10W
15W
20W
25W
9W
11W
13W
13W
16W
19W
FSQ0165RLX PDIP8 GW 1000 / Tape & Reel
FSQ0265RN PDIP−8 3000 / Tube
FSQ0265RLX PDIP8 GW 1000 / Tape & Reel
FSQ0365RN PDIP−8 3000 / Tube
FSQ0365RLX PDIP8 GW 1000 / Tape & Reel
14W
4.5 W
17.5W
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
1. The junction temperature can limit the maximum output power.
2. 230 V or 100/115 V with voltage doubler. The maximum power with CCM operation.
AC
AC
3. Typical continuous power in a non−ventilated, enclosed adapter measured at 50°C ambient temperature.
4. Maximum practical continuous power in an open−frame design at 50°C ambient temperature.
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2
FSQ0365, FSQ0265, FSQ0165, FSQ321
Application Circuit
Vo
AC
IN
Vstr
Drain
PWM
Sync
GND
Vfb
Vcc
Figure 1. Typical Flyback Application
Internal Block Diagram
Vstr
5
Vcc
2
Sync
4
Drain
6
7 8
+
−
OSC
0.7V/0.2V
+
−
+
−
Vref
0.35/0.55
VBurst
VCC Good
Vref
VCC
8V/12V
IFB
Idelay
PWM
Vfb
3R
S
R
Q
Q
3
Gate
Driver
Soft−
Start
LEB
200ns
R
AOCP
1
TSD
S
R
Q
VOCP
6V
GND
VSD
(1.1V )
2.5ms Time
Q
Delay
Sync
6V
Vovp
VCC Good
FSQ0365RN Rev.00
Figure 2. Internal Block Diagram
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3
FSQ0365, FSQ0265, FSQ0165, FSQ321
Pin Assignments
GND
Drain
V
Drain
Drain
CC
8−DIP
8−LSOP
V
FB
V
STR
Sync
Figure 3. Pin Configuration (Top View)
Table 2. PIN DEFINITIONS
Pin#
Name
Description
1
GND
SENSEFET source terminal on primary side and internal control ground.
2
V
CC
Positive supply voltage input. Although connected to an auxiliary transformer winding, current is supplied
from pin 5 (Vstr) via an internal switch during startup (see Figure 2).
It is not until V reaches the UVLO upper threshold (12 V) that the internal startup switch opens and de-
CC
vice power is supplied via the auxiliary transformer winding.
3
Vfb
The feedback voltage pin is the non−inverting input to the PWM comparator. It has a 0.9 mA current source
connected internally while a capacitor and opto-coupler are typically connected externally. There is a time
delay while charging external capacitor C from 3 V to 6 V using an internal 5 μA current source. This delay
fb
prevents false triggering under transient conditions, but still allows the protection mechanism to operate
under true overload conditions.
4
5
Sync
Vstr
This pin is internally connected to the sync−detect comparator for valley switching. Typically the voltage of
the auxiliary winding is used as Sync input voltage and external resistors and capacitor are needed to make
delay to match valley point. The threshold of the internal sync comparator is 0.7 V / 0.2 V.
This pin is connected to the rectified AC line voltage source. At startup, the internal switch supplies internal
bias and charges an external storage capacitor placed between the Vcc pin and ground. Once the V
reaches 12 V, the internal switch is opened.
CC
6, 7, 8
Drain
The drain pins are designed to connect directly to the primary lead of the transformer and are capable of
switching a maximum of 650 V. Minimizing the length of the trace connecting these pins to the transformer
decreases leakage inductance.
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4
FSQ0365, FSQ0265, FSQ0165, FSQ321
Table 3. ABSOLUTE MAXIMUM RATINGS (T = 25°C unless otherwise specified)
A
Symbol
Parameter
Min.
Max.
Unit
V
500
650
V
V
V
V
V
A
Vstr Pin Voltage
STR
V
Drain Pin Voltage
Supply Voltage
DS
V
20
CC
V
−0.3
9.0
Feedback Voltage Range
Sync Pin Voltage
FB
V
Sync
−0.3
9.0
I
12.0
Drain Current Pulsed (Note 5)
Single Pulsed Avalanche Energy (Note 6)
Total Power Dissipation
FSQ0365
FSQ0265
FSQ0165
FSQ321
DM
8.0
4.0
1.5
E
230
mJ
FSQ0365
FSQ0265
FSQ0165
FSQ321
AS
140
50
10
P
1.5
Internally Limited
+85
W
°C
°C
°C
D
T
−40
−40
−55
Recommended Operating Junction Temperature
Operating Ambient Temperature
Storage Temperature
J
T
A
T
STG
+150
ESD
CLASS 1C
CLASS B
Human Body Model; JESD22−A114
Machine Model; JESD22−A115
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
5. Repetitive rating: pulse width limited by maximum junction temperature.
6. L = 51 mH, starting T = 25°C.
J
Table 4. THERMAL IMPEDANCE
Symbol
Parameter
Value
Unit
8−DIP (Note 7)
80
20
35
°C/W
q
Junction−to−Ambient Thermal Resistance (Note 8)
Junction−to−Case Thermal Resistance (Note 9)
Junction−to−Top Thermal Resistance (Note 10)
JA
q
JC
q
JT
7. All items are tested with the standards JESD 51−2 and 51−10 (DIP)
8. Free−standing with no heat−sink, under natural convection
9. Infinite cooling condition − refer to the SEMI G30−88
10.Measured on the package top surface.
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5
FSQ0365, FSQ0265, FSQ0165, FSQ321
Table 5. ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise specified)
A
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
SENSEFET Section
BV
I
650
V
A
W
Drain−Source Breakdown Voltage
Zero−Gate−Voltage Drain Current
V
V
= 0 V, I = 100 mA
DSS
CC
D
100
4.5
= 650 V
DSS
DS
3.5
5.0
R
FSQ0365
FSQ0265
FSQ0165
FSQ321
Drain−Source On−
State Resistance
(Note 11)
T = 25°C, I = 0.5 A
J
DS(ON)
D
6.0
8.0
10.0
19.0
14.0
315
550
250
162
47
C
pF
pF
pF
ns
ns
ns
ns
FSQ0365
FSQ0265
FSQ0165
FSQ321
Input Capacitance
Output Capacitance
V
= 0 V, V = 25 V, f = 1 MHz
ISS
GS
GS
GS
DD
DD
DD
DD
DS
C
C
t
FSQ0365
FSQ0265
FSQ0165
FSQ321
V
V
V
V
V
V
= 0 V, V = 25 V, f = 1 MHz
OSS
DS
38
25
18
9.0
17.0
10.0
3.8
11.2
20.0
12.0
9.5
34
FSQ0365
FSQ0265
FSQ0165
FSQ321
Reverse Transfer
Capacitance
= 0 V, V = 25 V, f = 1 MHz
RSS
DS
FSQ0365
FSQ0265
FSQ0165
FSQ321
Turn−On Delay
= 350 V, I = 25 mA
d(on)
D
t
FSQ0365
FSQ0265
FSQ0165
FSQ321
Rise Time
= 350 V, I = 25 mA
r
D
15
4
19
28.2
55.0
30.0
33.0
32
t
FSQ0365
FSQ0265
FSQ0165
FSQ321
Turn−Off Delay
= 350 V, I = 25 mA
d(off)
D
t
FSQ0365
FSQ0265
FSQ0165
FSQ321
Fall Time
= 350 V, I = 25 mA
f
D
25
10
42
Burst−Mode Section
V
0.45
0.25
0.55
0.35
0.65
0.45
V
V
Burst−Mode Voltage
T = 25°C, t = 200 ns (Note 12)
J PD
BURH
V
BURL
V
200
mV
BUR(HYS)
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FSQ0365, FSQ0265, FSQ0165, FSQ321
Table 5. ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise specified) (continued)
A
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
Control Section
t
10.5
6.35
13.2
7.5
12.0
7.06
15.0
8.2
13.5
7.77
16.8
ms
ms
ms
ms
ms
%
Maximum On Time1
All but FSQ321 T = 25°C
J
ON.MAX1
ON.MAX2
t
Maximum On Time2
Blanking Time1
FSQ321
T = 25°C
J
t
B1
All but FSQ321
FSQ321
t
B2
Blanking Time2
t
W
3.0
Detection Time Window
T = 25°C, V
J
= 0 V
sync
Df
S
5
10
1100
0
Switching Frequency Variation (Note 14)
Feedback Source Current
Minimum Duty Cycle
−25°C < T < 85°C
J
I
FB
700
900
mA
%
V
V
= 0 V
= 0 V
FB
D
MIN
FB
V
UVLO Threshold Voltage
After Turn−on
11
7
12
8
13
9
V
V
START
V
STOP
t
15
ms
Internal Soft−Start Time 1 All but FSQ321
Internal Soft−Start Time 2 FSQ321
S/S1
With Free−Running Frequency
With Free−Running Frequency
t
10
ms
S/S2
Protection Section
I
A
Peak Current Limit
1.32
1.06
0.8
1.50
1.20
0.9
1.68
1.34
1.0
FSQ0365
FSQ0265
FSQ0165
FSQ321
T = 25°C, di/dt = 240 mA/ms
LIM
J
T = 25°C, di/dt = 200 mA/ms
J
T = 25°C, di/dt = 175 mA/ms
J
0.53
0.60
0.67
T = 25°C, di/dt = 125 mA/ms
J
V
5.5
4.0
6.0
5.0
200
6.0
3
6.5
6.0
V
mA
ns
V
Shutdown Feedback Voltage
Shutdown Delay Current
Leading−Edge Blanking Time
Over−Voltage Protection
V
= 15 V
= 5 V
SD
CC
FB
I
V
DELAY
(13)
t
LEB
V
t
5.5
2
6.5
4
V
CC
= 15 V, V = 2 V
OVP
FB
ms
°C
Over−Voltage Protection Blanking Time
Thermal Shutdown Temperature (Note 13)
OVP
T
SD
125
140
155
Sync Section
V
Sync Threshold Voltage
0.55
0.14
0.70
0.20
300
0.85
0.26
V
V
SH
V
SL
t
ns
Sync Delay Time (Notes 13, 14)
Sync
Total Device Section
I
1
3
5
mA
Operating Supply Current
(Control Part Only)
V
V
= 15 V
OP
CC
I
270
0.65
360
450
1.00
mA
Start Current
= V
− 0.1 V
START
CC
START
(Before V Reaches V
)
CC
START
I
0.85
26
mA
V
Startup Charging Current
V
CC
= 0 V, V
= Minimum 40 V
CH
STR
V
STR
Minimum V
Supply Voltage
STR
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
11. Pulse test: Pulse−Width = 300 ms, duty = 2%
12.Propagation delay in the control IC.
13.Though guaranteed, it is not 100% tested in production.
14.Includes gate turn−on time.
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FSQ0365, FSQ0265, FSQ0165, FSQ321
TYPICAL PERFORMANCE CHARACTERISTICS
(Characteristics graphs are normalized at T = 25°C)
A
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.2
1.0
0.8
0.6
0.4
0.2
0.0
−25
0
25
50
75
100
125
−25
0
25
50
75
100
125
Temperature [ °C]
Temperature [ °C]
Figure 4. Operating Supply Current (IOP) vs. TA
Figure 5. UVLO Start Threshold Voltage (VSTART
vs. TA
)
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.2
1.0
0.8
0.6
0.4
0.2
0.0
−25
0
25
50
75
100
125
−25
0
25
50
75
100
125
Temperature [ °C]
Temperature [ °C]
Figure 6. UVLO Stop Threshold Voltage (VSTOP
vs. TA
)
Figure 7. Startup Charging Current (ICH) vs. TA
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.2
1.0
0.8
0.6
0.4
0.2
0.0
−25
0
25
50
75
100
125
−25
0
25
50
75
100
125
Temperature [ °C]
Temperature [ °C]
Figure 8. Initial Switching Frequency (fS) vs. TA
Figure 9. Maximum On Time (tON.MAX) vs. TA
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FSQ0365, FSQ0265, FSQ0165, FSQ321
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
(Characteristics graphs are normalized at T = 25°C)
A
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.2
1.0
0.8
0.6
0.4
0.2
0.0
−25
0
25
50
75
100
125
−25
0
25
50
75
100
125
Temperature [ °C]
Temperature [ °C]
Figure 10. Blanking Time (tB) vs. TA
Figure 11. Feedback Source Current (IFB) vs. TA
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.2
1.0
0.8
0.6
0.4
0.2
0.0
−25
0
25
50
75
100
125
−25
0
25
50
75
100
125
Temperature [ °C]
Temperature [ °C]
Figure 12. Shutdown Delay Current (IDELAY) vs. TA
Figure 13. Burst Mode High Threshold Voltage
(Vburh) vs. TA
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.2
1.0
0.8
0.6
0.4
0.2
0.0
−25
0
25
50
75
100
125
−25
0
25
50
75
100
125
Temperature [ °C]
Temperature [ °C]
Figure 14. Burst Mode Low Threshold Voltage
(Vburl) vs. TA
Figure 15. Peak Current Limit (ILIM) vs. TA
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FSQ0365, FSQ0265, FSQ0165, FSQ321
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
(Characteristics graphs are normalized at T = 25°C)
A
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.2
1.0
0.8
0.6
0.4
0.2
0.0
−25
0
25
50
75
100
125
−25
0
25
50
75
100
125
Temperature [ °C]
Temperature [ °C]
Figure 16. Sync High Threshold (VSH) vs. TA
Figure 17. Sync Low Threshold (VSL) vs. TA
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.2
1.0
0.8
0.6
0.4
0.2
0.0
−25
0
25
50
75
100
125
−25
0
25
50
75
100
125
Temperature [ °C]
Temperature [ °C]
Figure 18. Shutdown Feedback Voltage (VSD
vs. TA
)
Figure 19. Over−Voltage Protection (VOP) vs. TA
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FSQ0365, FSQ0265, FSQ0165, FSQ321
FUNCTIONAL DESCRIPTION
R
sense
resistor would lead to incorrect feedback operation in
the Current Mode PWM control. To counter this effect, the
power switch employs a leading−edge blanking (LEB)
circuit. This circuit inhibits the PWM comparator for a short
Startup
At startup, an internal high−voltage current source
supplies the internal bias and charges the external capacitor
(C ) connected to the V pin, as illustrated in Figure 20.
a
time (t ) after the SENSEFET is turned on.
LEB
CC
When V reaches 12 V, the power switch begins switching
CC
Vref
VCC
Idelay
and the internal high−voltage current source is disabled. The
power switch continues its normal switching operation and
the power is supplied from the auxiliary transformer
IFB
VFB
VO
SENSEFET
OSC
3
FOD817A
D1
D2
CB
winding unless V goes below the stop voltage of 8 V.
3R
R
CC
+
Gate
driver
VDC
VFB*
KA431
−
Ca
OLP
Rsense
VSD
FSQ0365RN Rev. 00
VCC
Vstr
2
5
Figure 21. Pulse−Width−Modulation Circuit
Synchronization
ICH
Vref
The FSQ−series employs a valley switching technique to
minimize the switching noise and loss. The basic waveforms
of the valley switching converter are shown in Figure 22. To
minimize the MOSFET’s switching loss, the MOSFET
should be turned on when the drain voltage reaches its
minimum value, as shown in Figure 22. The minimum drain
8V/12V
VCC good
Internal
Bias
FSQ0365RN Rev.00
Figure 20. Startup Circuit
voltage is indirectly detected by monitoring the V
winding voltage, as shown in Figure 22.
CC
Feedback Control
Power Switch employs Current Mode control, as shown
in Figure 21. An opto−coupler (such as FOD817A) and
shunt regulator (such as KA431) are often used to
implement the feedback network. Comparing the feedback
Vds
VRO
voltage with the voltage across the R
resistor makes it
SENSE
VRO
VDC
possible to control the switching duty cycle. When the
reference pin voltage of the shunt regulator exceeds the
internal reference voltage of 2.5 V, the opto−coupler LED
current increases, pulling down the feedback voltage and
reducing the duty cycle. This event typically occurs when
input voltage is increased or output load is decreased.
tF
Vsync
V
ovp (6V)
0.7V
Pulse−by−Pulse Current Limit
Because Current Mode control is employed, the peak
current through the SENSEFET is limited by the inverting
0.2V
300ns Delay
input of PWM comparator (V *), as shown in Figure 21.
MOSFET Gate
ON
FB
Assuming that the 0.9mA current source flows only through
the internal resistor (3R + R = 2.8 kW), the cathode voltage
of diode D2 is about 2.5 V. Since D1 is blocked when the
ON
feedback voltage (V ) exceeds 2.5V, the maximum voltage
FB
FSQ0365RN Rev.00
of the cathode of D2 is clamped at this voltage, clamping
V
*. Therefore, the peak value of the current through the
FB
Figure 22. Valley Resonant Switching Waveforms
Protection Circuits
SENSEFET is limited.
Leading−Edge Blanking (LEB)
The FSQ−series has several self−protective functions,
such as Overload Protection (OLP), Abnormal
Over−Current protection (AOCP), Over−Voltage Protection
(OVP), and Thermal Shutdown (TSD). All the protections
At the instant the internal SENSEFET is turned on, a
high−current spike usually occurs through the SENSEFET,
caused by primary−side capacitance and secondary−side
rectifier reverse recovery. Excessive voltage across the
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FSQ0365, FSQ0265, FSQ0165, FSQ321
are implemented as Auto−Restart Mode. Once the fault
condition is detected, switching is terminated and the
SENSEFET remains off. This causes V to fall. When V
shutdown is the time required to charge CB from 2.8 V to
6 V with 5 mA. A 20 ~ 50 ms delay is typical for most
applications.
CC
CC
falls down to the Under−Voltage Lockout (UVLO) stop
voltage of 8 V, the protection is reset and the startup circuit
FSQ0365RN Rev.00
VFB
Overload protection
6.0V
charges the V capacitor. When the V reaches the start
voltage of 12 V, the FSQ−series resumes normal operation.
If the fault condition is not removed, the SENSEFET
CC
CC
remains off and V drops to stop voltage again. In this
CC
manner, the auto−restart can alternately enable and disable
the switching of the power SENSEFET until the fault
condition is eliminated. Because these protection circuits
are fully integrated into the IC without external components,
the reliability is improved without increasing cost.
2.8V
t12= CFB*(6.0−2.8)/dIelay
t1
t2
t
Fault
Figure 24. Overload Protection
occurs
Fault
removed
Power
on
VDS
Abnormal Over−Current Protection (AOCP)
When the secondary rectifier diodes or the transformer
pins are shorted, a steep current with extremely high−di/dt
can flow through the SENSEFET during the LEB time.
Even though the FSQ−series has Overload Protection
(OLP), it is not enough to protect the FSQ−series in that
abnormal case, since severe current stress is imposed on the
SENSEFET until OLP triggers. The FSQ−series has an
internal Abnormal Over−Current Protection (AOCP) circuit
as shown in Figure 25. When the gate turn−on signal is
applied to the power SENSEFET, the AOCP block is
enabled and monitors the current through the sensing
resistor. The voltage across the resistor is compared with a
preset AOCP level. If the sensing resistor voltage is greater
than the AOCP level, the set signal is applied to the latch,
resulting in the shutdown of the SMPS.
VCC
12V
8V
t
Normal
operation
Fault
situation
Normal
operation
FSQ0365RN Rev. 00
Figure 23. Auto−Restart Protection Waveforms
Overload Protection (OLP)
3R
OSC
Overload is defined as the load current exceeding its
normal level due to an unexpected abnormal event. In this
situation, the protection circuit should trigger to protect the
SMPS. However, even when the SMPS is in the normal
operation, the overload protection circuit can be triggered
during load transition. To avoid this undesired operation, the
overload protection circuit is designed to trigger only after
a specified time to determine whether it is a transient
situation or a true overload situation. Because of the
pulse−by−pulse current limit capability, the maximum peak
current through the SENSEFET is limited, and therefore the
maximum input power is restricted with a given input
voltage. If the output consumes more than this maximum
S
R
Q
Q
PWM
Gate
driver
LEB
200ns
R
Rsense
+
−
1
AOCP
FSQ0365RN Rev.00
GND
VOCP
Figure 25. Abnormal Over−Current Protection
Over−Voltage Protection (OVP)
If the secondary−side feedback circuit malfunctions or a
solder defect causes an opening in the feedback path, the
current through the opto−coupler transistor becomes almost
power, the output voltage (V ) decreases below the set
O
voltage. This reduces the current through the opto−coupler
LED, which also reduces the opto−coupler transistor
zero. Then V climbs up in a similar manner to the overload
FB
current, thus increasing the feedback voltage (V ). If V
FB
FB
situation, forcing the preset maximum current to be supplied
to the SMPS until the overload protection triggers. Because
more energy than required is provided to the output, the
output voltage may exceed the rated voltage before the
exceeds 2.8 V, D1 is blocked and the 5 mA current source
starts to charge CB slowly up to V . In this condition, V
CC
FB
continues increasing until it reaches 6 V, when the switching
operation is terminated, as shown in Figure 24. The delay for
www.onsemi.com
12
FSQ0365, FSQ0265, FSQ0165, FSQ321
overload protection triggers, resulting in the breakdown of
VO
set
the devices in the secondary side. To prevent this situation,
an OVP circuit is employed. In general, the peak voltage of
the sync signal is proportional to the output voltage and the
FSQ−series uses a sync signal instead of directly monitoring
the output voltage. If the sync signal exceeds 6 V, an OVP
is triggered, shutting down the SMPS. To avoid undesired
triggering of OVP during normal operation, the peak voltage
of the sync signal should be designed below 6 V.
VO
VFB
0.55V
0.35V
IDS
Thermal Shutdown (TSD)
The SENSEFET and the control IC are built in one
package. This makes it easy for the control IC to detect the
abnormal over temperature of the SENSEFET. If the
temperature exceeds ~150°C, the thermal shutdown
triggers.
VDS
Soft−Start
An internal soft−start circuit increases PWM comparator
inverting input voltage with the SENSEFET current slowly
after it starts up. The typical soft−start time is 15 ms. The
pulsewidth to the power switching device is progressively
increased to establish the correct working conditions for
transformers, inductors, and capacitors. The voltage on the
output capacitors is progressively increased with the
intention of smoothly establishing the required output
voltage. This helps prevent transformer saturation and
reduces stress on the secondary diode during startup.
time
Switching
disabled
Switching
disabled
t4
t2 t3
t1
FSQ0365RN Rev.00
Figure 26. Waveforms of Burst Operation
Switching Frequency Limit
To minimize switching loss and Electromagnetic
Interference (EMI), the MOSFET turns on when the drain
voltage reaches its minimum value in valley switching
operation. However, this causes switching frequency to
increases at light load conditions. As the load decreases, the
peak drain current diminishes and the switching frequency
increases. This results in severe switching losses at
light−load condition, as well as intermittent switching and
audible noise. Because of these problems, the valley
switching converter topology has limitations in a wide range
of applications.
Burst Operation
To minimize power dissipation in Standby Mode, the
power switch enters Burst−Mode operation. As the load
decreases, the feedback voltage decreases. As shown in
Figure 26, the device automatically enters Burst Mode when
the feedback voltage drops below V
(350 mV). At this
BURL
point, switching stops and the output voltages start to drop
at a rate dependent on standby current load. This causes the
To overcome this problem, FSQ−series employs a
frequency−limit function, as shown in Figure 27 and
Figure 28. Once the SENSEFET is turned on, the next
feedback voltage to rise. Once it passes V
(550 mV),
BURH
switching resumes. The feedback voltage then falls and the
process repeats. Burst Mode alternately enables and disables
switching of the power SENSEFET, reducing switching loss
in Standby Mode.
turn−on is prohibited during the blanking time (t ). After the
B
blanking time, the controller finds the valley within the
detection time window (t ) and turns on the MOSFET, as
W
shown in Figure 27 and Figure 28 (cases A, B, and C). If no
valley is found during t , the internal SENSEFET is forced
W
to turn on at the end of t (case D). Therefore, FSQ devices
W
have a minimum switching frequency of 55kHz and a
maximum switching frequency of 67kHz, as shown in
Figure 28.
www.onsemi.com
13
FSQ0365, FSQ0265, FSQ0165, FSQ321
tsmax=18ms
When the resonant period is 2 ms
67kHz
IDS
IDS
C
Constant
frequency
A
B
59kHz
55kHz
A
B
D
tB=15ms
Burst
mode
ts
IDS
IDS
PO
FSQ0365RN Rev. 00
tB=15ms
Figure 28. Switching Frequency Range
ts
IDS
IDS
C
tB=15ms
ts
IDS
IDS
D
tB=15ms
tW=3ms
tsmax=18ms
Figure 27. Valley Switching with Limited Frequency
FSQ0365RN Rev. 00
www.onsemi.com
14
FSQ0365, FSQ0265, FSQ0165, FSQ321
Typical Application Circuit of FSQ0365RN
Output Voltage
(Maximum Current)
Application
Power Switch Device
Input Voltage Range
85−265 V
Rated Output Power
DVD Player
Power Supply
FSQ0365RN
19 W
5.1 V (1.0 A)
3.4 V (1.0 A)
12 V (0.4 A)
16 V (0.3 A)
AC
Features
Key Design Notes
• High efficiency ( > 77% at universal input)
• The delay time for overload protection is designed to be
about 30 ms with C107 of 47nF. If faster/slower
triggering of OLP is required, C107 can be changed to
a smaller/larger value (eg. 100 nF for 60 ms).
• Low standby mode power consumption (< 1 W at
230 V input and 0.5 W load)
AC
• Reduce EMI noise through Valley Switching operation
• Enhanced system reliability through various protection
functions
• The input voltage of V
must be higher than −0.3 V.
By proper voltage sharing by R106 & R107 resistors,
the input voltage can be adjusted.
sync
• Internal soft−start: 15 ms
• The SMD−type 100 nF capacitor must be placed as
close as possible to V pin to avoid malfunction by
CC
abrupt pulsating noises and to improved surge
immunity.
Schematic
C209
47pF
T101
L201
EER2828
16V, 0.3A
11
RT101
5D−9
1
2
D201
UF4003
C202
470mF
35V
C201
470mF
35V
C210
47pF
C104
10nF
630V
R105
100kΩ
R102
56kΩ
L202
D101
1N 4007
C103
33mF
400V
R108
62Ω
12V, 0.4A
3
10 D202
UF4003
C203
470mF
35V
C204
470mF
35V
2
IC101
FSQ0365RN
12
6
5
4
8
7
BD101
Bridge
Diode
Vstr
Drain
Drain
1
3
L203
6
C106 C107
100nF 22mF
SMD 50V
Drain
Sync
FB
5.1V, 1A
R103
5Ω
2
3
C205
1000mF
10V
C206
1000mF
10V
Vcc
4
D203
SB360
GND
4
5
D102
1N 4004
C102
100nF,275VAC
C105
47nF
50V
1
R104
12kΩ
L204
9
3.4V, 1A
ZD101
1N4746A
C208
1000mF
10V
D204
SB360
C207
1000mF
10V
C110
33pF
50V
LF101
40mH
8
C302
3.3nF
R201
510Ω
C101
100nF
275VAC
R203
6.2kΩ
R202
1kΩ
C209
100nF
R204
20kΩ
IC202
FOD817A
TNR
10D471K
F101
FUSE
IC201
KA431
R205
6kΩ
FSQ0365RN Rev:00
AC IN
Figure 29. Demo Circuit of FSQ0365RN
www.onsemi.com
15
FSQ0365, FSQ0265, FSQ0165, FSQ321
Transformer
EER2828
12
Np/2
1
Np/2
Np/2
11
N16V
N12V
N3.4V
N16V
N12V
Na
2
3
4
5
10
9
8
7
Na
N5.1V
N3.4V
Np/2
6mm
3mm
6
N5.1V
FSQ0365RN Rev: 00
Figure 30. Transformer Schematic Diagram of FSQ0365RN
Table 6. WINDING SPECIFICATION
No.
Pin (s " f)
3 → ꢀ 2
Wire
Turns
Winding Method
φ
N /2
p
0.25 x 1
50
Center Solenoid Winding
Insulation: Polyester Tape t = 0.050 mm, 2−Layer
9 → ꢀ 8
Insulation: Polyester Tape t = 0.050 mm, 2−Layer
6 → ꢀ 9
Insulation: Polyester Tape t = 0.050 mm, 2−Layer
4 → ꢀ 5
Insulation: Polyester Tape t = 0.050 mm, 2−Layer
10 → ꢀ 12
Insulation: Polyester Tape t = 0.050 mm, 3−Layer
11 → ꢀ 12
Insulation: Polyester Tape t = 0.050 mm, 2−Layer
N /2
2 → ꢀ 1
Insulation: Polyester Tape t = 0.050 mm, 2−Layer
φ
N
0.33 x 2
4
Center Solenoid Winding
Center Solenoid Winding
Center Solenoid Winding
Center Solenoid Winding
Center Solenoid Winding
Center Solenoid Winding
3.4V
φ
N
0.33 x 1
2
5V
φ
N
0.25 x 1
16
14
18
50
a
φ
N
0.33 x 3
12V
φ
N
0.33 x 3
16V
φ
0.25 x 1
p
Table 7. TRANSFORMER ELECTRICAL CHARACTERISTICS
Pin
Specification
1.4 mH 10%
25 mH Maximum
Remarks
100 kHz, 1 V
Inductance
Leakage
1 − 3
1 − 3
Short All Other Pins
Core & Bobbin
Core: EER2828 (Ae = 86.66 mm )
Bobbin: EER2828
2
www.onsemi.com
16
FSQ0365, FSQ0265, FSQ0165, FSQ321
Table 8. EVALUATION BOARD PART LIST
Part
Value
Note
Part
Value
Note
Resistor
Inductor
R102
R103
R104
R105
56 kW
5 W
1 W
L201
L202
L203
L204
10 mH
10 mH
4.9 mH
4.9 mH
1/2 W
1/4 W
1/4 W
12 kW
100 kW
R106
6.2 kW
1/4 W
Diode
R107
R108
R201
R202
R203
R204
R205
6.2 kW
62 W
1/4 W
1 W
D101
D102
ZD101
D103
D201
D202
D203
IN4007
IN4004
1N4746A
1N4148
UF4003
UF4003
SB360
510 W
1 kW
1/4 W
1/4 W
1/4 W
1/4 W
1/4 W
6.2 kW
20 kW
6 kW
D204
SB360
Capacitor
C101
C102
100 nF / 275 V
Box Capacitor
Box Capacitor
AC
100 nF / 275 V
IC
AC
C103
C104
C105
33 mF / 400 V
10 nF / 630 V
47 nF / 50 V
Electrolytic Capacitor
Film Capacitor
IC101
IC201
IC202
FSQ0365RN
Power Switch
Voltage reference
Opto−coupler
KA431 (TL431)
FOD817A
Mono Capacitor
C106
C107
C110
C201
C202
C203
C204
C205
C206
C207
C208
C209
100 nF / 50 V
22 mF / 50 V
SMD (1206)
Fuse
NTC
Electrolytic Capacitor
Ceramic Capacitor
Electrolytic Capacitor
Electrolytic Capacitor
Electrolytic Capacitor
Electrolytic Capacitor
Electrolytic Capacitor
Electrolytic Capacitor
Electrolytic Capacitor
Electrolytic Capacitor
Ceramic Capacitor
Fuse
RT101
BD101
LF101
T101
2A/250V
5D−9
33 pF / 50 V
470 mF / 35 V
470 mF / 35 V
470 mF / 35 V
470 mF / 35 V
1000 mF / 10 V
1000 mF / 10 V
1000 mF / 10 V
1000 mF / 10 V
100 nF / 50 V
Bridge Diode
2KBP06M2N257
Bridge Diode
Line Filter
Transformer
Varistor
40 mH
TNR
10D471K
SENSEFET is a registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
www.onsemi.com
17
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PDIP−8
CASE 626−05
ISSUE P
DATE 22 APR 2015
SCALE 1:1
NOTES:
D
A
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
E
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACK-
AGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
H
8
5
4
E1
1
6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE
LEADS UNCONSTRAINED.
7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
LEADS, WHERE THE LEADS EXIT THE BODY.
8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
NOTE 8
c
b2
B
END VIEW
WITH LEADS CONSTRAINED
TOP VIEW
NOTE 5
INCHES
DIM MIN MAX
−−−−
A1 0.015
MILLIMETERS
A2
A
MIN
−−−
0.38
2.92
0.35
MAX
5.33
−−−
4.95
0.56
e/2
A
0.210
−−−−
NOTE 3
A2 0.115 0.195
L
b
b2
C
0.014 0.022
0.060 TYP
0.008 0.014
0.355 0.400
1.52 TYP
0.20
9.02
0.13
7.62
6.10
0.36
10.16
−−−
8.26
7.11
D
SEATING
PLANE
D1 0.005
0.300 0.325
E1 0.240 0.280
−−−−
A1
D1
E
C
M
e
eB
L
0.100 BSC
−−−− 0.430
0.115 0.150
−−−− 10°
2.54 BSC
−−−
2.92
−−−
10.92
3.81
10°
e
eB
8X
b
END VIEW
M
NOTE 6
M
M
M
0.010
C A
B
SIDE VIEW
GENERIC
MARKING DIAGRAM*
STYLE 1:
PIN 1. AC IN
2. DC + IN
3. DC − IN
4. AC IN
XXXXXXXXX
AWL
YYWWG
5. GROUND
6. OUTPUT
7. AUXILIARY
8. V
CC
XXXX = Specific Device Code
A
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
WL
YY
WW
G
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42420B
PDIP−8
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PDIP8 GW
CASE 709AJ
ISSUE O
DATE 31 JAN 2017
98AON13756G
ON SEMICONDUCTOR STANDARD
DOCUMENT NUMBER:
STATUS:
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
NEW STANDARD:
DESCRIPTION: PDIP8 GW
PAGE 1 OF2
DOCUMENT NUMBER:
98AON13756G
PAGE 2 OF 2
ISSUE
REVISION
DATE
O
RELEASED FOR PRODUCTION FROM FAIRCHILD MKT−MLSOP08A TO ON
SEMICONDUCTOR. REQ. BY D. TRUHITTE.
31 JAN 2017
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
© Semiconductor Components Industries, LLC, 2017
Case Outline Number:
January, 2017 − Rev. O
709AJ
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
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and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
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SI9122E
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