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FSQ0565RS/RQ

Green-Mode Power Switch

for Quasi-Resonant Operation - Low EMI and High Efficiency

Features

Description

! Optimized for Quasi-Resonant Converters (QRC)

! Low EMI through Variable Frequency Control and AVS

A Quasi-Resonant Converter (QRC) generally shows

lower EMI and higher power conversion efficiency than a

(Alternating Valley Switching)

conventional hard-switched converter with a fixed

switching frequency. The FSQ-series is an integrated

Pulse-Width Modulation (PWM) controller and

SenseFET specifically designed for quasi-resonant

operation and Alternating Valley Switching (AVS). The

PWM controller includes an integrated fixed-frequency

oscillator, Under-Voltage Lockout (UVLO), Leading-

Edge Blanking (LEB), optimized gate driver, internal soft-

start, temperature-compensated precise current sources

for a loop compensation, and self-protection circuitry.

Compared with a discrete MOSFET and PWM controller

solution, the FSQ-series can reduce total cost,

component count, size, and weight; while simultaneously

increasing efficiency, productivity, and system reliability.

This device provides a basic platform for cost-effective

designs of quasi-resonant switching flyback converters.

! High-Efficiency through Minimum Voltage Switching

! Narrow Frequency Variation Range over Wide Load

and Input Voltage Variation

! Advanced Burst-Mode Operation for Low Standby

Power Consumption

! Simple Scheme for Sync Voltage Detection

! Pulse-by-Pulse Current Limit

! Various Protection Functions: Overload Protection

(OLP), Over-Voltage Protection (OVP), Internal

Thermal Shutdown (TSD) with Hysteresis,

Output Short Protection (OSP)

! Under-Voltage Lockout (UVLO) with Hysteresis

! Internal Startup Circuit

! Internal High-Voltage Sense FET (650V)

! Built-in Soft-Start (17.5ms)

Applications

! Power Supply for LCD TV and Monitor, VCR, SVR,

STB, and DVD & DVD Recorder

! Adapter

October-2017, Rev. 3

Publication Order Number:

FSQ0565RS/D

Ordering Information

Maximum Output Power⁽¹⁾

230V_AC±15%⁽²⁾

85-265V_AC

Product

PKG.⁽⁵⁾

Number

Operating Current R_DS(ON)

Replaces

Devices

Temp.

Limit

Max.

Open

Adapter⁽³⁾

Frame⁽⁴⁾

FSQ0565RSWDTU

TO-220F-

2.25A

3.0A

FSCM0565R

FSDM0565RE

-25 to +85°C

2.2Ω

70W

80W

41W

60W

6L

FSQ0565RQWDTU

FSQ0565RSLDTU TO-220F-

6L

FSQ0565RQLDTU

(L-Forming)

2.25A

FSCM0565R

FSDM0565RE

70W

41W

3.0A

Notes:

1. The junction temperature can limit the maximum output power.

2. 230V_ACor 100/115V_ACwith doubler.

3. Typical continuous power in a non-ventilated enclosed adapter measured at 50°C ambient temperature.

4. Maximum practical continuous power in an open-frame design at 50°C ambient.

5. Eco Status, RoHS

Application Diagram

V_O

AC

IN

V_STR

Drain

PWM

Sync

GND

V_FB

V_CC

FSQ0565RS Rev. 00

Figure 1. Typical Flyback Application

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2

Block Diagrams

V_CC

3

V_str

6

Sync

5

Drain

1

OSC

AVS

V_ref

0.35/0.55

V_Burst

V

_CCgood

V_CC

V_ref

8V/12V

I_delay

I_FB

PWM

FB

4

3R

S

R

Q

Gate

driver

Soft-

Start

LEB

250ns

R

t < t

ON OSP

after SS

LPF

V

OSP

AOCP

2

S

R

Q

V

SD

V_OCP

(1.1V)

TSD

GND

Q

V_CC

LPF

V

OVP

V_CCgood

FSQ0565RS Rev.00

Figure 2. Internal Block Diagram of FSQ0565RS

V_CC

V_str

6

Sync

5

Drain

1

3

OSC

AVS

V_ref

0.35/0.55

V_Burst

V

_CCgood

V_CC

V_ref

8V/12V

I_delay

I_FB

PWM

FB

4

3R

S

R

Q

Gate

driver

Soft-

Start

LEB

250ns

R

t < t

ON OSP

after SS

LPF

V

OSP

AOCP

2

S

R

Q

V

SD

V_OCP

(1.1V)

TSD

GND

Q

LPF

V

OVP

V_CCgood

FSQ0565RQ Rev.00

Figure 3. Internal Block Diagram of FSQ0565RQ

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3

Pin Configuration

6. V_STR

5. Sync

4. FB

3. V_CC

2. GND

1. Drain

FSQ0565 Rev.00

Figure 4. Pin Configuration (Top View)

Pin Definitions

Pin #

Name

Drain

GND

Description

1

2

SenseFET Drain. High-voltage power SenseFET drain connection.

Ground. This pin is the control ground and the SenseFET source.

Power Supply. This pin is the positive supply input, providing internal operating current for

both startup and steady-state operation.

3

4

5

6

V_CC

Feedback. This pin is internally connected to the inverting input of the PWM comparator. The

collector of an opto-coupler is typically tied to this pin. For stable operation, a capacitor should

be placed between this pin and GND. If the voltage of this pin reaches 6V, the overload

protection triggers, which shuts down the power switch.

FB

Sync. This pin is internally connected to the sync-detect comparator for quasi-resonant switch-

ing. In normal quasi-resonant operation, the threshold of the sync comparator is 1.2V/1.0V.

Sync

V_str

Startup. This pin is connected directly, or through a resistor, to the high-voltage DC link. At

startup, the internal high-voltage current source supplies internal bias and charges the exter-

nal capacitor connected to the V_CCpin. Once V_CCreaches 12V, the internal current source is

disabled. It is not recommended to connect V_strand Drain together.

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Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be opera-

ble above the recommended operating conditions and stressing the parts to these levels is not recommended. In addi-

tion, extended exposure to stresses above the recommended operating conditions may affect device reliability. The

absolute maximum ratings are stress ratings only. T_A= 25°C, unless otherwise specified.

Symbol

V_str

Parameter

Min.

500

Max.

Unit

V

V_strPin Voltage

Drain Pin Voltage

Supply Voltage

V_DS

650

V

V_CC

20

13.0

11

V

V_FB

Feedback Voltage Range

Sync Pin Voltage

-0.3

V

V_Sync

I_DM

V

Drain Current Pulsed

A

T_C= 25°C

2.8

1.7

190

45

I_D

Continuous Drain Current⁽⁶⁾

A

T_C= 100°C

E_AS

P_D

Single Pulsed Avalanche Energy⁽⁷⁾

Total Power Dissipation (T_C=25°C)

Operating Junction Temperature

Operating Ambient Temperature

Storage Temperature

mJ

W

T_J

Internally limited

°C

T_A

-25

-55

+85

T_STG

+150

Electrostatic Discharge Capability, Human Body Model

Electrostatic Discharge Capability, Charged Device Model

2.0

ESD

kV

Notes:

6. Repetitive rating: pulse-width limited by maximum junction temperature.

7. L=14mH, starting T_J=25°C.

Thermal Impedance

T_A= 25°C unless otherwise specified.

Symbol

θ_JA

Parameter

Junction-to-Ambient Thermal Resistance⁽⁸⁾

Junction-to-Case Thermal Resistance⁽⁹⁾

Package

Value

50

Unit

°C/W

TO-220F-6L

θ_JC

2.8

Notes:

8. Free standing with no heat-sink under natural convection.

9. Infinite cooling condition - refer to the SEMI G30-88.

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5

Electrical Characteristics

T_A= 25°C unless otherwise specified.

Symbol

Parameter

Condition

Min. Typ. Max. Unit

SENSEFET SECTION

BV_DSS

I_DSS

Drain Source Breakdown Voltage

Zero-Gate-Voltage Drain Current

V_CC= 0V, I_D= 100µA

V_DS= 560V

650

V

µA

Ω

300

R_DS(ON)Drain-Source On-State Resistance

T_J= 25°C, I_D= 0.5A

1.76 2.20

C_OSS

t_d(on)

t_r

Output Capacitance

Turn-On Delay Time

Rise Time

V_GS= 0V, V_DS= 25V, f = 1MHz

V_DD= 350V, I_D= 25mA

78

22

52

95

50

pF

ns

t_d(off)

t_f

Turn-Off Delay Time

Fall Time

CONTROL SECTION

t_ON.MAXMaximum On Time

t_B

T_J= 25°C

8.8 10.0 11.2

13.5 15.0 16.5

6.0

µs

Blanking Time

T_J= 25°C, V_sync= 5V

T_J= 25°C, V_sync= 0V

t_W

Detection Time Window

Initial Switching Frequency

Switching Frequency Variation⁽¹¹⁾

f_S

59.6 66.7 75.8 kHz

Δf_S

t_AVS

-25°C < T_J< 85°C

±5

±10

%

On Time

4.0

µs

at V_IN= 240V_DC, Lm = 360μH

(AVS triggered when V_AVS> spec.

and t_AVS< spec.)

AVS Triggering

Threshold⁽¹¹⁾

Feedback

V_AVS

t_SW

1.2

V

Voltage

Sync = 500kHz sine input

V_FB= 1.2V, t_ON= 4.0µs

Switching Time Variance by AVS⁽¹¹⁾

13.5

20.5

µs

I_FB

D_MIN

Feedback Source Current

Minimum Duty Cycle

V_FB= 0V

700 900 1100 µA

0

13

9

%

V

V_START

V_STOP

t_S/S

11

7

12

8

UVLO Threshold Voltage

After turn-on

V

Internal Soft-Start Time

Over-Voltage Protection (FSQ0565RS)

Threshold

With free-running frequency

17.5

19

ms

V

V_OVP

18

7.4

1.0

20

9.6

2.4

V_OVP

t_OVP

V_CC= 15V, V_FB= 2V

8

V

Voltage

Over-Voltage Protection

(FSQ0565RQ)

Blanking

Time⁽¹¹⁾

1.7

µs

BURST-MODE SECTION

V_BURH

0.45 0.55 0.65

0.25 0.35 0.45

200

V

V_BURL

Burst-Mode Voltages

T_J= 25°C, t_PD= 200ns⁽¹⁰⁾

Hysteresis

mV

Continued on the following page...

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6

Electrical Characteristics (Continued)

T_A= 25°C unless otherwise specified.

Symbol

Parameter

Condition

Min. Typ. Max. Unit

PROTECTION SECTION

I_LIMIT

V_SD

FSQ0565RS

FSQ0565RQ

T_J= 25°C, di/dt = 370mA/µs

V_CC= 15V

2.00 2.25 2.50

2.64 3.0 3.36

A

Peak Current

Limit

Shutdown Feedback Voltage

Shutdown Delay Current

Leading-Edge Blanking Time⁽¹¹⁾

Threshold Time

5.5

4

6.0

5

6.5

6

V

I_DELAY

t_LEB

V_FB= 5V

µA

ns

µs

250

1.2

t_OSP

1.4

T_J= 25°C

Output Short Threshold Feedback

Protection⁽¹¹⁾Voltage

OSP triggered when t_ON< t_OSP,

V_FB> V_OSPand lasts longer than

t_{OSP_FB}

V_OSP

1.8

2.0

V

t_{OSP_FB}

T_SD

Feedback Blanking Time

2.5

3.0

µs

Shutdown Temperature

Hysteresis

125 140 155

60

Thermal

°C

Shutdown⁽¹¹⁾

Hys

SYNC SECTION

V_SH1

1.0

0.8

1.2

1.0

230

4.7

4.4

1.4

1.2

Sync Threshold Voltage 1

Sync Delay Time^{(11, 12)}

V_CC= 15V, V_FB= 2V

V

ns

V

V_SL1

t_sync

V_SH2

V_SL2

4.3

4.0

5.1

4.8

Sync Threshold Voltage 2

Low Clamp Voltage

I_{SYNC_MAX}= 800µA,

I_{SYNC_MIN}= 50µA

V_CLAMP

0.0

0.4

0.8

V

TOTAL DEVICE SECTION

I_OP

Operating Supply Current

V_CC= 13V

V_CC= 10V

(before V_CCreaches V_START

1

3

5

mA

µA

I_START

Start Current

350 450 550

)

I_CH

Startup Charging Current

V_CC= 0V, V_STR= minimum 50V 0.65 0.85 1.00 mA

26

V_STR

Minimum V_STRSupply Voltage

V

Notes:

10. Propagation delay in the control IC.

11. Guaranteed by design; not tested in production.

12. Includes gate turn-on time.

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7

Comparison Between FSDM0x65RNB and FSQ-Series

Function

FSDM0x65RE

FSQ-Series

FSQ-Series Advantages

! Improved efficiency by valley switching

! Reduced EMI noise

! Reduced components to detect valley point

Constant

Frequency PWM

Quasi-Resonant

Operation

Operation Method

! Valley Switching

! Inherent Frequency Modulation

! Alternate Valley Switching

Frequency

Modulation

Reduced

EMI Noise

EMI Reduction

Hybrid Control

CCM or AVS

Based on Load ! Improves efficiency by introducing hybrid control

and Input Condition

Advanced

Burst-Mode

Operation

Burst-Mode

Operation

Burst-Mode

Operation

! Improved standby power by advanced burst-mode

Strong Protections

TSD

OLP, OVP

OLP, OVP, OSP ! Improved reliability through precise OSP

! Stable and reliable TSD operation

! Converter temperature range

145°C without

Hysteresis

140°C with 60°C

Hysteresis

Differences Between FSQ0565RS and FSQ0565RQ

Function

FSQ0565RS

FSQ0565RQ

Remark

! Lower current peak is suitable to reduce conduc-

tion loss

I_LIM

2.25A

3.0A

! Higher current peak is suitable for handling higher

power

V_CCOVP

(triggered by V_CC

voltage)

Sync OVP

(triggered by Sync

voltage)

! Sync OVP is suitable when V_CCvoltage is pre reg-

Over Voltage

Protection

ulated.

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Typical Performance Characteristics

These characteristic graphs are normalized at T_A= 25°C.

1.2

1.0

0.8

0.6

0.4

0.2

0.0

1.2

1.0

0.8

0.6

0.4

0.2

0.0

-25

0

25

50

75

100

125

-25

0

25

50

75

100

125

Temperature [°C]

Figure 5. Operating Supply Current (I_OP) vs. T_A

Figure 6. UVLO Start Threshold Voltage

(V_START) vs. T_A

1.2

1.0

0.8

0.6

0.4

0.2

0.0

1.2

1.0

0.8

0.6

0.4

0.2

0.0

-25

0

25

50

75

100

125

-25

0

25

50

75

100

125

Temperature [°C]

Figure 7. UVLO Stop Threshold Voltage

(V_STOP) vs. T_A

Figure 8. Startup Charging Current (I_CH) vs. T_A

1.2

1.0

0.8

0.6

0.4

0.2

0.0

1.2

1.0

0.8

0.6

0.4

0.2

0.0

-25

0

25

50

75

100

125

-25

0

25

50

75

100

125

Temperature [°C]

Figure 9. Initial Switching Frequency (f_S) vs. T_A

Figure 10. Maximum On Time (t_ON.MAX) vs. T_A

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Typical Performance Characteristics (Continued)

These characteristic graphs are normalized at T_A= 25°C.

1.2

1.0

0.8

0.6

0.4

0.2

0.0

1.2

1.0

0.8

0.6

0.4

0.2

0.0

-25

0

25

50

75

100

125

-25

0

25

50

75

100

125

Temperature [°C]

Figure 11. Blanking Time (t_B) vs. T_A

Figure 12. Feedback Source Current (I_FB) vs. T_A

1.2

1.0

0.8

0.6

0.4

0.2

0.0

1.0

0.8

0.6

0.4

0.2

0.0

-25

0

25

50

75

100

125

-25

0

25

50

75

100

125

Temperature [°C]

Figure 13. Shutdown Delay Current (I_DELAY) vs. T_A

Figure 14. Burst-Mode High Threshold Voltage

(V_burh) vs. T_A

1.2

1.0

0.8

0.6

0.4

0.2

0.0

1.2

1.0

0.8

0.6

0.4

0.2

0.0

-25

0

25

50

75

100

125

-25

0

25

50

75

100

125

Temperature [°C]

Figure 15. Burst-Mode Low Threshold Voltage

(V_burl) vs. T_A

Figure 16. Peak Current Limit (I_LIM) vs. T_A

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Typical Performance Characteristics (Continued)

These characteristic graphs are normalized at T_A= 25°C.

1.2

1.0

0.8

0.6

0.4

0.2

0.0

1.2

1.0

0.8

0.6

0.4

0.2

0.0

-25

0

25

50

75

100

125

-25

0

25

50

75

100

125

Temperature [°C]

Figure 17. Sync High Threshold Voltage 1

(V_SH1) vs. T_A

Figure 18. Sync Low Threshold Voltage 1

(V_SL1) vs. T_A

1.2

1.0

0.8

0.6

0.4

0.2

0.0

1.0

0.8

0.6

0.4

0.2

0.0

-25

0

25

50

75

100

125

-25

0

25

50

75

100

125

Temperature [°C]

Figure 19. Shutdown Feedback Voltage (V_SD) vs. T_A

Figure 20. Over-Voltage Protection (V_OV) vs. T_A

1.2

1.0

0.8

0.6

0.4

0.2

0.0

1.2

1.0

0.8

0.6

0.4

0.2

0.0

-25

0

25

50

75

100

125

-25

0

25

50

75

100

125

Temperature [°C]

Figure 21. Sync High Threshold Voltage 2

(V_SH2) vs. T_A

Figure 22. Sync Low Threshold Voltage 2

(V_SL2) vs. T_A

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11

2.1 Pulse-by-Pulse Current Limit: Because current-

mode control is employed, the peak current through the

SenseFET is limited by the inverting input of PWM

comparator (V_FB*), as shown in Figure 24. Assuming

Functional Description

1. Startup: At startup, an internal high-voltage current

source supplies the internal bias and charges the

external capacitor (C_a) connected to the V_CCpin, as

that the 0.9mA current source flows only through the

internal resistor (3R + R = 2.8k), the cathode voltage of

diode D2 is about 2.5V. Since D1 is blocked when the

feedback voltage (V_FB) exceeds 2.5V, the maximum

illustrated in Figure 23. When V_CCreaches 12V, the

power switch begins switching and the internal

high-voltage current source is disabled. The power

switch continues its normal switching operation and

the power is supplied from the auxiliary transformer

voltage of the cathode of D2 is clamped at this voltage,

clamping V_FB*. Therefore, the peak value of the current

winding unless V_CCgoes below the stop voltage of 8V.

through the SenseFET is limited.

V_DC

2.2 Leading-Edge Blanking (LEB): At the instant the

internal SenseFET is turned on, a high-current spike

usually occurs through the SenseFET, caused by

primary-side capacitance and secondary-side rectifier

reverse recovery. Excessive voltage across the R_sense

C_VCC

V_CC

V_STR

resistor would lead to incorrect feedback operation in the

current-mode PWM control. To counter this effect, the

power switch employs a leading-edge blanking (LEB)

circuit. This circuit inhibits the PWM comparator for a

short time (t_LEB) after the SenseFET is turned on.

3

6

I_start

V_REF

8V/12V

V_{cc good}

Internal

Bias

3. Synchronization: The FSQ-series employs a quasi-

resonant switching technique to minimize the switching

noise and loss. The basic waveforms of the quasi-

resonant converter are shown in Figure 25. To minimize

the MOSFET's switching loss, the MOSFET should be

turned on when the drain voltage reaches its minimum

value, which is indirectly detected by monitoring the V_CC

FSQ0565 Rev.00

Figure 23. Startup Circuit

2.Feedback Control: power switch employs current-mode

control, as shown in Figure 24. An opto-coupler (such as

the FOD817A) and shunt regulator (such as the KA431)

are typically used to implement the feedback network.

Comparing the feedback voltage with the voltage across

the R_senseresistor makes it possible to control the

winding voltage, as shown in Figure 25.

V_ds

V_RO

switching duty cycle. When the reference pin voltage of

the shunt regulator exceeds the internal reference

voltage of 2.5V, the opto-coupler LED current increases,

pulling down the feedback voltage and reducing the duty

cycle. This typically happens when the input voltage is

increased or the output load is decreased.

V_RO

V_DC

T_F

V_sync

V_ovp(8V)

V_CC

I_delay

V_REF

I_FB

1.2V

1.0V

V_FB

V_O

SenseFET

OSC

4

H11A817A

D1

D2

230ns Delay

C_B

3R

R

MOSFET Gate

+

V_FB*

Gate

driver

KA431

-

ON

OLP

FSQ0565 Rev.00

R_sense

V_SD

FSQ0565 Rev.00

Figure 25. Quasi-Resonant Switching Waveforms

Figure 24. Pulse-Width-Modulation (PWM) Circuit

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12

The switching frequency is the combination of blank time

(t ) and detection time window (t ). In case of a heavy

t_X

t_B=15us

B

W

load, the sync voltage remains flat after t and waits for

B

valley detection during t . This leads to a low switching

W

frequency not suitable for heavy loads. To correct this

drawback, additional timing is used. The timing

conditions are described in Figures 26, 27, and 28. When

I_DS

the V

remains flat higher than 4.4V at the end of t ,

sync

B

V_DS

which is instant t , the next switching cycle starts after

X

internal delay time from t . In the second case, the next

X

ingnore

switching occurs on the valley when the V

goes below

sync

4.4V

4.4V within t . Once V

detects the first valley in t , the

B

sync

V_sync

1.2V

1.0V

other switching cycle follows classical QRC operation.

FSQ0565 Rev.00

t_X

t_B=15µs

internal delay

Figure 28. After V_syncFinds First Valley

I_DS

4. Protection Circuits: The FSQ-series has several

self-protective functions, such as Overload Protection

(OLP), Over-Voltage Protection (OVP), and Thermal

Shutdown (TSD). All the protections are implemented as

auto-restart mode. Once the fault condition is detected,

switching is terminated and the SenseFET remains off.

This causes V_CCto fall. When V_CCfalls down to the

V_DS

4.4V

V_sync

Under-Voltage Lockout (UVLO) stop voltage of 8V, the

protection is reset and the startup circuit charges the

V_CCcapacitor. When the V_CCreaches the start voltage

1.2V

1.0V

FSQ0565 Rev.00

internal delay

of 12V, normal operation resumes. If the fault condition is

not removed, the SenseFET remains off and V_CCdrops

Figure 26. V_sync> 4.4V at t_X

to stop voltage again. In this manner, the auto-restart can

alternately enable and disable the switching of the power

SenseFET until the fault condition is eliminated.

Because these protection circuits are fully integrated into

the IC without external components, reliability is

improved without increasing cost.

t_X

t_B=15us

Fault

occurs

I_DS

Fault

removed

Power

on

V_DS

V_CC

4.4V

V_sync

12V

8V

1.2V

1.0V

FSQ0565 Rev.00

t

internal delay

Figure 27. V_sync< 4.4V at t_X

FSQ0565 Rev.00

Normal

operation

Fault

situation

Normal

operation

Figure 29. Auto Restart Protection Waveforms

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13

4.1 Overload Protection (OLP): Overload is defined as

the load current exceeding its normal level due to an

unexpected abnormal event. In this situation, the

protection circuit should trigger to protect the SMPS.

However, even when the SMPS is in the normal

operation, the overload protection circuit can be

triggered during the load transition. To avoid this

undesired operation, the overload protection circuit is

designed to trigger only after a specified time to

determine whether it is a transient situation or a true

overload situation. Because of the pulse-by-pulse

current limit capability, the maximum peak current

through the SenseFET is limited, and therefore the

maximum input power is restricted with a given input

voltage. If the output consumes more than this maximum

power, the output voltage (V_O) decreases below the set

3R

R

OSC

PWM

S

R

Q

Gate

driver

LEB

250ns

R_sense

+

-

2

AOCP

FSQ0765R Rev.00

GND

V_OCP

Figure 31. Abnormal Over-Current Protection

4.3 Output-Short Protection (OSP): If the output is

shorted, steep current with extremely high di/dt can flow

through the SenseFET during the LEB time. Such a

steep current brings high voltage stress on the drain of

SenseFET when turned off. To protect the device from

such an abnormal condition, OSP is included in the FSQ-

voltage. This reduces the current through the opto-

coupler LED, which also reduces the opto-coupler

transistor current, thus increasing the feedback voltage

(V_FB). If V_FBexceeds 2.5V, D1 is blocked and the 5µA

current source starts to charge C_Bslowly up to V_CC. In

this condition, V_FBcontinues increasing until it reaches

series. It is comprised of detecting V and SenseFET

FB

turn-on time. When the V is higher than 2V and the

FB

6V, when the switching operation is terminated, as

shown in Figure 30. The delay time for shutdown is the

time required to charge C_FBfrom 2.5V to 6V with 5µA. A

SenseFET turn-on time is lower than 1.2µs, the power

switch recognizes this condition as an abnormal error and

shuts down PWM switching until V

reaches V

again.

CC

start

20 ~ 50ms delay time is typical for most applications.

An abnormal condition output short is shown in Figure 32.

FSQ 0565 Rev.00

V_FB

Turn-off delay

Rectifier

Diode

Current

MOSFET

Drain

Current

Overload protection

I_LIM

6.0V

V_FB

0

Minimum turn-on time

2.5V

D

V_o

1.2µs

t₁₂= C_fb*(6.0-2.5)/I_delay

output short occurs

0

T₁

T₂

t

I_o

Figure 30. Overload Protection

FSQ0565 Rev. 00

0

Figure 32. Output Short Waveforms

4.2 Abnormal Over-Current Protection (AOCP): When

the secondary rectifier diodes or the transformer pins are

shorted, a steep current with extremely high di/dt can

flow through the SenseFET during the LEB time. Even

though the FSQ-series has overload protection, it is not

enough to protect the FSQ-series in that abnormal case,

since severe current stress is imposed on the SenseFET

until OLP triggers. The FSQ-series has an internal

AOCP circuit, shown in Figure 31. When the gate turn-

on signal is applied to the power SenseFET, the AOCP

block is enabled and monitors the current through the

sensing resistor. The voltage across the resistor is

compared with a preset AOCP level. If the sensing

resistor voltage is greater than the AOCP level, the set

signal is applied to the latch, resulting in the shutdown of

the SMPS.

4.4.1 V_CCOver-Voltage Protection (OVP) of

FSQ0565RS: If the secondary-side feedback circuit

malfunctions or a solder defect causes an opening in the

feedback path, the current through the opto-coupler

transistor becomes almost zero. In this case, V_fbclimbs

up in a similar manner to the overload situation, forcing

the preset maximum current to be supplied to the SMPS

until overload protection is activated. Because more

energy than required is provided to the output, the output

voltage may exceed the rated voltage before overload

protection is activated, resulting in the breakdown of the

devices in the secondary side. To prevent this situation,

an over-voltage protection (OVP) circuit is employed. In

general, V_CCis proportional to the output voltage and the

www.onsemi.com

14

FSQ-series uses V_CCinstead of directly monitoring the

output voltage. If V_CCexceeds 19V, an OVP circuit is

exceeds approximately 140°C, the thermal shutdown

triggers IC shutdown. The IC resumes operation when

the junction temperature decreases 60°C from TSD

temperature and V_CCreaches startup voltage (V_start).

activated, resulting in the termination of the switching

operation. To avoid undesired activation of OVP during

normal operation, V_CCshould be designed below 19V.

5. Soft-Start: The power switch has an internal soft-start

circuit that increases PWM comparator inverting input

voltage with the SenseFET current slowly after it starts. The

typical soft-start time is 17.5ms. The pulse width to the

power switching device is progressively increased to

establish the correct working conditions for transformers,

inductors, and capacitors. The voltage on the output

capacitors is progressively increased with the intention of

smoothly establishing the required output voltage. This

mode helps prevent transformer saturation and reduces

stress on the secondary diode during startup.

4.4.2 Sync Over-Voltage Protection (OVP) of

FSQ0565RQ: If the secondary-side feedback circuit

malfunctions or a solder defect causes an opening in the

feedback path, the current through the opto-coupler

transistor becomes almost zero. V_FBclimbs up in a

similar manner to the overload situation, forcing the

preset maximum current to be supplied to the SMPS

until the overload protection triggers. Because more

energy than required is provided to the output, the output

voltage may exceed the rated voltage before the

overload protection triggers, resulting in the breakdown

of the devices in the secondary side. To prevent this

situation, an OVP circuit is employed. In general, the

peak voltage of the sync signal is proportional to the

output voltage and the FSQ-series uses a sync signal

instead of directly monitoring the output voltage. If the

sync signal exceeds 8V, an OVP is triggered, shutting

down the SMPS. To avoid undesired triggering of OVP

during normal operation, two points are considered, as

depicted in Figure 33. The peak voltage of the sync

signal should be designed below 6V and the spike of the

SYNC pin must be as low as possible to avoid getting

longer than t_OVPby decreasing the leakage inductance

6. Burst Operation: To minimize power dissipation in stand-

by mode, the power switch enters burst-mode operation.

As the load decreases, the feedback voltage decreases.

As shown in Figure 34, the device automatically enters

burst-mode when the feedback voltage drops below

V_BURL(350mV). At this point, switching stops and the

output voltages start to drop at a rate dependent on

standby current load. This causes the feedback voltage

to rise. Once it passes V_BURH(550mV), switching

resumes. The feedback voltage then falls and the

process repeats. Burst-mode operation alternately

enables and disables switching of the power SenseFET,

thereby reducing switching loss in standby mode.

shown at V_CCwinding coil.

V_{Vcc_coil}&V_CC

FSQ0565RQ Rev.00

V_O

Vo^set

Absolue max V_CC(20V)

V_CC

V_{Vcc_coil}

V_FB

0.55V

0.35V

N

pri

V_DC

N_Vcc

I_DS

Improper OVP triggering

V_OVP(8V)

V

sync

V_SH2(4.8V)

t_OVP

V_DS

V_CLAMP

Figure 33. OVP Triggering of FSQ0565RQ

FSQ0565 Rev. 00

time

Switching

disabled

t1

t2 t3

t4

4.5 Thermal Shutdown with Hysteresis (TSD): The

SenseFET and the control IC are built in one package.

This enables the control IC to detect the abnormally high

temperature of the SenseFET. If the temperature

Figure 34. Waveforms of Burst Operation

www.onsemi.com

15

7. Switching Frequency Limit: To minimize switching

loss and Electromagnetic Interference (EMI), the

MOSFET turns on when the drain voltage reaches its

minimum value in quasi-resonant operation. However,

this causes switching frequency to increases at light load

conditions. As the load decreases or input voltage

increases, the peak drain current diminishes and the

switching frequency increases. This results in severe

switching losses at light-load condition, as well as

intermittent switching and audible noise. These problems

create limitations for the quasi-resonant converter

topology in a wide range of applications.

To overcome these problems, FSQ-series employs a

frequency-limit function, as shown in Figures 35 and 36.

Once the SenseFET is turned on, the next turn-on is

prohibited during the blanking time (t_B). After the

blanking time, the controller finds the valley within the

detection time window (t_W) and turns on the MOSFET, as

shown in Figures 35 and Figure 36 (Cases A, B, and C).

If no valley is found during t_W, the internal SenseFET is

forced to turn on at the end of t_W(Case D). Therefore,

the devices have a minimum switching frequency of

48kHz and a maximum switching frequency of 67kHz.

8. AVS (Alternating Valley Switching): Due to the

quasi-resonant operation with limited frequency, the

switching frequency varies depending on input voltage,

load transition, and so on. At high input voltage, the

switching on time is relatively small compared to low

input voltage. The input voltage variance is small and the

switching frequency modulation width becomes small. To

improve the EMI performance, AVS is enabled when

input voltage is high and the switching on time is small.

t_s^max=21μs

I_DS

A

B

V_DS

t_B=15μs

t_s

Internally, quasi-resonant operation is divided into two

categories; one is first-valley switching and the other is

second-valley switching after blanking time. In AVS, two

successive occurrences of first-valley switching and the

other two successive occurrences of second-valley

switching is alternatively selected to maximize frequency

modulation. As depicted in Figure 36, the switching

frequency hops when the input voltage is high. The

internal timing diagram of AVS is described in Figure 37.

I_DS

V_DS

t_B=15μs

t_s

I_DS

f_s

1

15μs

1

Assume the resonant period is 2 us

C

V_DS

67kHz

59kHz

t_B=15μs

17μs

53kHz

48kHz

1

t_s

19μs

AVS trigger point

Constant

frequency

1

Variable frequency within limited range

DCM

21μs

CCM

I_DS

AVS region

V_DS

D

C

B

A

t_B=15μs

t_W=6μs

V_IN

FSQ0565 Rev.00

t_s^max=21μs

FSQ0565 Rev. 00

Figure 36. Switching Frequency Range

Figure 35. QRC Operation with Limited Frequency

www.onsemi.com

16

V_gate

V_gatecontinued 2 pulses

1st valley switching

V_gatecontinued 2 pulses

V_gatecontinued another 2 pulses

1st valley switching

2nd valley switching

GateX2

fixed

One-shot

AVS

triggering

de-triggering

1st or 2nd is depend on GateX2

triggering

1st or 2nd is dependent on GateX2

V_DS

t_B

GateX2: Counting V_gateevery 2 pulses independent on other signals.

FSQ0565 Rev. 00

1st valley- 2nd valley frequency modulation.

Modulation frequency is approximately 17kHz.

Figure 37. Alternating Valley Switching (AVS)

PCB Layout Guide

Due to the combined scheme, power switch shows better

noise immunity than conventional PWM controller and

MOSFET discrete solutions. Furthermore, internal drain

current sense eliminates noise generation caused by a

sensing resistor. There are some recommendations for

PCB layout to enhance noise immunity and suppress the

noise inevitable in power-handling components.

There are typically two grounds in the conventional

SMPS: power ground and signal ground. The power

ground is the ground for primary input voltage and

power, while the signal ground is ground for PWM

controller. In power switch, those two grounds share the

same pin, GND. Normally the separate grounds do not

share the same trace and meet only at one point, the GND

pin. More, wider patterns for both grounds are good for

large currents by decreasing resistance.

Capacitors at the V_CCand FB pins should be as close as

possible to the corresponding pins to avoid noise from

the switching device. Sometimes Mylar® or ceramic

capacitors with electrolytic for V_CCis better for smooth

operation. The ground of these capacitors needs to

connect to the signal ground (not power ground).

The cathode of the snubber diode should be close to the

Drain pin to minimize stray inductance. The Y-capacitor

between primary and secondary should be directly

connected to the power ground of DC link to maximize

surge immunity.

Figure 38. Recommended PCB Layout

Because the voltage range of feedback and sync line is

small, it is affected by the noise of the drain pin. Those

traces should not draw across or close to the drain line.

When the heat sink is connected to the ground, it should

be connected to the power ground. If possible, avoid

using jumper wires for power ground and drain.

Mylar® is a registered trademark of DuPont Teijin Films.

www.onsemi.com

17

Typical Application Circuit

Input Voltage

Range

Output Voltage

(Maximum Current)

Application

Device

Rated Output Power

LCD Monitor

Power Supply

5.0V (2.0A)

14V (2.8A)

FSQ0565RS

85-265V_AC

50W

Features

! Average efficiency of 25%, 50%, 75%, and 100% load conditions is higher than 80% at universal input

! Low standby mode power consumption (<1W at 230V_ACinput and 0.5W load)

! Reduce EMI noise through valley switching operation

! Enhanced system reliability through various protection functions

! Internal soft-start (17.5ms)

Key Design Notes

! The delay time for overload protection is designed to be about 23ms with C105 of 33nF. If faster/slower triggering of

OLP is required, C105 can be changed to a smaller/larger value (e.g. 100nF for 70ms).

! The input voltage of V_Syncmust be between 4.7V and 8V just after MOSFET turn-off to guarantee hybrid control and

to avoid OVP triggering during normal operation.

! The SMD-type 100nF capacitor must be placed as close as possible to V_CCpin to avoid malfunction

by abrupt pulsating noises and to improve surge immunity.

1. Schematic

L201

5μH

FSQ0565RS Rev.00

D201

MBRF10H100

T1

EER3016

10

14V,

2.8A

1

2

C202

1000μF

25V

C201

1000μF

25V

R103

43kΩ

1W

C104

3.3nF

630V

R102

68kΩ

8

D101

C103

100μF

400V

1N 4007

3

2

BD101

FSQ0565RS

2KBP06M

6

1

3

V_str

Drain

Vcc

R105

100Ω 100nF 47μF

0.5W SMD 50V

C106 C107

L202

5μH

5

D202

MBRF1060

Sync

5V, 2A

4

3

Vfb

4

7

4

GND

2

D102

UF 4004

C204

1000μF

10V

C203

2200μF

10V

C105

33nF

100V

C102

150nF

275VAC

R107

39kΩ

6

5

ZD101

1N4745A

C301

4.7nF

1kV

LF101

30mH

R108

27kΩ

R201

620Ω

R101

12MΩ

1W

R204

8kΩ

R202

1.2kΩ

R203

18kΩ

C205

47nF

Optional components

IC301

FOD817A

IC201

KA431

C101

150nF

275V_AC

RT1

5D-9

R205

8kΩ

F1

FUSE

250V

2A

Figure 39. Demo Circuit of FSQ0565RS

www.onsemi.com

18

2. Transformer

FSQ0565RS

Rev.0.0

EER3016

FSQ0565RS Rev.0.0

Top

10

9

N_14V

1

N_p/2

2

4

7

8

5

6

N_a

N_5V

N_p/2

N_5V

8

3

N_p/2

N_14V10

4

7

2

N_p/2

3

N_a

N_5V

5

6

Bottom

Figure 40. Transformer Schematic Diagram of FSQ0565RS

3. Winding Specification

Position

No

Insulation: Polyester Tape t = 0.025mm, 4 Layers

N_p/2 2 → 1 0.4φ × 1