FSQ0765RQWDTU [ONSEMI]
650V 集成电源开关,准谐振运行,用于 70W 离线反激转换器;型号: | FSQ0765RQWDTU |
厂家: | ONSEMI |
描述: | 650V 集成电源开关,准谐振运行,用于 70W 离线反激转换器 局域网 开关 电源开关 转换器 |
文件: | 总21页 (文件大小:3032K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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April 2009
FSQ0765RQ
Green-Mode Fairchild Power Switch (FPS™) for
Quasi-Resonant Operation - Low EMI and High Efficiency
Features
Description
! Optimized for Quasi-Resonant Converter (QRC)
! Low EMI through Variable Frequency Control and AVS
A Quasi-Resonant Converter (QRC) generally shows
lower EMI and higher power conversion efficiency than a
(Alternating Valley Switching)
conventional hard-switched converter with a fixed
switching frequency. The FSQ-series is an integrated
Pulse-Width Modulation (PWM) controller and
SenseFET specifically designed for quasi-resonant
operation and Alternating Valley Switching (AVS). The
PWM controller includes an integrated fixed-frequency
oscillator, Under-Voltage Lockout (UVLO), Leading-
Edge Blanking (LEB), optimized gate driver, internal soft-
start, temperature-compensated precise current sources
for a loop compensation, and self-protection circuitry.
Compared with a discrete MOSFET and PWM controller
solution, the FSQ-series can reduce total cost,
component count, size, and weight; while simultaneously
increasing efficiency, productivity, and system reliability.
This device provides a basic platform that is well suited
for cost-effective designs of quasi-resonant switching
flyback converters.
! High-Efficiency through Minimum Voltage Switching
! Narrow Frequency Variation Range over Wide Load
and Input Voltage Variation
! Advanced Burst-Mode Operation for Low Standby
Power Consumption
! Simple Scheme for Sync Voltage Detection
! Pulse-by-Pulse Current Limit
! Various Protection functions: Overload Protection
(OLP), Over-Voltage Protection (OVP), Abnormal
Over-Current Protection (AOCP), Internal Thermal
Shutdown (TSD) with Hysteresis, Output Short
Protection (OSP)
! Under-Voltage Lockout (UVLO) with Hysteresis
! Internal Startup Circuit
! Internal High-Voltage Sense FET (650V)
! Built-in Soft-Start (17.5ms)
Applications
! Power Supply for LCD TV and Monitor, VCR, SVR,
STB, and DVD & DVD Recorder
! Adapter
Related Resources
Visit http://www.fairchildsemi.com/apnotes/ for:
! AN-4134: Design Guidelines for Offline Forward
Converters Using Fairchild Power Switch (FPS™)
! AN-4137: Design Guidelines for Offline Flyback
Converters Using Fairchild Power Switch (FPS™)
! AN-4140: Transformer Design Consideration for
Offline Flyback Converters Using Fairchild Power
Switch (FPS™)
! AN-4141: Troubleshooting and Design Tips for
Fairchild Power Switch (FPS™) Flyback Applications
! AN-4145: Electromagnetic Compatibility for Power
Converters
! AN-4147: Design Guidelines for RCD Snubber of
Flyback
! AN-4148: Audible Noise Reduction Techniques for
Fairchild Power Switch Fairchild Power Switch(FPS™)
Applications
! AN-4150: Design Guidelines for Flyback Converters
Using FSQ-Series Fairchild Power Switch (FPS™)
© 2008 Fairchild Semiconductor Corporation
FSQ0765RQ Rev. 1.0.1
www.fairchildsemi.com
Ordering Information
Maximum Output Power(1)
230VAC±15%(2)
85-265VAC
Product
PKG.(5)
Number
Operating Current RDS(ON)
Replaces
Devices
Temp.
Limit
Max.
Open
Open
Adapter(3)
Adapter(3)
Frame(4)
Frame(4)
FSCM0765R
FSDM0765RB
FSQ0765RQWDTU TO-220F-6L -25 to +85°C
3.5A
1.6Ω
80W
90W
48W
70W
Notes:
1. The junction temperature can limit the maximum output power.
2. 230VAC or 100/115VAC with doubler.
3. Typical continuous power in a non-ventilated enclosed adapter measured at 50°C ambient temperature.
4. Maximum practical continuous power in an open-frame design at 50°C ambient.
5.
For Fairchild’s definition of “green” Eco Status, please visit:
http://www.fairchildsemi.com/company/green/rohs_green.html. Eco Status: RoHS.
© 2008 Fairchild Semiconductor Corporation
FSQ0765RQ Rev. 1.0.1
www.fairchildsemi.com
2
Application Diagram
VO
AC
IN
Vstr
Drain
PWM
Sync
GND
VCC
FB
FSQ0765R Rev.00
Figure 1. Typical Flyback Application
Internal Block Diagram
VCC
3
Vstr
6
Sync
5
Drain
1
OSC
AVS
Vref
0.35/0.55
VBurst
VCC good
VCC
Vref
8V/12V
Idelay
IFB
PWM
FB
4
3R
S
R
Q
Q
Gate
driver
Soft-
Start
LEB
250ns
R
t
ON
< t
OSP
after SS
LPF
V
OSP
AOCP
2
S
R
Q
V
VOCP
(1.1V)
TSD
SD
GND
Q
LPF
V
OVP
VCC good
FSQ0765R Rev.00
Figure 2. Internal Block Diagram
© 2008 Fairchild Semiconductor Corporation
FSQ0765RQ Rev. 1.0.1
www.fairchildsemi.com
3
Pin Configuration
6. Vstr
5. Sync
4. FB
3. VCC
2. GND
1. Drain
FSQ0765R Rev.00
Figure 3. Pin Configuration (Top View)
Pin Definitions
Pin # Name
Description
1
2
Drain SenseFET drain. High-voltage power SenseFET drain connection.
GND Ground. This pin is the control ground and the SenseFET source.
Power Supply. This pin is the positive supply input. This pin provides internal operating current for
both startup and steady-state operation.
3
4
5
6
VCC
Feedback. This pin is internally connected to the inverting input of the PWM comparator. The
collector of an opto-coupler is typically tied to this pin. For stable operation, a capacitor should be
placed between this pin and GND. If the voltage of this pin reaches 6V, the overload protection
triggers, which shuts down the FPS.
FB
Sync. This pin is internally connected to the sync-detect comparator for quasi-resonant switching.
In normal quasi-resonant operation, the threshold of the sync comparator is 1.2V/1.0V.
Sync
Startup. This pin is connected directly, or through a resistor, to the high-voltage DC link. At
start-up, the internal high-voltage current source supplies internal bias and charges the external
capacitor connected to the VCC pin. Once VCC reaches 12V, the internal current source is disabled.
Vstr
It is not recommended to connect Vstr and Drain together.
© 2008 Fairchild Semiconductor Corporation
FSQ0765RQ Rev. 1.0.1
www.fairchildsemi.com
4
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be opera-
ble above the recommended operating conditions and stressing the parts to these levels is not recommended. In addi-
tion, extended exposure to stresses above the recommended operating conditions may affect device reliability. The
absolute maximum ratings are stress ratings only. TA = 25°C, unless otherwise specified.
Symbol
Vstr
Parameter
Min.
500
Max.
Unit
V
Vstr Pin Voltage
Drain Pin Voltage
Supply Voltage
VDS
650
V
VCC
20
V
VFB
Feedback Voltage Range
Sync Pin Voltage
-0.3
-0.3
13.0
13.0
14.4
3.6
V
VSync
IDM
V
Drain Current Pulsed
A
TC = 25°C
C = 100°C
ID
Continuous Drain Current(6)
A
T
2.28
570
45
EAS
PD
Single Pulsed Avalanche Energy(7)
Total Power Dissipation(Tc=25°C)
Operating Junction Temperature
Operating Ambient Temperature
Storage Temperature
mJ
W
TJ
Internally limited
°C
°C
°C
TA
-25
-55
+85
TSTG
+150
Human Body Model
2
2
ESD
Electrostatic Discharge Capability
kV
Charged Device Model
Notes:
6. Repetitive rating: Pulse width limited by maximum junction temperature.
7. L=81mH, starting TJ=25°C.
Thermal Impedance
TA = 25°C unless otherwise specified.
Symbol
θJA
Parameter
Junction-to-Ambient Thermal Resistance(8)
Junction-to-Case Thermal Resistance(9)
Value
50
Unit
°C/W
°C/W
θJC
2.8
Notes:
8. Free standing with no heat-sink under natural convection.
9. Infinite cooling condition - refer to the SEMI G30-88.
© 2008 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSQ0765RQ Rev. 1.0.1
5
Electrical Characteristics
TA = 25°C unless otherwise specified.
Symbol
Parameter
Condition
Min. Typ. Max. Unit
SENSEFET SECTION
BVDSS
IDSS
RDS(ON)
COSS
td(on)
tr
Drain Source Breakdown Voltage
Zero-Gate-Voltage Drain Current
Drain-Source On-State Resistance
Output Capacitance
VCC = 0V, ID = 100µA
650
V
µA
Ω
VDS = 520V, VGS = 0V
TJ = 25°C, ID = 1.8A
300
1.6
1.3
125
27
VGS = 0V, VDS = 25V, f = 1MHz
pF
ns
ns
ns
ns
Turn-On Delay Time
Rise Time
102
63
VDD = 325V, ID = 6.5A
td(off)
tf
Turn-Off Delay Time
Fall Time
65
CONTROL SECTION
tON.MAX Maximum On Time
tB
TJ = 25°C
8.8 10.0 11.2
13.5 15.0 16.5
6.0
µs
µs
µs
Blanking Time
TJ = 25°C, Vsync = 5V
TJ = 25°C, Vsync = 0V
tW
Detection Time Window
Initial Switching Frequency
Switching Frequency Variation(11)
fS
59.6 66.7 75.8 kHz
ΔfS
tAVS
-25°C < TJ < 85°C
±5
±10
%
On Time
4.0
µs
at VIN = 240VDC, Lm = 360μH
(AVS triggered when VAVS>spec
& tAVS<spec.)
AVS Triggering
Threshold(11)
Feedback
VAVS
tSW
1.2
V
Voltage
Sync = 500kHz sine input
VFB = 1.2V, tON = 4.0µs
Switching Time Variance by AVS(11)
13.5
20.5
µs
IFB
DMIN
Feedback Source Current
Minimum Duty Cycle
VFB = 0V
VFB = 0V
700 900 1100 µA
0
13
9
%
V
VSTART
VSTOP
tS/S
11
7
12
8
UVLO Threshold Voltage
Internal Soft-Start Time
After turn-on
V
With free-running frequency
17.5
ms
BURST-MODE SECTION
VBURH
0.45 0.55 0.65
0.25 0.35 0.45
200
V
V
VBURL
Burst-Mode Voltages
TJ = 25°C, tPD = 200ns(10)
Hysteresis
mV
Note:
10. Propagation delay in the control IC.
Continued on the following page...
© 2008 Fairchild Semiconductor Corporation
FSQ0765RQ Rev. 1.0.1
www.fairchildsemi.com
6
Electrical Characteristics (Continued)
TA = 25°C unless otherwise specified.
Symbol
Parameter
Condition
Min. Typ. Max. Unit
PROTECTION SECTION
ILIMIT
VSD
IDELAY
tLEB
Peak Current Limit
TJ = 25°C, di/dt = 460mA/µs
VCC = 15V
3.08 3.50 3.92
A
V
Shutdown Feedback Voltage
Shutdown Delay Current
Leading-Edge Blanking Time(11)
Threshold Time
5.5
4
6.0
5
6.5
6
VFB = 5V
µA
ns
µs
250
1.2
tOSP
1.4
TJ = 25°C
Output Short Threshold Feedback
Protection(11) Voltage
OSP triggered when tON<tOSP
VFB>VOSP & lasts longer than
tOSP_FB
,
VOSP
1.8
2.0
2.0
V
tOSP_FB
TSD
Feedback Blanking Time
2.5
3.0
µs
Shutdown Temperature
Hysteresis
125 140 155
60
Thermal
°C
Shutdown(11)
Hys
SYNC SECTION
VSH1
1.0
0.8
1.2
1.0
230
4.7
4.4
1.4
1.2
Sync Threshold Voltage 1
Sync Delay Time(11)(12)
VCC = 15V, VFB = 2V
VCC = 15V, VFB = 2V
V
ns
V
VSL1
tsync
VSH2
VSL2
4.3
4.0
5.1
4.8
Sync Threshold Voltage 2
Low Clamp Voltage
ISYNC_MAX = 800µA
ISYNC_MIN = 50µA
VCLAMP
0.0
0.4
0.8
V
VOVP
tOVP
Threshold Voltage
Blanking Time(11)
V
CC = 15V, VFB=2V
7.4
1.0
8.0
1.7
8.6
2.4
V
Over-Voltage
Protection
µs
TOTAL DEVICE SECTION
Operating Supply Current
(Control Part Only)
IOP
VCC = 13V, VFB=0V
1
3
5
mA
µA
VCC = 10V
ISTART
Start Current
350 450 550
(before VCC reaches VSTART
)
ICH
Startup Charging Current
VCC = 0V, VSTR = minimum 50V 0.65 0.85 1.00 mA
VSTR
Minimum VSTR Supply Voltage
26
V
Notes:
11. Guaranteed by design, but not tested in production.
12. Includes gate turn-on time.
© 2008 Fairchild Semiconductor Corporation
FSQ0765RQ Rev. 1.0.1
www.fairchildsemi.com
7
Comparison Between FSDM0x65RNB and FSQ-Series
Function
FSDM0x65RE
FSQ-Series
FSQ-Series Advantages
! Improved efficiency by valley switching
! Reduced EMI noise
! Reduced components to detect valley point
Constant
Frequency PWM
Quasi-Resonant
Operation
Operation Method
! Valley switching
Reduce EMI Noise ! Inherent frequency modulation
! Alternate valley switching
Frequency
Modulation
EMI Reduction
Hybrid Control
CCM or AVS
Based on Load ! Improves efficiency by introducing hybrid control
and Input Condition
Advanced
Burst-Mode
Operation
Burst-Mode
Operation
Burst-Mode
Operation
! Improved standby power by AVS in burst-mode
! Improved reliability through precise AOCP
! Improved reliability through precise OSP
OLP, OVP,
AOCP, OSP
Strong Protections
TSD
OLP, OVP
! Stable and reliable TSD operation
! Converter temperature range
145°C without
Hysteresis
140°C with 60°C
Hysteresis
© 2008 Fairchild Semiconductor Corporation
FSQ0765RQ Rev. 1.0.1
www.fairchildsemi.com
8
Typical Performance Characteristics
These characteristic graphs are normalized at TA= 25°C.
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
Temperature [°C]
Temperature [°C]
Figure 4. Operating Supply Current (IOP) vs. TA
Figure 5. UVLO Start Threshold Voltage
(VSTART) vs. TA
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
Temperature [°C]
Temperature [°C]
Figure 6. UVLO Stop Threshold Voltage
(VSTOP) vs. TA
Figure 7. Startup Charging Current (ICH) vs. TA
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
Temperature [°C]
Temperature [°C]
Figure 8. Initial Switching Frequency (fSW) vs. TA
Figure 9. Maximum On Time (tON.MAX) vs. TA
© 2008 Fairchild Semiconductor Corporation
FSQ0765RQ Rev. 1.0.1
www.fairchildsemi.com
9
Typical Performance Characteristics (Continued)
These characteristic graphs are normalized at TA= 25°C.
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
Temperature [°C]
Temperature [°C]
Figure 10. Blanking Time (tB) vs. TA
Figure 11. Feedback Source Current (IFB) vs. TA
1.2
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.0
0.8
0.6
0.4
0.2
0.0
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
Temperature [°C]
Temperature [°C]
Figure 12. Shutdown Delay Current (IDELAY) vs. TA
Figure 13. Burst-Mode High Threshold Voltage
(Vburh) vs. TA
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
Temperature [°C]
Temperature [°C]
Figure 14. Burst-Mode Low Threshold Voltage
(Vburl) vs. TA
Figure 15. Peak Current Limit (ILIM) vs. TA
© 2008 Fairchild Semiconductor Corporation
FSQ0765RQ Rev. 1.0.1
www.fairchildsemi.com
10
Typical Performance Characteristics (Continued)
These characteristic graphs are normalized at TA= 25°C.
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
Temperature [°C]
Temperature [°C]
Figure 16. Sync High Threshold Voltage 1
(VSH1) vs. TA
Figure 17. Sync Low Threshold Voltage 1
(VSL1) vs. TA
1.2
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.0
0.8
0.6
0.4
0.2
0.0
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
Temperature [°C]
Temperature [°C]
Figure 18. Shutdown Feedback Voltage (VSD) vs. TA
Figure 19. Over-Voltage Protection (VOV) vs. TA
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
Temperature [°C]
Temperature [°C]
Figure 20. Sync High Threshold Voltage 2
(VSH2) vs. TA
Figure 21. Sync Low Threshold Voltage 2
(VSL2) vs. TA
© 2008 Fairchild Semiconductor Corporation
FSQ0765RQ Rev. 1.0.1
www.fairchildsemi.com
11
2.2 Leading-Edge Blanking (LEB): At the instant the
internal SenseFET is turned on, a high-current spike
usually occurs through the SenseFET, caused by
primary-side capacitance and secondary-side rectifier
reverse recovery. Excessive voltage across the Rsense
Functional Description
1. Startup: At startup, an internal high-voltage current
source supplies the internal bias and charges the
external capacitor (Ca) connected to the VCC pin, as
illustrated in Figure 22. When VCC reaches 12V, the
resistor would lead to incorrect feedback operation in the
current-mode PWM control. To counter this effect, the
FPS employs a leading-edge blanking (LEB) circuit. This
circuit inhibits the PWM comparator for a short time
(tLEB) after the SenseFET is turned on.
FPS™ begins switching and the internal high-voltage
current source is disabled. The FPS continues its normal
switching operation and the power is supplied from the
auxiliary transformer winding unless VCC goes below the
stop voltage of 8V.
Vref
VCC
Idelay
VDC
IFB
VFB
VO
SenseFET
OSC
4
FOD817A
D1
D2
Ca
CB
3R
R
+
Gate
VFB
*
driver
VCC
KA431
-
Vstr
3
6
OLP
Rsense
VSD
ICH
FSQ0765R Rev. 00
Vref
8V/12V
VCC good
Figure 23. Pulse-Width-Modulation (PWM) Circuit
Internal
Bias
3. Synchronization: The FSQ-series employs a quasi-
resonant switching technique to minimize the switching
noise and loss. The basic waveforms of the quasi-
resonant converter are shown in Figure 24. To minimize
the MOSFET's switching loss, the MOSFET should be
turned on when the drain voltage reaches its minimum
value, which is indirectly detected by monitoring the VCC
FSQ0765R Rev.00
Figure 22. Startup Circuit
2. Feedback Control: FPS employs current-mode
control, as shown in Figure 23. An opto-coupler (such as
the FOD817A) and shunt regulator (such as the KA431)
are typically used to implement the feedback network.
Comparing the feedback voltage with the voltage across
the Rsense resistor makes it possible to control the
winding voltage, as shown in Figure 24.
Vds
VRO
switching duty cycle. When the reference pin voltage of
the shunt regulator exceeds the internal reference
voltage of 2.5V, the opto-coupler LED current increases,
pulling down the feedback voltage and reducing the duty
cycle. This typically happens when the input voltage is
increased or the output load is decreased.
VRO
VDC
tF
Vsync
Vovp (8V)
2.1 Pulse-by-Pulse Current Limit: Because current-
mode control is employed, the peak current through the
SenseFET is limited by the inverting input of PWM
comparator (VFB*), as shown in Figure 23. Assuming
1.2V
1.0V
230ns Delay
that the 0.9mA current source flows only through the
internal resistor (3R + R = 2.8k), the cathode voltage of
diode D2 is about 2.5V. Since D1 is blocked when the
feedback voltage (VFB) exceeds 2.5V, the maximum
MOSFET Gate
ON
ON
voltage of the cathode of D2 is clamped at this voltage,
clamping VFB*. Therefore, the peak value of the current
FSQ0765R Rev.00
through the SenseFET is limited.
Figure 24. Quasi-Resonant Switching Waveforms
© 2008 Fairchild Semiconductor Corporation
FSQ0765RQ Rev. 1.0.1
www.fairchildsemi.com
12
The switching frequency is the combination of blank time
(t ) and detection time window (t ). In case of a heavy
tX
tB=15μs
B
W
load, the sync voltage remains flat after t and waits for
B
valley detection during t . This leads to a low switching
W
frequency not suitable for heavy loads. To correct this
drawback, additional timing is used. The timing
conditions are described in Figures 25, 26, and 27. When
IDS
IDS
the V
remains flat higher than 4.4V at the end of t
sync
B
VDS
that is t , the next switching cycle starts after internal
X
delay time from t . In the second case, the next switching
X
ingnore
occurs on the valley when the V
goes below 4.4V
sync
4.4V
within t . Once V
detects the first valley within t , the
B
B
sync
Vsync
1.2V
1.0V
other switching cycle follows classical QRC operation.
internal delay
FSQ0765R Rev. 00
tX
tB=15μs
Figure 27. After Vsync Finds First Valley
IDS
IDS
4. Protection Circuits: The FSQ-series has several
self-protective functions, such as Overload Protection
(OLP), Abnormal Over-Current Protection (AOCP),
Over-Voltage Protection (OVP), and Thermal Shutdown
(TSD). All the protections are implemented as auto-
restart mode. Once the fault condition is detected,
switching is terminated and the SenseFET remains off.
This causes VCC to fall. When VCC falls down to the
VDS
4.4V
Vsync
Under-Voltage Lockout (UVLO) stop voltage of 8V, the
protection is reset and the startup circuit charges the
VCC capacitor. When the VCC reaches the start voltage
1.2V
1.0V
internal delay
FSQ0765R Rev. 00
of 12V, normal operation resumes. If the fault condition is
not removed, the SenseFET remains off and VCC drops
Figure 25. Vsync > 4.4V at tX
to stop voltage again. In this manner, the auto-restart can
alternately enable and disable the switching of the power
SenseFET until the fault condition is eliminated.
Because these protection circuits are fully integrated into
the IC without external components, the reliability is
improved without increasing cost.
tX
tB=15μs
Fault
occurs
Fault
removed
Power
on
VDS
IDS
IDS
VDS
VCC
4.4V
12V
8V
Vsync
1.2V
1.0V
t
internal delay
FSQ0765R Rev. 00
Normal
operation
Fault
situation
Normal
operation
FSQ0765R Rev. 00
Figure 26. Vsync < 4.4V at tX
Figure 28. Auto Restart Protection Waveforms
© 2008 Fairchild Semiconductor Corporation
FSQ0765RQ Rev. 1.0.1
www.fairchildsemi.com
13
4.1 Overload Protection (OLP): Overload is defined as
the load current exceeding its normal level due to an
unexpected abnormal event. In this situation, the
protection circuit should trigger to protect the SMPS.
However, even when the SMPS is in the normal
operation, the overload protection circuit can be
triggered during the load transition. To avoid this
undesired operation, the overload protection circuit is
designed to trigger only after a specified time to
determine whether it is a transient situation or a true
overload situation. Because of the pulse-by-pulse
current limit capability, the maximum peak current
through the SenseFET is limited, and therefore the
maximum input power is restricted with a given input
voltage. If the output consumes more than this maximum
power, the output voltage (VO) decreases below the set
3R
R
OSC
PWM
S
R
Q
Q
Gate
driver
LEB
250ns
Rsense
+
-
2
AOCP
FSQ0765R Rev.00
GND
VOCP
Figure 30. Abnormal Over-Current Protection
4.3 Output-Short Protection (OSP): If the output is
shorted, steep current with extremely high di/dt can flow
through the SenseFET during the LEB time. Such a
steep current brings high voltage stress on the drain of
SenseFET when turned off. To protect the device from
such an abnormal condition, OSP is included in the FSQ-
voltage. This reduces the current through the opto-
coupler LED, which also reduces the opto-coupler
transistor current, thus increasing the feedback voltage
(VFB). If VFB exceeds 2.5V, D1 is blocked and the 5µA
current source starts to charge CB slowly up to VCC. In
this condition, VFB continues increasing until it reaches
series. It is comprised of detecting V and SenseFET
FB
turn-on time. When the V is higher than 2V and the
FB
6V, when the switching operation is terminated, as
shown in Figure 29. The delay time for shutdown is the
time required to charge CFB from 2.5V to 6V with 5µA. A
SenseFET turn-on time is lower than 1.2µs, the FPS
recognizes this condition as an abnormal error and shuts
down PWM switching until V
reaches V
again. An
CC
start
20 ~ 50ms delay time is typical for most applications.
abnormal condition output short is shown in Figure 31.
Turn-off delay
MOSFET
Rectifier
FSQ0765R Rev.00
VFB
Drain
Diode Current
Current
Overload protection
6.0V
ILIM
VFB
0
Minimum turn-on time
D
2.5V
Vo
1.2us
t12= CFB*(6.0-2.5)/Idelay
output short occurs
0
t1
t2
t
Io
FSQ0765R Rev. 00
Figure 29. Overload Protection
0
Figure 31. Output Short Waveforms
4.2 Abnormal Over-Current Protection (AOCP): When
the secondary rectifier diodes or the transformer pins are
shorted, a steep current with extremely high di/dt can
flow through the SenseFET during the LEB time. Even
though the FSQ-series has overload protection, it is not
enough to protect the FSQ-series in that abnormal case,
since severe current stress is imposed on the SenseFET
until OLP triggers. The FSQ-series has an internal
AOCP circuit shown in Figure 30. When the gate turn-on
signal is applied to the power SenseFET, the AOCP
block is enabled and monitors the current through the
sensing resistor. The voltage across the resistor is
compared with a preset AOCP level. If the sensing
resistor voltage is greater than the AOCP level, the set
signal is applied to the latch, resulting in the shutdown of
the SMPS.
4.4 Over-Voltage Protection (OVP): If the secondary-
side feedback circuit malfunctions or a solder defect
causes an opening in the feedback path, the current
through the opto-coupler transistor becomes almost
zero. Then, VFB climbs up in a similar manner to the
overload situation, forcing the preset maximum current
to be supplied to the SMPS until the overload protection
triggers. Because more energy than required is provided
to the output, the output voltage may exceed the rated
voltage before the overload protection triggers, resulting
in the breakdown of the devices in the secondary side.
To prevent this situation, an OVP circuit is employed. In
general, the peak voltage of the sync signal is
proportional to the output voltage and the FSQ-series
© 2008 Fairchild Semiconductor Corporation
FSQ0765RQ Rev. 1.0.1
www.fairchildsemi.com
14
uses a sync signal instead of directly monitoring the
output voltage. If the sync signal exceeds 8V, an OVP is
triggered, shutting down the SMPS. To avoid undesired
triggering of OVP during normal operation, there are two
points to be considered, which are depicted in Figure 32.
One is at the peak voltage of the sync signal should be
designed below 6V and the other is that the spike of the
sync pin should be as low as possible; not to get longer
than tOVP by decreasing the leakage inductance shown
6. Burst Operation: To minimize power dissipation in
standby mode, the FPS enters burst-mode operation. As
the load decreases, the feedback voltage decreases. As
shown in Figure 33, the device automatically enters
burst-mode when the feedback voltage drops below
VBURL (350mV). At this point, switching stops and the
output voltages start to drop at a rate dependent on
standby current load. This causes the feedback voltage
to rise. Once it passes VBURH (550mV), switching
at VCC winding coil.
resumes. The feedback voltage then falls and the
process repeats. Burst-mode operation alternately
enables and disables switching of the power SenseFET,
thereby reducing switching loss in standby mode.
VVcc_coil &VCC
FSQ0765R Rev.00
Absolue max VCC (20V)
VCC
VVcc_coil
VO
set
VO
VFB
N
pri
VDC
N
Vcc
0.55V
0.35V
Improper OVP triggering
VOVP (8V)
V
sync
IDS
VSH2 (4.8V)
tOVP
tOVP
VCLAMP
VDS
Figure 32. OVP Triggering
time
Switching
disabled
Switching
disabled
4.5 Thermal Shutdown with Hysteresis (TSD): The
SenseFET and the control IC are built in one package.
This allows the control IC to detect abnormally high
temperature of the SenseFET. If the temperature
exceeds approximately 140°C, the thermal shutdown
triggers IC shutdown. The IC recovers its operation when
the junction temperature decreases 60°C from TSD
temperature and VCC reaches startup voltage (Vstart).
t4
t2 t3
t1
FSQ0765R Rev.00
Figure 33. Waveforms of Burst Operation
7. Switching Frequency Limit: To minimize switching
loss and Electromagnetic Interference (EMI), the
MOSFET turns on when the drain voltage reaches its
minimum value in quasi-resonant operation. However,
this causes switching frequency to increases at light load
conditions. As the load decreases or input voltage
increases, the peak drain current diminishes and the
switching frequency increases. This results in severe
switching losses at light-load condition, as well as
intermittent switching and audible noise. These problems
create limitations for the quasi-resonant converter
topology in a wide range of applications.
5. Soft-Start: The FPS has an internal soft-start circuit
that increases PWM comparator inverting input voltage
with the SenseFET current slowly after it starts up. The
typical soft-start time is 17.5ms. The pulse width to the
power switching device is progressively increased to
establish the correct working conditions for transformers,
inductors, and capacitors. The voltage on the output
capacitors is progressively increased with the intention of
smoothly establishing the required output voltage. This
mode helps prevent transformer saturation and reduces
stress on the secondary diode during startup.
To overcome these problems, FSQ-series employs a
frequency-limit function, as shown in Figures 34 and 35.
Once the SenseFET is turned on, the next turn-on is
prohibited during the blanking time (tB). After the
blanking time, the controller finds the valley within the
detection time window (tW) and turns on the MOSFET, as
shown in Figures 34 and Figure 35 (Cases A, B, and C).
© 2008 Fairchild Semiconductor Corporation
FSQ0765RQ Rev. 1.0.1
www.fairchildsemi.com
15
If no valley is found during tW, the internal SenseFET is
forced to turn on at the end of tW (Case D). Therefore,
8. AVS (Alternating Valley Switching): Due to the
quasi-resonant operation with limited frequency, the
switching frequency varies depending on input voltage,
load transition, and so on. At high input voltage, the
switching on time is relatively small compared to low
input voltage. The input voltage variance is small and the
switching frequency modulation width becomes small. To
improve the EMI performance, AVS is enabled when
input voltage is high and the switching on time is small.
the devices have a minimum switching frequency of
48kHz and a maximum switching frequency of 67kHz.
tsmax=21μs
IDS
IDS
A
Internally, quasi-resonant operation is divided into two
categories; one is first-valley switching and the other is
second-valley switching after blanking time. In AVS, two
successive occurrences of first-valley switching and the
other two successive occurrences of second-valley
switching is alternatively selected to maximize frequency
modulation. As depicted in Figure 35, the switching
frequency hops when the input voltage is high. The
internal timing diagram of AVS is described in Figure 36.
tB=15μs
ts
IDS
IDS
B
tB=15μs
ts
fs
1
Assume the resonant period is 2us
15μs
67kHz
1
59kHz
17μs
IDS
IDS
53kHz
1
48kHz
19μs
AVS trigger point
C
Constant
frequency
1
Variable frequency within limited range
DCM
tB=15μs
21μs
CCM
AVS region
ts
D
C
B
A
IDS
IDS
Vin
FSQ0765R Rev.00
D
tB=15μs
Figure 35. Switching Frequency Range
tW=6μs
tsmax=21μs
FSQ0765R Rev. 00
Figure 34. QRC Operation with Limited Frequency
Vgate
Vgate continued 2 pulses
Vgate continued 2 pulses
Vgate continued another 2 pulses
1st valley switching
2nd valley switching
1st valley switching
GateX2
fixed
fixed
fixed
fixed
fixed fixed
One-shot
AVS
triggering
de-triggering
1st or 2nd is depend on GateX2
triggering
1st or 2nd is dependent on GateX2
VDS
tB
tB
tB
tB
tB
tB
GateX2: Counting Vgate every 2 pulses independent on other signals.
FSQ0765R Rev. 00
1st valley- 2nd valley frequency modulation.
Modulation frequency is approximately 17kHz.
Figure 36. Alternating Valley Switching (AVS)
© 2008 Fairchild Semiconductor Corporation
FSQ0765RQ Rev. 1.0.1
www.fairchildsemi.com
16
PCB Layout Guide
Due to the combined scheme, FPS shows better noise
immunity than conventional PWM controller and
MOSFET discrete solution. Further more are internal
drain current sense eliminates the possibility of noise
generation caused by a sensing resistor. There are some
recommendations for PCB layout to enhance noise
immunity and suppress natural noise inevitable in power-
handling components.
There are typically two grounds in the conventional
SMPS: power ground and signal ground. The power
ground is the ground for primary input voltage and
power, while the signal ground is ground for PWM
controller. In FPS, those two grounds share the same
pin, GND. Normally the separate grounds do not share
the same trace and meet only at one point, the GND pin.
More, wider patterns for both grounds are good for large
currents by decreasing resistance.
Capacitors at the VCC and FB pins should be as close
as possible to the corresponding pins to avoid noise from
the switching device. Sometimes Mylar® or ceramic
capacitors with electrolytic for VCC are better for smooth
operation. The ground of these capacitors needs to
connect to the signal ground (not power ground).
Figure 37. Recommended PCB Layout
The cathode of the snubber diode should be close to the
drain pin to minimize stray inductance. The Y-capacitor
between primary and secondary should be directly
connected to the power ground of DC link to maximize
surge immunity.
Because the voltage range of feedback and sync line is
small, it is affected by the noise of the drain pin. Those
traces should not draw across or close to the drain line.
When the heat sink is connected to the ground, it should
be connected to the power ground. If possible, avoid
using jumper wires for power ground and drain.
Mylar® is a registered trademark of DuPont Teijin Films.
© 2008 Fairchild Semiconductor Corporation
FSQ0765RQ Rev. 1.0.1
www.fairchildsemi.com
17
2.74
2.34
(0.70)
10.36
9.96
B
A
6.88
6.48
C
5.18
4.98
3.40
3.20
3.28
3.08
Ø
16.08
15.68
(17.83)
(21.01)
(1.13)
1.30
R1.00
#2,4,6
R1.00
0.85
0.75
5PLCS
6PLCS
1.05
0.65
0.55
#1
#6
4.90
4.70
#1,3,5
6PLCS
0.61
0.46
3.18
A B
2.19
1.75
0.05 C
1.27
0.20
3.81
5°
5°
NOTES:
A) NO PACKAGE STANDARD APPLIES.
B) DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR EXTRUSIONS.
C) DIMENSIONS ARE IN MILLIMETERS.
D) DRAWING FILENAME : MKT-TO220E06REV2
4.80
4.40
APPROVALS
DRAWN:
DATE
03MAR2010
J.U. COMPARATIVO JR.
CHECKED:
L. STA CRUZ
APPROVED:
6LD,TO220,FULLPACK
L-FORMING
M.R. GESTOLE
C.N. TANGPUZ
SCALE
SIZE
DRAWING NUMBER
REV
1:1 N/A
2
MKT-T0220E06
FORMERLY: N/A
SHEET :
1
OF
1
[MM]
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