FSUSB104UMX [ONSEMI]
小功率,两端口,高速 USB2.0 (480Mbps) 开关;型号: | FSUSB104UMX |
厂家: | ONSEMI |
描述: | 小功率,两端口,高速 USB2.0 (480Mbps) 开关 开关 |
文件: | 总10页 (文件大小:375K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/
or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application
by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized
for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for
implantation in the human body. Should Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and holdonsemi and its officers, employees,
subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal Opportunity/Affirmative
Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. Other names and brands may be claimed as the property of others.
FSUSB104 — Low-Power, Two-Port, Hi-Speed,
USB2.0 (480 Mbps) Switch
Features
Description
.
.
.
Low On Capacitance: 3.7 pF Typical
The FSUSB104 is a bi-directional, low -pow er, tw o-port,
Hi-Speed, USB2.0 sw itch. Configured as a double-pole,
double-throw sw itch (DPDT) sw itch, it is optimized for
sw itching betw een tw o Hi-Speed (480 Mbps) sources or
a Hi-Speed and Full-Speed (12 Mbps) source.
Low On Resistance: 3.9 Ω Typical
Low Pow er Consumption: 1 μA Maximum
-15 μA Maximum ICCT over an Expanded Voltage
Range (VIN=1.8 V, VCC=4.3 V)
The FSUSB104 is compatible w ith the requirements of
USB2.0 and features an extremely low on capacitance
(CON) of 3.7 pF. The w ide bandw idth of this device
(720 MHz) exceeds the bandw idth needed to pass the
third harmonic, resulting in signals w ith minimum edge
and phase distortion. Superior channel-to-channel
crosstalk also minimizes interference.
.
.
.
.
Wide -3 db Bandw idth: > 720 MHz
Packaged in Pb-free 10-Lead UMLP (1.4 x 1.8 mm)
8 kV ESD Rating, >16 kV Pow er/GND ESD Rating
Pow er-Off Protection on All Ports When VCC=0 V
-D+/D- Pins Tolerate up to 5.25 V
The FSUSB104 contains special circuitry on the sw itch
I/O pins for applications w here the VCC supply is
pow ered-off (VCC=0), w hich allow s the device to
w ithstand an over-voltage condition. This device is
designed to minimize current consumption even w hen
the control voltage applied to the SEL pin is low er than
the supply voltage (VCC). This feature is especially
valuable to ultra-portable applications, such as cell
phones, allow ing for direct interface w ith the general-
purpose I/Os of the baseband processor. Other
applications include sw itching and connector sharing in
portable cell phones, PDAs, digital cameras, printers,
and notebook computers.
Applications
.
.
Cell phone, PDA, Digital Camera, and Notebook
LCD Monitor, TV, and Set-Top Box
Ordering Information
Top
Mark
Operating Temperature
Range
Part Number
Package
10-Lead, Quad, Ultrathin Molded Leadless Package
(UMLP), 1.4 x 1.8 mm
FSUSB104UMX
JF
-40 to +85°C
HSD1+
HSD2+
D+
D-
HSD1-
HSD2-
Sel
Control
/OE
Figure 1. Analog Symbol
© 2008 Semiconductor Components Industries, LLC.
November-2017, Rev. 2
Publication Order Number:
FSUSB104/D
Pin Assignments
D- D+
2
1
GND
3
4
10 Sel
9
HSD2-
V
CC
5
8
/OE
HSD2+
6
7
HSD1- HSD1+
Figure 2. Pin Assignment (Top Through View)
Pin Definitions
Pin #
Name
Description
1
2
D+
D-
USB Data Bus
USB Data Bus
3
GND
HSD2-
HSD2+
HSD1-
HSD1+
/OE
Ground
4
Multiplexed Source Inputs
Multiplexed Source Inputs
Multiplexed Source Inputs
Multiplexed Source Inputs
Sw itch Enable
5
6
7
8
9
VCC
Supply Voltage
10
Sel
Sw itch Select
Truth Table
Sel
/OE
Function
X
HIGH
LOW
LOW
Disconnect
LOW
HIGH
D+, D-=HSD1+, HSD1-
D+, D-=HSD2+, HSD2-
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2
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
VCC
Parameter
Min.
-0.5
-0.5
-0.5
-50
Max.
5.6
Unit
V
Supply Voltage
VCNTRL
VSW
DC Input Voltage (S, /OE)(1)
DC Sw itch I/O Voltage(1)
DC Input Diode Current
DC Output Current
VCC
5.25
V
V
I
IK
mA
mA
°C
IOUT
50
+150
7
TSTG
Storage Temperature
-65
All Pins
Human Body Model, JEDEC: JESD22-A114
Charged Device Model, JEDEC: JESD22-C101
I/O to GND
Pow er to GND
8
16
2
ESD
kV
Note:
1. The input and output negative ratings may be exceeded if the input and output diode current ratings are
observed.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. ON Semiconductor
does not recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
VCC
Parameter
Min.
3.0
0
Max.
4.4
Unit
V
Supply Voltage
VCNTRL
VSW
Control Input Voltage (S, /OE)(2)
VCC
4.5
V
Sw itch I/O Voltage
-0.5
-40
V
TA
Operating Temperature
+85
°C
Note :
2. The control input must be held HIGH or LOW and it must not float.
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3
DC Electrical Characteristics
All typical values are at 25°C unless otherw ise specified.
TA=- 40ºC to +85ºC
Symbol
Parameter
Conditions
VCC (V)
Units
Min. Typ. Max.
VIK
VIH
Clamp Diode Voltage
Input Voltage High
I =-18 mA
IN
3.0
3.0 to 3.6
4.3
-1.2
V
V
1.3
1.7
0.5
0.7
V
3.0 to 3.6
4.3
V
VIL
Input Voltage Low
V
I
Control Input Leakage
Off State Leakage
VSW=0 to VCC
4.3
-1
-2
1
2
µA
IN
0 ≤ Dn, HSD1n, HSD2n
≤ 3.6V
IOZ
4.3
0
µA
µA
Ω
Pow er-Off Leakage Current
(All I/O Ports)
VSW=0 V to 4.3 V, VCC=0 V
Figure 4
IOFF
RON
-2
2
HS Sw itch On Resistance(3)
3.0
3.9
6.5
VSW=0.4 V, ION=-8 mA
Figure 3,
∆RON
HS Delta Ron(4)
VSW=0.4 V, ION=-8 mA
VCNTRL=0 or VCC, IOUT=0
VCNTRL =2.6 V, VCC=4.3 V
VCNTRL =1.8 V, VCC=4.3 V
3.0
4.3
4.3
4.3
0.65
Ω
ICC
Quiescent Supply Current
1.0
µA
µA
µA
10.0
15.0
Increase in ICC Current per
Control Voltage and VCC
ICCT
Note s:
3. Measured by the voltage drop betw een HSDn and Dn pins at the indicated current through the sw itch.
On resistance is determined by the low er of the voltage on the tw o (HSDn or Dn ports).
4. Guaranteed by characterization. Not tested in production.
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4
AC Electrical Characteristics
All typical value are for VCC=3.3 V at 25°C unless otherw ise specified.
TA=- 40ºC to +85ºC
Min. Typ. Max.
Symbol
Parameter
Conditions
VCC (V)
Units
RL=50 Ω, CL=5 pF
VSW=0.8 V
Figure 5, Figure 6
Turn-On Time
S, /OE to Output
tON
3.0 to 3.6
13
30
ns
RL=50 Ω, CL=5 pF
VSW=0.8 V
Figure 5, Figure 6
Turn-Off Time
S, /OE to Output
tOFF
3.0 to 3.6
3.3
12
25
ns
ns
ns
CL=5 pF, RL=50 Ω
Figure 5, Figure 7
tPD
Propagation Delay(5)
Break-Before-Make
Off Isolation
0.25
RL=50 Ω, CL=5 pF
VSW1=VSW2=0.8 V
Figure 9
tBBM
3.0 to 3.6
2.0
6.5
RL=50 Ω, f=240 MHz
Figure 11
OIRR
Xtalk
3.0 to 3.6
3.0 to 3.6
-30
-45
720
550
dB
dB
Non-Adjacent Channel
Crosstalk
RL=50 Ω, f=240 MHz
Figure 12
RL=50 Ω, CL=0 pF
Figure 10
MHz
MHz
BW
-3db Bandw idth
3.0 to 3.6
RL=50 Ω, CL=5 pF
Figure 10
Note :
5. Guaranteed by characterization. Not tested in production.
USB Hi-Speed-Related AC Electrical Characteristics
TA=- 40ºC to +85ºC
Min. Typ. Max.
Symbol
Parameter
Conditions
Vcc (V)
Units
Skew of Opposite Transitions
of the Same Output(6)
CL=5 pF, RL=50 Ω
Figure 8
tSK(P)
3.0 to 3.6
20
ps
RL=50 Ω, CL=5 pf,
tR=tF=500ps (10-90%) at
480 Mbps
tJ
Total Jitter(6)
3.0 to 3.6
200
ps
(PRBS=215 – 1)
Note:
6. Guaranteed by characterization. Not tested in production.
Capacitance
TA=- 40ºC to +85ºC
Min. Typ. Max.
1.5
Symbol
Parameter
Conditions
Units
C
IN
Control Pin Input Capacitance
D+/D- On Capacitance
VCC=0 V
V
CC=3.3 V, /OE=0 V, f=240 MHz
CON
3.7
2.0
pF
Figure 14
V
CC and /OE=3.3 V
See Figure 13
COFF
D1n, D2n Off Capacitance
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5
Test Diagrams
VON
IDn(OFF)
NC
A
HSD
n
V
Dn
SW
V
Select
SW
GND
ION
GND
V
Sel= 0 orVcc
Select
GND
**Each switch port is tested separately
V
Sel= 0 orVcc
R
ON = VON / ION
Figure 3. On Resistance
Figure 4. Off Leakage
HSD
n
tRISE= 2.5ns
tFALL = 2.5ns
Dn
C
V
SW
V
CC
VOUT
R
90%
CC /2
90%
CC /2
R
GND
L
L
S
Input– V/OE, V
Sel
V
V
GND
10%
10%
90%
GND
V
V
Sel
OH
90%
GND
Output- VOUT
VOL
RL , R , and CL are functions of the application
S
tON
tOFF
environment (see AC Tables for specific values)
CL includes test fixture and stray capacitance.
Figure 5. AC Test Circuit Load
Figure 6. Turn-On / Turn-Off Waveforms
tRISE
tFALL
= 500ps
= 500ps
+400mV
-400mV
400mV
90%
0V
90%
50%
50%
Input
0V
10%
10%
tPLH
tPHL
VOH
Output
50%
50%
Output
VOL
tPHL
tPLH
Figure 7. Propagation Delay (tRtF – 500 ps)
Figure 8. Intra-Pair Skew Test tSK(P)
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6
Test Diagrams (Continued)
tRISE= 2.5ns
Vcc
Input - VSel
HSD
90%
Vcc/2
n
Dn
C
V
SW1
10%
0V
VOUT
GND
L
V
R
L
SW2
VOUT
GND
0.9*Vout
GND
0.9*Vout
R
S
tBBM
V
Sel
RL , R , and CL are functions of the application
S
GND
environment (see AC Tables for specific values)
CL includes test fixture and stray capacitance.
Figure 9. Break -Before -Make Interval Timing
Network Analyzer
RS
Network Analyzer
R
S
VIN
V
IN
V
GND
V
GND
S
R
S
T
GND
OUT
GND
VOUT
V
GND
V
Sel
Sel
V
GND
GND
GND
R
GND
T
RT
RS and RT are functions of the application
environment (see AC Tables for specific values).
Off isolation = 20 Log (VOUT / VIN
GND
GND
RS and RT are functions of the application
)
environment (see AC Tables for specific values).
Figure 10. Bandwidth
Figure 11. Channel Off Isolation
Network Analyzer
NC
R
S
V
IN
V
GND
S
GND
V
Sel
GND
R
T
GND
V
OUT
GND
R
T
RS and RT are functions of the application environment
(see AC Tables for specific values).
GND
Crosstalk = 20 Log (VOUT / VIN)
Figure 12. Non-Adjacent Channel-to-Channel Crosstalk
HSD
HSD
n
Capacitance
Meter
n
S
S
V
Capacitance
Meter
V
= 0 or V
cc
Sel
= 0 or V
cc
Sel
HSD
HSD
n
n
Figure 13. Channel Off Capacitance
Figure 14. Channel On Capacitance
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7
Physical Dimensions
0.05 C
1.40
A
B
2X
1.80
(9X)
0.563
1.70
PIN#1 IDENT
0.663
0.05 C
2X
TOP VIEW
0.50±.05
1
2.10
0.15±.05
0.10 C
0.40
0.225
(10X)
0.08 C
SEATING
PLANE
RECOMMENDED
LAND PATTERN
C
0.025±.025
SIDE VIEW
9X
0.45
1.45
0.55
0.40
1.40±.05
(0.20)4X
0.40±.05
(9X)
3
1.85
0.40
6
DETAIL A
0.225
(10X)
1.80±.05
4X
1
(0.60)
OPTIONAL MINIMIAL
TOE LAND PATTERN
PIN#1 IDENT
10
0.20±.05 (10X)
NOTES:
0.10 C A B
0.05 C
A. PACKAGE DOES NOT CONFORM TO
ANY JEDEC STANDARD.
BOTTOM VIEW
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 2009.
1.00±.05
D. LAND PATTERN RECOMMENDATION IS
EXISTING INDUSTRY LAND PATTERN.
45°
0.40±.05
E. DRAWING FILENAME: MKT-UMLP10Arev6.
DETAIL A
SCALE : 2X
PACKAGE
EDGE
LEAD
LEAD
OPTION 2
OPTION 1
SCALE : 2X
SCALE : 2X
Figure 15. 10-Lead, Ultrathin Molded Leadless Package (UMLP)
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8
ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the
United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A
listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make
changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor
products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by
ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do var y in different applications and
actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts.
ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for
use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or
any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs,
damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or
unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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