FSUSB40L10X [ONSEMI]
小功率,两端口,高速 USB2.0 (480Mbps) 开关;型号: | FSUSB40L10X |
厂家: | ONSEMI |
描述: | 小功率,两端口,高速 USB2.0 (480Mbps) 开关 开关 |
文件: | 总12页 (文件大小:992K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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December 2009
FSUSB40 — 低功耗双端口高速 USB2.0 (480Mbps) 开关
特性
描述
FSUSB40是双向低功耗双端口高速USB2.0 开关。结构
类 似 于 双 刀 双 掷 开 关 , 它 对 于 切 换 两 个 高 速 源
(480Mbps)或一个高速和全速源(12Mbps)是优化选择。
低导通电容: 5.9pF典型值
低导通电阻: 3.9Ω 典型值
低功耗: 1μA最大值
FSUSB40是兼容USB2.0要求和拥有5.9pF超低电容的特
性。元件宽广的带宽(720MHz)超过了需要通过三阶谐波
的带宽 ,从而可以最小化边缘和相位的失真,超高品质
的通道与通道之间的串扰特性也最小化了干扰。
-在扩展的电压范围内(VIN=1.8V, VCC=4.3V),
最大ICCT电流为15μA
宽广的 -3db带宽: > 720MHz
封装:
FSUSB40在开关的I/O管脚包含有特殊的电路针对当
VCC=0时允许元件耐过压的应用。这个元件被设计最小化
-无铅10-引脚 MicroPak™ (1.6 x 2.1mm)
-无铅10-引脚 UMLP (1.4 x 1.8mm)
了电流消耗即使用在SEL 管脚的控制电压低于供电电
压。这种特性对手机类超便携式应用尤其重要,通过它可
以直接与基带处理器通用I/O口连接. 其它应用包括在便携
式手机, PDAs, 数字相机, 打印机, 和笔记本电脑中的切换
和连接。
8kV的ESD, >16kV 电源对地 ESD
当VCC=0V时所有管脚有断电保护
-D+/D-管脚可耐压高达5.25V
在无需额外元件的情况下所有的USB端口可耐过压
高达5.25V
重要注解
欲知其它详情, 请联系 analogswitch@fairchildsemi.com.
应用
手机, PDA, 数字相机, 和笔记本
LCD显示屏, TV, 和机顶盒
订货信息
Eco
Status
订货号码
表面标记 操作温度范围
封装
FSUSB40L10X
FSUSB40UMX
HD
HC
-40 到 +85°C
-40 到+85°C
RoHS
Green
10-引脚MicroPak™ 1.6 x 2.1mm, JEDEC MO-255B
10-引脚, 方型, 超薄模塑无脚封 (UMLP), 1.4 x 1.8mm
MicroPak™ is a trademark of Fairchild Semiconductor Corporation.
For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html
HSD1+
D+
HSD2+
HSD1-
D-
HSD2-
Sel
Control
/OE
图1:模拟符号
© 2007 Fairchild Semiconductor Corporation
FSUSB40 • Rev. 1.0.8
www.fairchildsemi.com
管脚分配图
Vcc
10
1
Sel
9
/OE
HSD2+ HSD1+
2
1
2
HSD1+
HSD2+
D+
HSD1-
HSD2-
D-
D+
GND
D-
3
4
10 Sel
8
9
Vcc
3
4
7
6
5
8
/OE
6
7
HSD2- HSD1-
5
GND
图2:MicroPak™ 分配图 (俯视图)
图3:管脚分配图 UMLP (俯视图)
管脚定义
MicroPak™ Pin #
UMLP Pin #
管脚名称
/OE
描述
9
8
10
开关使能
1
4, 6
Sel
开关选择脚
USB 数据线
多路复用源输入
Ground
3, 5
D+, D-
2, 3, 7, 8
5
1, 2, 6, 7
4
HSDn+, HSDn-
GND
真值表
Sel
/OE
功能
断开
X
H
L
L
L
D+, D-=HSD1+, HSD1-
D+, D-=HSD2+, HSD2-
H
© 2007 Fairchild Semiconductor Corporation
FSUSB40 • Rev. 1.0.8
www.fairchildsemi.com
2
最大绝对额定值
超出绝对最大额定值会破坏设备 , 设备会不工作或者说不建议设备在和超过建议的工作条件下被操作. 另外, 过长的暴露
在超过建议工作条件下会影响设备的可靠性. 这种绝对最大额定值仅仅是极端额定值.
表达符号
VCC
参数
最小值
-0.5
最大值
+5.5
单位
V
供电电压
VCNTRL
VSW
DC 输入电压 (S, /OE)(1)
DC 开关 I/O 电压(1)
DC 输入二极管电流
DC输出电流
-0.5
VCC
V
-0.50
-50
5.25
V
IIK
mA
mA
°C
IOUT
100
+150
7
TSTG
储存温度
-65
所有管脚
I/O对地
人体电流模式, JEDEC: JESD22-A114
充放电模式, JEDEC: JESD22-C101
8
16
2
ESD
kV
电源对地
注:
1. 如输入及输出二极管电流额定值均达到时则可能会超出输入及输出负额定值。
推荐工作条件
推荐工作条件表中定义的是实际元件工作的条件, 推荐工作条件指定用于保证实现数据表规范的最佳性能, Fairchild
建议不得超出以上值或设计至最大绝对额定值。
表达符号
VCC
参数
最小值
3.0
最大值
4.3
单位
V
供电电压
VCNTRL
VSW
控制输入电压 (S, /OE) (2)
开关 I/O电压
操作温度
0
VCC
V
-0.5
-40
4.5
V
TA
+85
°C
注:
2. 控制输入必须保持高平或 低平且不得悬空.
© 2007 Fairchild Semiconductor Corporation
FSUSB40 • Rev. 1.0.8
www.fairchildsemi.com
3
DC 电气特性
如未说明均为25ºC下的标准值.
TA=- 40ºC 至 +85ºC
表达符号
参数
条件
VCC (V)
单位
最小 典型 最大
钳位二极管电压
VIK
VIH
IIN=-18mA
3.0
-1.2
V
V
3.0 至 3.6
4.3
1.3
1.7
0.5
0.7
输入高电平
V
3.0 至 3.6
4.3
V
VIL
输入低电平
V
IIN
控制输入漏电流
断开漏电流
VSW=0 to VCC
4.3
-1
-2
1
2
µA
0 ≤ Dn, HSD1n, HSD2n
≤ 3.6V
IOZ
4.3
0
µA
µA
Ω
VSW=0V to 4.3V, VCC=0V
见图5
IOFF
RON
断电漏电流 (所有I/O端口)
-2
2
VSW=0.4V, ION=-8mA
高速开关导通电阻(3)
3.0
3.9
6.5
见图4
∆RON
高速导通电阻差(4)
静态供电电流
VSW=0.4V, ION=-8mA
3.0
4.3
0.65
Ω
ICC
VCNTRL=0 or VCC, IOUT=0
1.0
µA
V
CNTRL=2.6V VCC=4.3V
4.3
4.3
10.0
15.0
µA
µA
控制电压和VCC 增加时ICC
相应的增加量
ICCT
VCNTRL=1.8V VCC=4.3V
注:
3. 在开关指定电流下通过测量管脚 HSDn 和 Dn 管脚之间的电压降获得. 导通电阻由两管脚上较低的电压决定.
4. 由特性保证.
© 2007 Fairchild Semiconductor Corporation
FSUSB40 • Rev. 1.0.8
www.fairchildsemi.com
4
AC 电气特性
如未说明均为 25ºC, 3.3V VCC 下的标准值.
TA=- 40ºC 至 +85ºC
表达符号
参数
条件
VCC (V)
单位
最小 典型
最大
RL=50Ω, CL=5pF; VSW=0.8V
见图 6, 7
tON
tOFF
tPD
开启时间 S, /OE到输出
关断时间 S, /OE到输出
传播延迟(5)
3.0 至 3.6
3.0 至 3.6
3.3
13
30
ns
ns
ns
RL=50Ω, CL=5pF; VSW=0.8V
见图 6, 7
12
25
CL=5 pF, RL=50Ω
见图 6, 8
0.25
RL=50Ω, CL=5pF
VSW1=VSW2=0.8V
tBBM
先断后开
3.0 至 3.6
2.0
6.5
ns
见图 12
RL=50Ω, f=240MHz
见图 14
OIRR
隔离度
3.0 至 3.6
3.0 至 3.6
-30
-45
720
550
dB
dB
RL=50Ω, f=240MHz
见图 15
Xtalk
非相邻通道串扰
RL=50Ω, CL=0pF
见图 13
MHz
MHz
BW
-3db带宽
3.0 至 3.6
RL=50Ω, CL=5pF
见图 13
注:
5. 由特性保证.
与USB高速相关的AC电气特性
TA=- 40ºC 至 +85ºC
表达符号
参数
条件
Vcc (V)
单位
最小 典型 最大
同一输出相反传输方向上的 CL=5pF, RL=50Ω
tSK(P)
3.0 至 3.6
3.0 至 3.6
20
ps
ps
偏差(6)
见图 9
RL=50ꢀ, CL=5pf,
tR=tF=500ps (10-90%) 在
tJ
总抖动(6)
200
480Mbps时
(PRBS=215 – 1)
Note:
6. 由特性保证.
电容
TA=- 40ºC 至 +85ºC
表达符号
参数
条件
单位
最小
典型 最大
CIN
控制管脚输入电容
VCC=0V
1.5
VCC=3.3V, /OE=0V, f=1MHz
见图 11
CON
D+/D- 导通电容
5.9
2.0
6.5
pF
VCC and /OE=3.3V
见图 10
COFF
D1n, D2n 断开电容
© 2007 Fairchild Semiconductor Corporation
FSUSB40 • Rev. 1.0.8
www.fairchildsemi.com
5
测试图
VON
IDn(OFF)
NC
A
HSD
n
V
Dn
SW
V
Select
SW
GND
ION
GND
V
Sel= 0 orVcc
Select
GND
**Each switch port is tested separately
V
Sel= 0 orVcc
R
ON = VON / ION
图4.导通电阻
图5.断开漏电流
HSD
n
tRISE= 2.5ns
tFALL = 2.5ns
Dn
V
SW
V
CC
VOUT
C
L
R
90%
CC /2
90%
CC /2
R
GND
L
S
Input– V/OE, VSel
V
V
GND
10%
GND
10%
90%
V
VOH
Sel
90%
tON
GND
Output- VOUT
VOL
RL , RS, and CL are functions of the application
environment (see AC Tables for specific values)
CL includes test fixture and stray capacitance.
tOFF
图6.AC测试电路负载
图7.开启/ 关断波形
tRISE
tFALL
= 500ps
= 500ps
+400mV
-400mV
400mV
90%
0V
90%
50%
50%
Input
0V
10%
10%
tPLH
tPHL
VOH
Output
50%
50%
Output
VOL
tPHL
tPLH
图8.传播延迟 (tRtF – 500ps)
图9.对内偏移测试tSK(P)
HSD
n
HSD
n
Capacitance
Meter
S
V
S
Capacitance
Meter
= 0 or V
cc
Sel
V
= 0 or V
cc
Sel
HSD
n
HSD
n
图10.通道断开电容
图11.通道导通电容
© 2007 Fairchild Semiconductor Corporation
FSUSB40 • Rev. 1.0.8
www.fairchildsemi.com
6
测试图(续)
tRISE= 2.5ns
Vcc
Input - VSel
HSD
90%
Vcc/2
n
Dn
C
V
SW1
10%
0V
VOUT
GND
L
V
R
L
SW2
VOUT
GND
0.9*Vout
GND
0.9*Vout
R
S
tBBM
V
Sel
RL , RS, and CL are functions of the application
environment (see AC Tables for specific values)
CL includes test fixture and stray capacitance.
GND
图12.先断后开间隔时间
Network Analyzer
RS
VIN
VS
GND
GND
GND
V
Sel
VOUT
GND
RT
GND
RS and RT are functions of the application
environment (see AC Tables for specific values).
图13. 带宽
Network Analyzer
R
S
V
IN
V
S
GND
R
T
GND
V
GND
Sel
V
OUT
GND
GND
R
T
RS and RT are functions of the application
environment (see AC Tables for specific values).
GND
Off isolation = 20 Log (VOUT / VIN)
图14. 通道隔离度
Network Analyzer
NC
R
S
V
IN
V
GND
S
GND
V
Sel
GND
R
T
GND
V
OUT
GND
R
T
RS and RT are functions of the application environment
(see AC Tables for specific values).
GND
Crosstalk = 20 Log (VOUT / VIN)
图15. 非相邻通道串扰
© 2007 Fairchild Semiconductor Corporation
FSUSB40 • Rev. 1.0.8
www.fairchildsemi.com
7
物理尺寸
0.10
C
2.10
A
2X
1.62
B
KEEPOUT ZONE, NO TRACES
OR VIAS ALLOWED
(0.11)
0.56
1.12
1.60
PIN1 IDENT IS
2X LONGER THAN
OTHER LINES
0.10 C
(0.35) 10X
(0.25)
2X
10X
0.50
TOP VIEW
RECOMMENDED LAND PATTERN
0.55 MAX
0.05 C
0.05 C
0.05
0.00
(0.20)
C
0.35
0.25
SIDE VIEW
(0.15)
D
DETAIL A
(0.36)
0.35
0.25
0.65
0.55
0.35
0.25
DETAIL A 2X SCALE
1
4
0.56
NOTES:
10
5
A. PACKAGE CONFORMS TO JEDEC
REGISTRATION MO-255, VARIATION UABD .
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
D. PRESENCE OF CENTER PAD IS PACKAGE
SUPPLIER DEPENDENT. IF PRESENT IT
IS NOT INTENDED TO BE SOLDERED AND
HAS A BLACK OXIDE FINISH.
(0.29)
0.35
6
9
9X
0.25
0.50
0.25
0.15
9X
1.62
0.10
0.05
C
C
A B
ALL FEATURES
E. DRAWING FILENAME: MKT-MAC10Arev5.
BOTTOM VIEW
图16.10引脚MicroPak™
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2007 Fairchild Semiconductor Corporation
FSUSB40 • Rev. 1.0.8
www.fairchildsemi.com
8
物理尺寸
0.15
C
1.40
A
2X
1.700
9X
0.563
B
0.663
1
1.80
2.100
PIN #1 QUADRANT
0.400
0.15
C
2X
10X
0.225
TOP VIEW
RECOMMENDED LAND PATTERN
0.55 MAX.
1.450
9X
0.10
0.08
C
0.550
0.400
0.450
0.152
SEATING
PLANE
C
0.050
C
1.850
SIDE VIEW
10X
0.225
3
OPTIONAL MINIMIAL TOE LAND PATTERN
0.40
10X
6
0.35
0.45
9X
1
10
0.45
0.55
0.500
0.100
0.15
0.25
0.10
0.05
C
C
A B
0.100
0.100
BOTTOM VIEW
DETAIL A
PIN #1 TERMINAL
SCALE: 2X
A. DIMENSIONS ARE IN MILLIMETERS.
B. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994
C. DRAWING FILENAME: UMLP10Arev2
图17. 10引脚方型, 超薄模塑无脚封装(UMLP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2007 Fairchild Semiconductor Corporation
FSUSB40 • Rev. 1.0.8
www.fairchildsemi.com
9
© 2007 Fairchild Semiconductor Corporation
FSUSB40 • Rev. 1.0.8
www.fairchildsemi.com
10
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ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
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