FSUSB42UMX_12 [FAIRCHILD]
Low-Power, Two-Port, Hi-Speed, USB2.0 (480Mbps) UART Switch;
| 型号： | FSUSB42UMX_12 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Low-Power, Two-Port, Hi-Speed, USB2.0 (480Mbps) UART Switch |
| 文件： | 总10页 (文件大小：723K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Click here for this datasheet
translated into Chinese!
February 2012
FSUSB42 — Low-Power, Two-Port, Hi-Speed,
USB2.0 (480Mbps) UART Switch
Description
Features
The FSUSB42 is a bi-directional, low-power, two-port,
Hi-Speed, USB2.0 switch. Configured as a double-pole,
double-throw switch (DPDT) switch, it is optimized for
switching between two Hi-Speed (480Mbps) sources or
a Hi-Speed and Full-Speed (12Mbps) source.
.
.
.
Low On Capacitance: 3.7pF Typical
Low On Resistance: 3.9Ω Typical
Low Power Consumption: 1μA Maximum
-15μA Maximum ICCT over an Expanded Voltage
The FSUSB42 is compatible with the requirements of
USB2.0 and features an extremely low on capacitance
(CON) of 3.7pF. The wide bandwidth of this device
(720MHz) exceeds the bandwidth needed to pass the
third harmonic, resulting in signals with minimum edge
and phase distortion. Superior channel-to-channel
crosstalk also minimizes interference.
Range (VIN=1.8V, VCC=4.4V)
.
.
Wide -3db Bandwidth: > 720MHz
Packaged in:
-10-Lead UMLP (1.4 x 1.8mm)
-10-Lead MSOP
.
.
8kV ESD Rating, >16kV Power/GND ESD Rating
Over-Voltage Tolerance (OVT) on all USB Ports
Up to 5.25V without External Components
The FSUSB42 contains special circuitry on the switch
I/O pins for applications where the VCC supply is
powered-off (VCC=0), which allows the device to
withstand an over-voltage condition. This device is
designed to minimize current consumption even when
the control voltage applied to the SEL pin is lower than
the supply voltage (VCC). This feature is especially
valuable to ultra-portable applications, such as cell
phones, allowing for direct interface with the general-
purpose I/Os of the baseband processor. Other
applications include switching and connector sharing in
portable cell phones, PDAs, digital cameras, printers,
and notebook computers.
Applications
.
.
Cell phone, PDA, Digital Camera, and Notebook
LCD Monitor, TV, and Set-Top Box
IMPORTANT NOTE:
For additional performance information, please contact
analogswitch@fairchildsemi.com.
Ordering Information
Operating Temperature
Part Number Top Mark
Range
Package
10-Lead, Quad, Ultrathin Molded Leadless Package
(UMLP), 1.4 x 1.8mm
FSUSB42UMX
FSUSB42MUX
HE
-40 to +85°C
-40 to +85°C
10-Lead, Molded Small Outline Package (MSOP)
JEDEC MO-187, 3.0mm Wide
FSUSB42
MicroPak™ is a trademark of Fairchild Semiconductor Corporation.
HSD1+
HSD2+
D+
D-
HSD1-
HSD2-
Sel
Control
/OE
Figure 1. Analog Symbol
© 2007 Fairchild Semiconductor Corporation
FSUSB42 • Rev. 1.1.5
www.fairchildsemi.com
Pin Assignments
V
/OE
CC
10
9
1
2
3
4
5
D- D+
Sel
HSD2+
HSD2-
HSD1+
HSD1-
2
1
GND
3
4
10 Sel
D+
8
9
HSD1-
Vcc
5
8
/OE
HSD1+
6
7
D-
7
HSD2- HSD2+
GND
6
Figure 2. Pin Assignment 10L UMLP
(Top Through View)
Figure 3. Pin Assignment 10L MSOP
(Top Through View)
Pin Definitions
UMLP Pin#
MSOP Pin#
Name
D+
Description
1
2
3
4
USB Data Bus
D-
USB Data Bus
3
5
GND
HSD1-
HSD1+
HSD2-
HSD2+
/OE
Ground
4
6
Multiplexed Source Inputs (UART / USB)
Multiplexed Source Inputs (UART / USB)
Multiplexed Source Inputs (USB Only)
Multiplexed Source Inputs (USB Only)
Switch Enable
5
7
6
8
7
9
8
10
1
9
VCC
Supply Voltage
10
2
Sel
Switch Select
Truth Table
Sel
X
/OE
HIGH
LOW
LOW
Function
Disconnect
LOW
HIGH
D+, D-=HSD1+, HSD1-
D+, D-=HSD2+, HSD2-
© 2007 Fairchild Semiconductor Corporation
FSUSB42 • Rev. 1.1.5
www.fairchildsemi.com
2
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
VCC
Parameter
Min.
-0.5
-0.5
-0.50
-50
Max.
5.6
Unit
V
Supply Voltage
VCNTRL
VSW
DC Input Voltage (S, /OE)(1)
DC Switch I/O Voltage(1)
VCC
V
5.25
V
IIK
DC Input Diode Current
mA
mA
°C
IOUT
DC Output Current
100
+150
1
TSTG
MSL
Storage Temperature
-65
Moisture Sensitivity Level (JEDEC J-STD-020A)
Level
All Pins
7
8
I/O to GND
Power to GND
D+/D-
Human Body Model, JEDEC: JESD22-A114
16
ESD
kV
9
15
8
Air Discharge
Contact
IEC 61000-4-2 System on USB Connector
Pins D+ & D-
2
Charged Device Model, JEDEC: JESD22-C101
Note:
1. The input and output negative ratings may be exceeded if the input and output diode current ratings are observed.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Min.
3.0
0
Max.
4.4
Unit
V
VCC
Supply Voltage
(2)
VCNTRL
Control Input Voltage (S, /OE)
Switch I/O Voltage
VCC
4.5
V
VSW
TA
-0.5
-40
V
Operating Temperature
+85
°C
Note:
2. The control input must be held HIGH or LOW and it must not float.
© 2007 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSUSB42 • Rev. 1.1.5
3
DC Electrical Characteristics
All typical value are at TA=25°C unless otherwise specified.
TA=- 40°C to +85°C
Symbol
VIK
Parameter
Clamp Diode Voltage
Input Voltage High
Condition
VCC (V)
Unit
Min. Typ. Max.
IIN=-18mA
3.0
3.0 to 3.6
4.3
-1.2
V
V
1.3
1.7
0.5
0.7
VIH
V
3.0 to 3.6
4.3
V
VIL
Input Voltage Low
V
IIN
Control Input Leakage
Off State Leakage
VSW=0 to VCC
0 to 4.3
-1
-2
1
2
µA
0 Dn, HSD1n, HSD2n
3.6V
IOZ
4.3
0
µA
µA
Power-Off Leakage Current
(All I/O Ports)
VSW=0V to 4.3V, VCC=0V
Figure 5
IOFF
RON
-2
2
VSW=0.4V, ION=-8mA
Figure 4,
HS Switch On Resistance(3)
3.0
3.9
6.5
(4)
∆RON
HS Delta RON
VSW=0.4V, ION=-8mA
VCNTRL=0 or VCC, IOUT=0
VCNTRL=2.6V, VCC=4.3V
VCNTRL=1.8V, VCC=4.3V
3.0
4.3
4.3
4.3
0.65
ICC
Quiescent Supply Current
1
µA
µA
µA
10
15
Increase in ICC Current per
Control Voltage and VCC
ICCT
Notes:
3. Measured by the voltage drop between HSDn and Dn pins at the indicated current through the switch.
On resistance is determined by the lower of the voltage on the two (HSDn or Dn ports).
4. Guaranteed by characterization.
© 2007 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSUSB42 • Rev. 1.1.5
4
AC Electrical Characteristics
All typical value are for VCC=3.3V at TA=25°C unless otherwise specified.
TA=- 40°C to +85°C
Min. Typ. Max.
Symbol
Parameter
Condition
VCC (V)
Unit
RL=50Ω, CL=5pF
SW=0.8V
Figure 6, Figure 7
Turn-On Time
S, /OE to Output
tON
V
3.0 to 3.6
13
30
25
ns
RL=50Ω, CL=5pF
Turn-Off Time
S, /OE to Output
tOFF
VSW=0.8V
3.0 to 3.6
3.3
12
ns
ns
ns
Figure 6, Figure 7
CL=5 pF, RL=50Ω
Figure 6, Figure 8
tPD
Propagation Delay(5)
Break-Before-Make
Off Isolation
0.25
RL=50Ω, CL=5pF
VSW1=VSW2=0.8V
Figure 10
tBBM
3.0 to 3.6
2.0
6.5
RL=50Ω, f=240MHz
Figure 12
OIRR
3.0 to 3.6
3.0 to 3.6
-30
-45
720
550
dB
dB
Non-Adjacent Channel
Crosstalk
RL=50Ω, f=240MHz
Figure 13
Xtalk
RL=50Ω, CL=0pF
Figure 11
MHz
MHz
BW
-3db Bandwidth
3.0 to 3.6
RL=50Ω, CL=5pF
Figure 11
Note:
5. Guaranteed by characterization.
USB Hi-Speed-Related AC Electrical Characteristics
TA=- 40ºC to +85ºC
Min. Typ. Max.
Symbol
Parameter
Condition
VCC (V)
Unit
Skew of Opposite Transitions CL=5pF, RL=50Ω
tSK(P)
3.0 to 3.6
20
ps
of the Same Output(6)
Figure 9
RL=50ꢀ, CL=5pf,
tR=tF=500ps (10-90%) at
480Mbps
tJ
Total Jitter(6)
3.0 to 3.6
200
ps
(PRBS=215 – 1)
Note:
6. Guaranteed by characterization.
Capacitance
TA=- 40°C to +85°C
Symbol
Parameter
Condition
Unit
Min.
Typ. Max.
CIN
Control Pin Input Capacitance
D+/D- On Capacitance
VCC=0V
1.5
VCC=3.3V, /OE=0V, f=240MHz
Figure 15
CON
3.7
2.0
pF
VCC and /OE=3.3V
Figure 14
COFF
D1n, D2n Off Capacitance
© 2007 Fairchild Semiconductor Corporation
FSUSB42 • Rev. 1.1.5
www.fairchildsemi.com
5
Test Diagrams
VON
IDn(OFF)
NC
A
HSD
n
V
Dn
SW
V
Select
SW
GND
ION
GND
V
Sel= 0 orVcc
Select
GND
**Each switch port is tested separately
V
Sel= 0 orVcc
R
ON = VON / ION
Figure 4. On Resistance
Figure 5. Off Leakage
HSD
n
tRISE= 2.5ns
tFALL = 2.5ns
Dn
C
V
SW
V
CC
VOUT
90%
CC /2
90%
CC /2
R
R
GND
L
L
S
Input– V/OE, VSel
V
V
GND
10%
GND
10%
90%
V
VOH
Sel
90%
tON
GND
Output- VOUT
RL , R , and CL are functions of the application
VOL
S
tOFF
environment (see AC Tables for specific values)
CL includes test fixture and stray capacitance.
Figure 6. AC Test Circuit Load
Figure 7. Turn-On / Turn-Off Waveforms
tRISE
tFALL
= 500ps
= 500ps
+400mV
-400mV
400mV
90%
0V
90%
50%
50%
Input
0V
10%
10%
tPLH
tPHL
VOH
Output
50%
50%
Output
VOL
tPHL
tPLH
Figure 8. Propagation Delay (tRtF – 500ps)
Figure 9. Intra-Pair Skew Test tSK(P)
© 2007 Fairchild Semiconductor Corporation
FSUSB42 • Rev. 1.1.5
www.fairchildsemi.com
6
Test Diagrams (Continued)
tRISE= 2.5ns
Vcc
Input - VSel
HSD
90%
Vcc/2
n
Dn
C
V
SW1
10%
0V
VOUT
GND
L
V
R
L
SW2
VOUT
GND
0.9*Vout
GND
0.9*Vout
R
S
tBBM
V
Sel
RL , RS, and CL are functions of the application
environment (see AC Tables for specific values)
CL includes test fixture and stray capacitance.
GND
Figure 10. Break-Before-Make Interval Timing
Network Analyzer
RS
Network Analyzer
R
S
VIN
V
IN
V
GND
V
GND
S
R
S
T
GND
OUT
GND
VOUT
V
GND
V
Sel
Sel
V
GND
GND
GND
R
GND
T
RT
RS and RT are functions of the application
environment (see AC Tables for specific values).
Off isolation = 20 Log (VOUT / VIN
GND
GND
RS and RT are functions of the application
)
environment (see AC Tables for specific values).
Figure 11. Bandwidth
Figure 12. Channel Off Isolation
Network Analyzer
NC
R
S
V
IN
V
GND
S
GND
V
Sel
GND
R
T
GND
V
OUT
GND
R
T
RS and RT are functions of the application environment
(see AC Tables for specific values).
GND
Crosstalk = 20 Log (VOUT / VIN)
Figure 13. Non-Adjacent Channel-to-Channel Crosstalk
HSD
HSD
n
Capacitance
Meter
n
S
S
V
Capacitance
Meter
V
= 0 or V
cc
Sel
= 0 or V
cc
Sel
HSD
HSD
n
n
Figure 14. Channel Off Capacitance
Figure 15. Channel On Capacitance
© 2007 Fairchild Semiconductor Corporation
FSUSB42 • Rev. 1.1.5
www.fairchildsemi.com
7
Physical Dimensions
(9X)
0.563
1.70
0.15
C
1.40
A
B
0.663
2X
1
2.10
1.80
PIN#1 IDENT
0.40
0.15
C
0.225
(10X)
TOP VIEW
2X
RECOMMENDED
LAND PATTERN
0.55 MAX.
0.152
0.10 C
9X
0.45
1.45
0.08
C
0.55
0.40
SEATING
PLANE
C
0.05
SIDE VIEW
1.85
0.35
(9X)
0.45
0.225
(10X)
3
OPTIONAL MINIMIAL
TOE LAND PATTERN
0.40
6
DETAIL A
1
NOTES:
PIN#1 IDENT
A. PACKAGE DOES NOT FULLY CONFORM TO
0.15
0.25
10
JEDEC STANDARD.
(10X)
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
0.10
0.05
C A B
C
BOTTOM VIEW
D. LAND PATTERN RECOMMENDATION IS
BASED ON FSC DESIGN ONLY.
E. DRAWING FILENAME: MKT-UMLP10Arev3.
0.55
0.45
0.10
0.10
0.10
DETAIL A
SCALE : 2X
PACKAGE
EDGE
LEAD
LEAD
OPTION 2
SCALE : 2X
OPTION 1
SCALE : 2X
Figure 16. 10-Lead, Ultrathin Molded Leadless Package (UMLP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2007 Fairchild Semiconductor Corporation
FSUSB42 • Rev. 1.1.5
www.fairchildsemi.com
8
Physical Dimensions (Continued)
Figure 17. 10-Lead, Molded Small Outline Package (MSOP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2007 Fairchild Semiconductor Corporation
FSUSB42 • Rev. 1.1.5
www.fairchildsemi.com
9
© 2007 Fairchild Semiconductor Corporation
FSUSB42 • Rev. 1.1.5
www.fairchildsemi.com
10
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