FT10001L6X [ONSEMI]
重置计时器，带固定延迟和重置脉冲;
| 型号： | FT10001L6X |
| 厂家： | 
ONSEMI |
| 描述： | 重置计时器，带固定延迟和重置脉冲 脉冲 |
| 文件： | 总13页 (文件大小：1343K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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January 2012
FT10001
Reset Timer with Fixed Delay and Reset Pulse
Description
Features
The FT10001 is a timer for resetting a mobile device
where long reset times are needed. The long delay
helps avoid unintended resets caused by accidental key
presses. It has a fixed delay of 10 ±20% seconds. The
DSR pin enables Test Mode operation by immediately
forcing /RST1 LOW for factory testing.
.
.
.
.
.
.
.
.
.
Fixed Reset Delay: 10 Seconds
One Input Reset Pin
Open-Drain Output Pin with Fixed 530ms Pulse
1.8V to 5.0V Operation (TA=-40°C to +85°C)
1.7V to 5.0V Operation (TA=-25°C to +85°C)
1.65V to 5.00V Operation (TA=0°C to +85°C)
<1µA ICCQ Consumption
The FT10001 has one input for single-button resetting
capability. The device has a single open-drain output
with 0.5mA pull-down drive.
FT10001 draws minimal ICC current when inactive and
functions over a power supply range of 1.65V to 5.00V.
Zero-Second Test-Mode Enable
Integrated Pull-Up Resistor on /SRO
Applications
.
.
.
.
.
Cell Phones
Portable Media Players
Tablets
Mobile Devices
Consumer Medical
Ordering Information
Operating
Temperature Range
Packing
Part Number
Package
Method
5000 Units on
Tape and Reel
FT10001L6X
FT10001FHX
6-Lead, MicroPak™ 1.0 x 1.45mm, JEDEC MO-252
6-Lead, MicroPak2™ 1.0 x 1.0mm Body, .35mm Pitch
-40C to +85C
5000 Units on
Tape and Reel
-40C to +85C
© 2011 Fairchild Semiconductor Corporation
FT10001 • Rev. 1.0.1
www.fairchildsemi.com
Block Diagram
Figure 1.
Block Diagram
Pin Configuration
Figure 2.
Pad Assignments (Top-Through View)
Pin Definitions
Description
Pin # Name
Normal Operation
Zero-Second Factory-Test Mode
Open-drain output, active LOW
GND
1
2
3
4
/RST1 Open-drain output, active LOW
GND GND
/SR0 Reset input with integrated pull-up, active LOW Reset input with integrated pull-up, active LOW
VCC Power supply Power supply
Delay selection input; tie to GND during normal Delay selection input. Pull HIGH to enable Zero-
5
DSR
operation.(1)
second delay for factory test.
Used for device testing; tie to GND during
normal operation.
Used for device testing; tie to GND during normal
operation.
6
TEST
Note:
1. This pin must always be tied to either GND or VCC. It must not float.
© 2011 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FT10001 • Rev 1.0.1
2
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
VCC
VIN
Parameter
Condition
Min.
-0.5
-0.5
-0.5
Max.
7.0
Unit
V
Supply Voltage
DC Input Voltage
Output Voltage(2)
/SR0, DSR
/RST1
7.0
V
VOUT
IIK
7.0
V
DC Input Diode Current
DC Output Diode Current
DC Output Sink Current
VIN < 0V
VOUT < 0V
-50
mA
mA
mA
mA
C
IOK
-50
IOL
+50
100
+150
+150
+260
5
ICC
DC VCC or Ground Current per Supply Pin
Storage Temperature Range
TSTG
TJ
-65
Junction Temperature Under Bias
C
TL
Junction Lead Temperature, Soldering 10 Seconds
Power Dissipation
C
PD
mW
Human Body Model, JESD22-A114
4
ESD
Electrostatic Discharge Capability
kV
Charged Device Model, JESD22-C101
2
Note:
2. All output current Absolute Maximum Ratings must be observed.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Condition
Min. Max. Unit
1.8
1.7
5.0
5.0
-40C to +85C
VCC
Supply Voltage
V
-25C to +85C
0C to +85C
1.65
5.00
VCC=0V After Power Down,
Rising to 0.5V
tRFC
VCC Recovery Time After Power Down
5
ms
VIN
VOUT
IOL
Input Voltage
/SR0
0
0
5
V
V
Output Voltage
/RST1
5
DC Output Sink Current
Free-Air Operating Temperature
Thermal Resistance
/RST1, VCC=2.0V to 5.0V
+0.5
+85
350
mA
C
TA
-40
°C/W
JA
© 2011 Fairchild Semiconductor Corporation
FT10001 • Rev 1.0.1
www.fairchildsemi.com
3
DC Electrical Characteristics
Conditions of TA=-40°C to 80°C with VCC=1.8V - 5.0V OR TA=-25°C to 85°C with VCC=1.7V – 5.0V OR TA=0°C to
85°C with VCC=1.65V – 5.00V produce the performance characteristics below.
Symbol
Parameter
Condition
Min.
Typ. Max. Unit
VIH
Input High Voltage
DSR, /SR0
0.65 x VCC
V
0.25 x
V
VIL
Input Low Voltage
DSR, /SR0
VCC
VOL
RPU
Low Level Output Voltage
RST, IOL=500µA
0.3
V
Integrated Pull-Up Resistor on /SR0
Input Leakage Current /SR0
Input Leakage Current DSR
50
kΩ
VIN= VCC
1
1
IIN
µA
µA
0V VIN 5.0V
Quiescent Supply Current
(Timer Inactive)
/SR0=VCC
1
ICC
Dynamic Supply Current (Timer Active) /SR0=0V
200
AC Electrical Characteristics
Conditions of TA=-40°C to 80°C with VCC=1.8V - 5.0V OR TA=-25°C to 85°C with VCC=1.7V – 5.0V OR TA=0°C to
85°C with VCC=1.65V – 5.00V produce the performance characteristics below.
Symbol
Parameter
Condition
Min.
Typ. Max. Unit
tPHL1
Timer Delay, /SR0 to RST (DSR=0)
8
10
12
s
CL=5pF, RL=5K,
See Figure 4
tREC
Reset Timeout Delay
420
530
635
ms
Capacitance Specifications
TA=+25C.
Symbol
CIN
Parameter
Condition
Typ. Unit
Input Capacitance
Output Capacitance
VCC=GND
4
5
pF
pF
COUT
VCC=5.0V
© 2011 Fairchild Semiconductor Corporation
FT10001 • Rev 1.0.1
www.fairchildsemi.com
4
Functional Description
Default operation time N is 10s. If the DSR pin is pulled
HIGH prior to VCC ramp, the FT10001 enters Test Mode
and the reset output, /RST1, is immediately pulled LOW
for factory testing. The DSR pin MUST be forced to
GND during normal operation. The DSR pin should
never be driven HIGH or left to FLOAT during normal
operation. The DSR PIN state should never be changed
during device operation; it must be biased prior to
supplying the VCC supply. If there is a need to use the
DSR=VCC Test Mode, the /SR0 must be HIGH when
the DSR pin is moved from LOW to HIGH to enter Zero-
Second Factory-Test Mode. To return to the standard
10-second reset time, the same procedure must be
followed with DSR=GND. The DSR pin should never be
allowed to change state while the /SR0 pin is LOW.
state 530ms after time tREC has expired, regardless of
the state of /SR0. The /RST1 output is an open-drain
driver. When the count time exceeds time 10s, the
/RST1 output pulls LOW.
Short Duration (tW < 10s)
When the /SR0 input goes LOW, the internal timer starts
counting. If the /SR0 input goes HIGH before 10s has
elapsed, the timer stops counting and resets and no
changes occur on the outputs.
Long Duration (tW > 10s)
When the /SR0 input goes LOW, the internal timer starts
counting. If the /SR0 input stays LOW for at least 10s, the
RST output is enabled and pulled LOW. The output RST
is held LOW for tREC, 530ms, as soon as the reset time
of 10s is met, regardless of the state of the /SR0 pin.
When the /SR0 input has returned HIGH and tREC has
expired, the internal timer resets and awaits the next
RESET event.
Operation Modes
A low input signal on /SR0 starts the oscillator. There
are two scenarios for counting: short duration and long
duration. In the short-duration scenario, output /RST1 is
not affected. In the long-duration scenario, the output
/RST1 goes LOW after /SR0 has been held LOW for
10s. The /RST1 output returns to its original HIGH
Zero-Second Test Mode
/RST1 goes LOW immediately after /SR0 goes LOW.
N=7.5s
Short-Duration,
Normal Operation
/SR0
/RST1 never goes LOW because
/SR0 LOW duration does not meet
requirement: Reset Time N=10s
RST1
Long-Duration,
Normal Operation
/SR0
/RST1 goes LOW because
/SR0 LOW duration exceeds
requirement: Reset Time N=10s
RST1
tREC=530ms
/SR0
Zero-Second Factory-Test Mode
/RST1 goes LOW immediately
after /SR0 goes LOW
RST1
tREC=530ms
Figure 3.
Reset Timing Waveforms
© 2011 Fairchild Semiconductor Corporation
FT10001 • Rev 1.0.1
www.fairchildsemi.com
5
AC Test Circuit and Waveforms
Figure 4.
AC Test Circuit and Waveforms for /RST1 Output ST Output
© 2011 Fairchild Semiconductor Corporation
FT10001 • Rev 1.0.1
www.fairchildsemi.com
6
Physical Dimensions
2X
0.05 C
1.45
B
(1)
2X
0.05 C
(0.49)
5X
(0.254)
1.00
(0.75)
(0.52)
1X
A
TOP VIEW
PIN 1 IDENTIFIER
5
0.55MAX
(0.30)
6X
PIN 1
0.05 C
0.05
0.00
RECOMMENED
LAND PATTERN
0.05 C
C
0.45
0.35
0.10
6X
0.00
0.25
6X
0.15
1.0
DETAIL A
0.10
C B A
0.40
0.30
0.05
C
0.35
0.25
5X
5X
0.40
0.30
DETAIL A
PIN 1 TERMINAL
0.075 X 45
CHAMFER
0.5
BOTTOM VIEW
(0.05)
6X
(0.13)
4X
Notes:
1. CONFORMS TO JEDEC STANDARD M0-252 VARIATION UAAD
2. DIMENSIONS ARE IN MILLIMETERS
3. DRAWING CONFORMS TO ASME Y14.5M-1994
4. FILENAME AND REVISION: MAC06AREV4
5. PIN ONE IDENTIFIER IS 2X LENGTH OF ANY
OTHER LINE IN THE MARK CODE LAYOUT.
Figure 5.
6-Lead MicroPak™ 1.0 x 1.45mm, JEDEC MO-252
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2011 Fairchild Semiconductor Corporation
FT10001 • Rev 1.0.1
www.fairchildsemi.com
7
Physical Dimensions
0.35
0.05 C
1.00
B
A
2X
5X 0.40
1X 0.45
PIN 1
0.66
MIN 250uM
1.00
6X 0.19
0.05 C
TOP VIEW
RECOMMENDED LAND PATTERN
FOR SPACE CONSTRAINED PCB
2X
0.90
0.35
0.05 C
0.55MAX
C
5X 0.52
SIDE VIEW
0.73
0.57
1X
(0.08) 4X
DETAIL A
0.09
0.19
6X
1
2
3
0.20 6X
ALTERNATIVE LAND PATTERN
FOR UNIVERSAL APPLICATION
(0.05) 6X
0.35
5X
0.25
0.60
6
5
4
0.10
.05 C
C B A
0.40
0.30
0.35
(0.08)
4X
BOTTOM VIEW
NOTES:
A. COMPLIES TO JEDEC MO-252 STANDARD
B. DIMENSIONS ARE IN MILLIMETERS.
0.075X45°
CHAMFER
C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994
D. LANDPATTERN RECOMMENDATION IS BASED ON FSC
DESIGN.
DETAIL A
PIN 1 LEAD SCALE: 2X
E. DRAWING FILENAME AND REVISION: MGF06AREV3
Figure 6.
6-Lead MicroPak2™ 1.0 x 1.0mm, .35mm Pitch
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2011 Fairchild Semiconductor Corporation
FT10001 • Rev 1.0.1
www.fairchildsemi.com
8
© 2011 Fairchild Semiconductor Corporation
FT10001 • Rev 1.0.1
www.fairchildsemi.com
9
Revisions
Rev 0.0
Rev 0.1
8/1/11
Sean Ryan
Sean Ryan
Initial Rev – created from FT7521 datasheet
Updated the t to align with reset time of 10sec.
8/11/11
REC
Rev 0.2
Rev 0.3
Rev 0.4
Alvan Lam
Alvan Lam
Alvan Lam
Added micropak2 information and marketing drawing
8/24/11
8/25/11
9/6/11
Updated the NMOS symbol in block diagram
Created revision table instead of using Hidden Text
Changed ABS Max to 7V, initial datasheet released by
Techdoc
Rev 1.0.0
Rev 1.0.1
12/6/11
Alvan Lam
Alvan Lam
Added 1.7/-25C condition to align FT7521 datasheet
12/14/11
© 2011 Fairchild Semiconductor Corporation
FT10001 • Rev 1.0.1
www.fairchildsemi.com
10
© 2011 Fairchild Semiconductor Corporation
FT10001 • Rev 1.0.1
www.fairchildsemi.com
11
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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