FT7511L6X [ONSEMI]
重置计时器,带有固定延迟和重置脉冲;型号: | FT7511L6X |
厂家: | ONSEMI |
描述: | 重置计时器,带有固定延迟和重置脉冲 脉冲 |
文件: | 总10页 (文件大小:1387K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s
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is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
July 2012
FT7511
Reset Timer with Fixed Delay and Reset Pulse
Description
Features
The FT7511 is a timer for resetting a mobile device
where long reset times are needed. The long delay
helps avoid unintended resets caused by accidental key
presses. It has a fixed delay of 7.5 ±20% seconds. The
DSR pin enables Test Mode operation by immediately
forcing /RST1 LOW for factory testing.
.
.
.
.
.
.
.
.
Fixed Reset Delay: 7.5 Seconds
One Input Reset Pin
Open-Drain Output Pin with Fixed 80ms Pulse
1.8V to 5.0V Operation (TA=-40°C to +85°C)
1.7V to 5.0V Operation (TA=-25°C to +85°C)
1.65V to 5.0V Operation (TA=0°C to +85°C)
<1µA ICCQ Consumption
The FT7511 has one input for single-button resetting
capability. The device has a single open-drain output
with 0.5mA pull-down drive.
FT7511 draws minimal ICC current when inactive and
functions over a power supply range of 1.65V to 5.0V.
Zero-Second Test Mode Enable
Applications
.
.
.
.
.
Cell Phones
Portable Media Players
Tablets
Mobile Devices
Consumer Medical
Figure 1.
Block Diagram
Ordering Information
Operating
Temperature Range
Top
Mark
Part Number
Package
Packing Method
6-Lead, MicroPak™ 1.0 x 1.45mm,
JEDEC MO-252
5000 Units on
Tape and Reel
FT7511L6X
PD
-40C to +85C
© 2012 Fairchild Semiconductor Corporation
FT7511 • Rev. 1.0.0
www.fairchildsemi.com
Pin Configuration
Figure 2.
Pad Assignments (Top-Through View)
Pin Definitions
Description
Pin # Name
Normal Operation
0-Second Factory-Test Mode
Open-Drain Output, Active LOW
GND
1
2
3
4
/RST1 Open-Drain Output, Active LOW
GND GND
/SR0 Reset Input, Active LOW
Reset Input, Active LOW
Power Supply
VCC Power Supply
Delay Selection Input. Tie to GND(1) during
normal operation.
Delay Selection Input. Pull HIGH to enable the
0-second delay for factory test.
5
DSR
Used for device testing; should be tied to GND Used for device testing; should be tied to GND
during normal operation. during normal operation.
6
TEST
Note:
1. The DSR pin must always be tied to either GND or VCC; it must not float.
© 2012 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FT7511 • Rev. 1.0.0
2
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
VCC
VIN
Parameter
Condition
Min. Max. Unit
Supply Voltage
-0.5
-0.5
-0.5
7.0
7.0
7.0
-50
-50
+50
100
+150
+150
+260
5
V
V
DC Input Voltage
Output Voltage(2)
/SR0, DSR
/RST1
VOUT
IIK
V
DC Input Diode Current
DC Output Diode Current
DC Output Sink Current
VIN < 0V
VOUT < 0V
mA
mA
mA
mA
C
IOK
IOL
ICC
DC VCC or Ground Current per Supply Pin
Storage Temperature Range
TSTG
TJ
-65
Junction Temperature Under Bias
Junction Lead Temperature, Soldering 10 Seconds
Power Dissipation
C
TL
C
PD
mW
Human Body Model, JESD22-A114
Charged Device Model, JESD22-C101
4
ESD
Electrostatic Discharge Capability
kV
2
Note:
2. All output current Absolute Maximum Ratings must be observed.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Condition
Min. Max. Unit
1.8
1.7
5.0
5.0
-40C to +85C
VCC
Supply Voltage(3)
V
-25C to +85C
0C to +85C
1.65
5.00
V
0.5V
CC=0V After Power Down, Rising to
tRFC
VCC Recovery Time After Power Down
5
ms
VIN
VOUT
IOL
Input Voltage(3)
/SR0
0
0
5
V
V
Output Voltage
/RST1
5
DC Output Sink Current
Free-Air Operating Temperature
Thermal Resistance
/RST1, VCC=1.8V to 5.0V
+0.5
+85
350
mA
C
TA
-40
°C/W
JA
Note:
3. VCC should never be allowed to float while input pins are driven.
© 2012 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FT7511 • Rev. 1.0.0
3
DC Electrical Characteristics
Unless otherwise specified; conditions of TA=-40 to 80°C with VCC=1.8 - 5.0V, OR TA=-25 to 85°C with VCC=1.7 – 5V,
OR TA=0 to 85°C with VCC=1.65 – 5V produce the performance characteristics below.
Symbol
VIH
Parameter
Condition
Min.
Max.
Unit
V
Input High Voltage
DSR, /SR0
0.65 x VCC
VIL
Input Low Voltage
DSR, /SR0
0.25 x VCC
V
VOL
Low Level Output Voltage
Input Leakage Current (/SR0, DSR)
RST, IOL=500µA
0V VIN 5.0V
0.3
1.0
1
V
IIN
µA
µA
µA
Quiescent Supply Current (Timer Inactive) /SR0=VCC
Dynamic Supply Current (Timer Active) /SR0=0V
ICC
100
AC Electrical Characteristics
Unless otherwise specified; conditions of TA=-40 to 80°C with VCC=1.8 - 5.0V, OR TA=-25 to 85°C with VCC=1.7 – 5V,
OR TA=0 to 85°C with VCC=1.65 – 5V produce the performance characteristics below.
Symbol
tPHL1
Parameter
Timer Delay, /SR0 to RST (DSR=0)
Reset Timeout Delay
Condition
Min. Typ. Max. Unit
6.0
60
7.5
80
9.0
s
CL=5pF, RL=5K, See Figure 6
tREC
100
ms
Capacitance Specifications
TA=+25C.
Symbol
CIN
Parameter
Condition
VCC=GND
Typical
4.0
Unit
pF
Input Capacitance
Output Capacitance
COUT
VCC=5.0V
5.0
pF
© 2012 Fairchild Semiconductor Corporation
FT7511 • Rev. 1.0.0
www.fairchildsemi.com
4
Functional Description
Device default operation time N is 7.5s. If the DSR pin is
pulled HIGH prior to VCC ramp, the FT7511 enters Test
Mode and the reset output, /RST1, is immediately pulled
LOW for factory testing. The DSR pin MUST be forced
to GND during normal operation. The DSR pin should
never be driven HIGH or left to float during normal
operation. The DSR pin state should never be changed
during device operation; it must be biased prior to
supplying the VCC supply. If there is a need to use the
DSR=VCC Test Mode, the /SR0 must be HIGH when the
DSR pin is moved from LOW to HIGH to enter Zero-
Second Factory-Test Mode. To return to the standard
7.5-second reset time, the same procedure must be
followed with DSR=GND. The DSR pin should never be
allowed to change state while the /SR0 pin is LOW.
original HIGH state 80ms after time tREC has expired,
regardless of the state of /SR0. The /RST1 output is an
open-drain driver. When the count time exceeds 7.5
seconds, the /RST1 output pulls LOW.
Short Duration (tW < 7.5s)
When the /SR0 input goes LOW, the internal timer starts
counting. If the /SR0 input goes HIGH before 7.5s has
elapsed, the timer stops counting and resets; no
changes occur on the outputs.
Long Duration (tW > 7.5s)
When the /SR0 input goes LOW, the internal timer starts
counting. If the /SR0 input stays LOW for at least 7.5s, the
RST output is enabled and pulled LOW. The output RST
is held LOW for tREC, 80ms, as soon as the reset time of
7.5s is met, regardless of the state of the /SR0 pin.
When the /SR0 input has returned HIGH and tREC has
expired, the internal timer resets and awaits the next
RESET event.
Operation Modes
A low input signal on /SR0 starts the oscillator. There
are two scenarios for counting: short duration and long
duration. In the short-duration scenario, output /RST1 is
not affected. In the long-duration scenario, the output
/RST1 goes LOW after /SR0 has been held LOW for at
least 7.5 seconds. The /RST1 output returns to its
0-Second Test Mode
/RST1 goes LOW immediately after /SR0 goes LOW.
Figure 3.
Reset Timing Waveforms
© 2012 Fairchild Semiconductor Corporation
FT7511 • Rev. 1.0.0
www.fairchildsemi.com
5
Application Diagram
Figure 4.
Recommended Application Diagram
AC Test Circuit and Waveforms
Figure 5.
AC Test Circuit
Figure 6.
Waveforms for /RST1 Output
© 2012 Fairchild Semiconductor Corporation
FT7511 • Rev. 1.0.0
www.fairchildsemi.com
6
Physical Dimensions
2X
0.05 C
1.45
B
(1)
2X
0.05 C
(0.49)
5X
(0.254)
1.00
(0.75)
(0.52)
1X
A
TOP VIEW
PIN 1 IDENTIFIER
5
0.55MAX
(0.30)
6X
PIN 1
0.05 C
0.05
0.00
RECOMMENED
LAND PATTERN
0.05 C
C
0.45
0.35
0.10
6X
0.00
0.25
6X
0.15
1.0
DETAIL A
0.10
C B A
0.40
0.30
0.05
C
0.35
0.25
5X
5X
0.40
0.30
DETAIL A
PIN 1 TERMINAL
0.075 X 45
CHAMFER
0.5
BOTTOM VIEW
(0.05)
6X
(0.13)
4X
Notes:
1. CONFORMS TO JEDEC STANDARD M0-252 VARIATION UAAD
2. DIMENSIONS ARE IN MILLIMETERS
3. DRAWING CONFORMS TO ASME Y14.5M-1994
4. FILENAME AND REVISION: MAC06AREV4
5. PIN ONE IDENTIFIER IS 2X LENGTH OF ANY
OTHER LINE IN THE MARK CODE LAYOUT.
Figure 7.
6-Lead MicroPak™ 1.0 x 1.45mm, JEDEC MO-252
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2012 Fairchild Semiconductor Corporation
FT7511 • Rev. 1.0.0
www.fairchildsemi.com
7
© 2012 Fairchild Semiconductor Corporation
FT7511 • Rev. 1.0.0
www.fairchildsemi.com
8
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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