FUSB15101MNTWG_技术文档

DATA SHEET

www.onsemi.com

Programmable USBꢀType-C⁾

and Power Delivery 3.1

Source Controller with PPS

Support

1

QFN20 4x4, 0.5P

CASE 485BH−01

MARKING DIAGRAM

FUSB15101

6

The FUSB15101 is a highly integrated USB Power Delivery (PD)

power source controller that can control the opto−coupler in the

secondary side of an AC−DC adapter or a DC−DC port power

regulator.

11

FUSB

15101

ALYWG

G

The FUSB15101 enables a complete solution for USB power

sources through optimized hardware peripherals and complete

open−source embedded firmware all in a compact solution.

1

®

It integrates a highly efficient Arm Cortex −M0+ processor with

custom designed peripherals to seamlessly support USB PD 3.1 source

applications. The FUSB15101 supports the PPS specification in USB

PD, with a minimum of 3.3 V and a maximum of 21 V output voltage

control. It includes Constant Voltage (CV) and Constant Current Limit

(CL) control blocks, various protection mechanisms and high voltage

tolerance on connector pins.

16

FUSB = Specific Device Code

15101 = Specific Device Code

A

L

Y

W

G

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

Key Features

(Note: Microdot may be in either location)

• 32−bit Arm Cortex−M0+ Processor

• 32 KB OTP (One Time Programmable) Program Memory

• USB PD 3.1 with PPS Support

♦ Power Management Unit with VIN Support from 3.3 V to 24 V

♦ Integrated VCONN Supply for Interrogating E−Marked Cables

• Idle and Sleep Modes to Meet CoC and DoE Requirements

ORDERING INFORMATION

Device

Package

Shipping

FUSB15101MNTWG

QFN20

(Pb−Free)

4,000 / Tape &

Reel

• Peripherals

♦ USB Type−C / PD Detection and Communication Layer

♦ VBUS NMOS Gate Driver for Load Switch Control

♦ VBUS Discharge Functionality

♦ Programmable Constant Voltage & Constant Current Control

♦ Two 10−bit DAC’s for Precise Voltage and Current Control

♦ Two NTC Temperature Measurements

♦ 10−bit ADC for Voltage, Current and Temperature Reporting

♦ Two General Purpose 32−bit Timers

Typical Applications

• Wall Chargers for Mobile Phones and

Tablets and Computing Devices

• AC−DC USB PD Compliant Adapters

• Power Banks

♦ Watchdog Timer (WDT)

2

♦ I C Master/Slave Peripheral

• Cigarette Lighter Adapters

♦ UART on D+/− Pins

• Output Fault Protection

♦ Over−Voltage

♦ Under−Voltage

♦ Over−Current

♦ Over−Temperature

• 20−pin QFN Package (4 mm x 4 mm, 0.5 P)

1

Publication Order Number:

FUSB15101/D

June, 2022 − Rev. 0

FUSB15101

Introduction

• Current Sense Amplifier: Programmable for use

with 5 mꢀ or 10 mꢀ sense resistors.

The FUSB15101 supports USB Type−C 2.1 and USB PD

3.1 specifications for power source applications with VBUS

voltages ranging from 3.3 V to 21 V.

A highly flexible and open firmware environment allows

hardware peripherals to be customized to meet a variety

application needs.

• High Voltage Protection: 26 V DC tolerant BLD, CC and

D+/−.

• ADC: 10−bit ADC for accurate monitoring of VBUS

voltage and current, external temperatures or voltages.

2

• I C: Serial communication port capable of acting as

Key integrated functions and peripherals are highlighted

below:

a host or device.

• UART: UART peripheral available via HVDP/DM.

• GPIOs: Fully programmable I/Os with internal

terminations. Configurable as input or output (CMOS or

open−drain).

• Multiple Timers: Three independent 32−bit timers are

available: 1 General Purpose, 1 Watchdog, and

1 Wake−up / General Purpose.

• Dual External NTC: Integrated current sources are used

in conjunction with the ADC to monitor a variety of NTC

resistors.

• Arm Cortex−M0+: A 32−bit core with flexible clocking

up to 12 MHz.

• Memories: A total of 32 kB of One Time Programmable

Memory (OTP) is available to store program code; 2 KB

of SRAM program memory.

• USB Type−C and PD: Integrated USB PD PHY and

Type−C termination/comparators supporting latest

USB−IF specification. Open and customizable USB PD

firmware stack allows for tailored vendor specific

functions.

• Low Power Operation Modes: Programmable Sleep

Modes allowing the device to minimize power usage as

needed. Automatic USB−C detection and weak−up

functionality from sleep modes.

• Temperature Range: Extended operating temperature

range of −40°C to 105°C.

• Integrated VCONN Switch: Provides power to cable

eMarkers to interrogate current capabilities.

• CC/CV Control: Firmware controlled feedback voltage

and current loop operation with programmable voltage

and current DACs, Cable Drop Compensation, OVP,

UVP and OCP.

www.onsemi.com

2

FUSB15101

HVDP

HVDM

VDD

VIN LGATE BLD

vdd

GND

Resistor

Divider / BC 1.2

Gate Driver

vdd

UART

Rx

vdd

UART

Tx

V_IN−ON

V_IN−OFF

/

9R

R

Discharge

FAULT

UART PHY

HVCC1

HVCC2

V_CS−AMP

Trigger

_BLD

RESET

Protection

CVCC

_mode

vdd

CC State Machine &

Comparators

vdd

1.1 V REG

IREF

CSP

X A_VCCR

V_CS−AMP

Cable Drop

BMC

Rcvr

CSN

VCCR

vdd

BMC

Timers

UART

DRIVER

ARM

M0+

Compensation

USB PHY

VREF

Type−C

I2C

V_COMR

HS OSC

Band Gap

LF Osc.

SRAM

2KB

FAULT

Protection

Block

SWD

USB PD

CC−CV

VCVR

V_IN−1:10

OVP/UVP/

OCP

Mode_

change

OTP

32KB

BC1.2

V_UVP

V

vdd

_OVPV_COMR

Protection

V_CS−AMP

V_IN−1:10

I2C_SCL

I2C_SDA

I2C_INT

NTCA

NTCB

I2C

GPIO

SWD

BLD−1:10

Analog to Digital

Converter

vdd

D+

D−

1.8 V LDO

VCORE

SFB

Figure 1. Simplified Block Diagram

V_BUS

Q1

RBLD

CC1

CC2

D2

Input

filter

CBULK

CBUS

D+

D−

5m

R5

SZESD

7241

CVDD

CSN

C3

CSP

CVCORE

1

FAULT

FB

HV 10

6

5

4

1

2

3

DRV VCCL

GND VCCH

CS

2

3

NC

9

8

BLD

R1

CSP

15

14

13

12

11

1

2

3

4

5

CSP

C4

HVDP

CSN

ZCD

CS

VCCH

VCCL

DRV

CS

TRIG

ZCD

CS

CSN

D+

D−

FUSB15101

QFN

4mm x 4mm

0.5mm pitch

R2

R3

D1

HVDM

HVCC1

HVCC2

VREF

IREF

SFB

NCP4307

4

5

7

6

R6

C2

CC1

CC2

C1 R4

GND

NCP1345

CC

ZCD

4 x

SZESD

7241

Figure 2. AC/DC Application Schematic

www.onsemi.com

3

FUSB15101

CSP2

CSN2

CSN1

CSP1

NVTFS4C10N

VSW1_A

NVTFS4C10N

VSW2_A

NVTFS002N04CL

V_BUS

RBLD

SZESD

7241

CC1

CC2

HSG2

HSG1

NFET

C5

D+

D−

2 x

NSVR0240V2

LSG1

LSG2

VCC

NVTFS4C10N

VCC

EN

BST1

BST2

V1

HSG1

LSG1

HSG2

HSG1

CVDD

LSG1

HSG2

LSG2

VCCD

VDRV

CVCORE

VCC

LSG2

VCC

NCV81599

5m

PGND 1

PGND 2

CSP1

CSN1

CSP2

CSN2

FB

VSW1

VSW2

VSW1

VSW2

CSP1

CSN1

CSP2

CSN2

PDRV

BLD

CSP

CSN

INT

15

14

13

12

11

1

2

3

4

5

CSP

SDA

SCL

HVDP

CSN

CSP

CSN

R2

FUSB15101

QFN

4 mm x 4 mm

0.5 mm pitch

D+

CLIND

ADDR

CS1

CS2

HVDM

HVCC1

HVCC2

VREF

IREF

SFB

D−

R2

COMP

AGND GND

R3

R6

C2

CC1

CC2

C1 R4

CC

4 x

SZESD

7241

Figure 3. DC/DC Application Schematic

www.onsemi.com

4

FUSB15101

PIN CONNECTIONS

15

14

13

12

11

BLD

1

2

3

4

5

CSP

CSN

FUSB15101

QFN

4 mm x 4 mm

0.5mm pitch

HVDP

HVDM

HVCC1

HVCC2

VREF

IREF

SFB

GND

Top View

Figure 4. QFN20 Top−View

PIN FUNCTION DESCRIPTION

Pin #

Name

Description

1

CSP

Current Sensing Amplifier Positive Terminal. Connect this pin directly to the positive end of the current

sense resistor with a short PCB trace.

2

3

4

5

CSN

VREF

IREF

SFB

Current Sensing Amplifier Negative Terminal . Connect this pin directly to the negative end of the current

sense resistor with a short PCB trace.

Output Voltage Sensing Voltage. This pin is used for CV regulation, and it is tied to the internal CV loop

amplifier non−inverting input terminal. It is tied to the output voltage resistor divider.

Constant Current Amplifying Signal. The voltage level on this point is the amplified current sense signal.

This pin is tied to the internal CC loop amplifier’s non−inverting input terminal.

Secondary Feedback. Common output of the dual OTA open drain operational amplifiers. Typically,

an opto−coupler is connected to this pin to provide feedback to the primary side PWM controller.

2

6

7

I2C_INT/GPIO0

I2C_SDA/GPIO1

I2C_SCL/GPIO2

NTC_A/GPIO3/SWCK

NTC_B/GPIO4/SWD

HVCC2

I C Interrupt Signal / General Purpose I/O

2

I C Data Signal / General Purpose I/O

2

8

I C Clock Signal / General Purpose I/O

9

An external NTC can be connected to this pin / General purpose I/O/SWCK.

10

11

Configuration Channel 2. This pin is used to detect USB Type−C devices and communicate over USB

PD when applicable.

12

HVCC1

Configuration Channel 1. This pin is used to detect USB Type−C devices and communicate over USB

PD when applicable.

13

14

15

16

17

HVDM

HVDP

BLD

USB Communication Interface. This pin is tied to the USB D− data line input.

USB Communication Interface. This pin is tied to the USB D+ data line input.

Bleeder pin. This pin is tied to VBUS after the load switch to discharge VBUS.

Ground reference for IC

GND

VIN

Output voltage (Input voltage to the FUSB15101). This pin is tied to the output of the adapter to monitor

its output voltage and supply internal bias.

18

19

LGATE

VDD

Load switch gate drive signal. This pin is tied to the gate of the load switch.

Internal 5 V supply voltage.

20

VCORE

GND

Internal 1.8 V supply voltage for the MCU core.

Connect to GND Plane for thermal dissipation.

DAP

www.onsemi.com

5

FUSB15101

ELECTRICAL SPECIFICATIONS

MAXIMUM RATINGS (Notes 1, 2)

Symbol

Parameter

Min

−0.3

−0.5

−0.3

4

Typ

−

Max

26

Unit

V

USB

D+/− and CC Connector Pins

I/O Voltage

V

IO

−

6.0

2.0

31

V

NTC

NTC_A and NTC_B Pin Voltage

VREF Pin Input Voltage

−

V

VREF

−

V

IREF

IREF Pin Input Voltage

−

V

CSx

CSP and CSN Pins Input Voltages

VDD Pin Input Voltage

−

V

DC

−

V

CORE

VCORE Pin Input Voltage

−

V

LGATE

LGATE Pin Input Voltage

−

V

SFB

SFB Pin Input Voltage

−

26

V

IN

VIN Pin Input Voltage

−

26

V

BLD

BLD Pin Input Voltage

−

26

V

ESD

Human Body Model, ANSI/ESDA/JEDEC JS−001−2012 (Note 2)

Charged Device Model, JESD22−C101 (Note 2)

−

kV

HBM

CDM

2

−

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe

Operating parameters.

2. Meets JEDEC standards JS−001−2012 and JESD 22−C101.

OPERATING RATINGS

Symbol

Parameter

Functional Range for Supply Input

Min

Typ

5.0

−

Max

24

Unit

V

IN

3.135

V

HVCC

Communication Channel Pins

D+/− USB Voltage

GPIO, I2C, RESET

Junction Temperature

Operating Ambient Temperature

VCORE Pin Voltage

VDD Pin Voltage

0

5.5

V

−

3.6

V

HVDP/DM

V

IO

0

−

5.5

V

T

J

−40

0

−

+125

+105

1.9

°C

V

T

A

−

V

CORE

−

V

VDD

4.75

0

−

5.5

V

NTC_X

NTC_/B Pin Voltage

VREF Pin Voltage

IREF Pin Voltage

−

1.28

2.2

V

REF

0

−

V

I

0

−

1.8

V

REF

V

CSP Voltage

0

−

0.063

−

V

CSP

CSN Pin Voltage

−

0

V

CSN

V

SFB Pin Voltage

0

−

22.5

25

V

SFB

V

LGATE

LGATE Pin Voltage

BLD Pin Voltage

0

−

V

BLD

0

−

22.5

V

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

www.onsemi.com

6

FUSB15101

THERMAL CHARACTERISTICS (Note 3)

Symbol

Characteristic

Value

38.6

4.2

Unit

°C/W

ꢁ

JA

ꢁ

JC

Junction−to−Ambient Thermal Resistance

Junction−to−Case Thermal Resistance

3. Junction−to−ambient thermal resistance is a function of application and board layout. This data is measured with two−layer 2s2p boards in

accordance to JEDEC standard JESD51. Special attention must be paid not to exceed junction temperature T (max) at a given ambient

J

temperature T .

A

ELECTRICAL CHARACTERISTICS (Minimum and maximum values are at VIN = 3.135 V to 22.5 V, TA = −40°C to +105°C unless

otherwise noted. Typical values are at TA = 25°C, VIN = 5.0 V)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

INTERNAL POWER SUPPLY

VIN

I

Operating Supply Current

at 5 V

Attached, PD Communication

in progress, ADCs enabled,

−

3.5

−

mA

IN−OP−5V

NTCs enabled, CC & CV enabled,

Gate Driver Enabled. VIN = 5 V,

VCS = −25 mV, RCS = 5 m

ꢀ

I

Operating Supply Current at 20 V Attached, PD Communication

in progress, ADCs enabled,

−

4.4

−

mA

IN−OP−20V

NTCs enabled, CC & CV enabled,

Gate Driver Enabled. VIN = 20 V,

VCS = −25 mV, RCS = 5 m

ꢀ

I

Operating Supply Current

at Sleep Mode

No Device Attached, Type−C enabled

& Gate Driver OFF or BC1.2 Detection

enabled & Gate Driver ON; VIN = 5 V,

VCS = 0 V excluding IP−CC1 and

IP−CC2 Supply Current and ISFB

Current

0.75

IN−Sleep

V

IC Turn−On Threshold Voltage

IC Turn−Off Threshold Voltage

IC Turn−Off Debounce Time

Increase VIN

2.9

2.75

−

3.2

2.875

−

3.4

3.0

V

IN−ON

V

VIN > VIN−ON then decrease VIN

IN−OFF

VIN−off−Debounce

t

200

100

ꢂs

t

Hardware OCP Debouce on Both Entering and exiting OCP Mode

Edges

−

50

VIN−OCP−Debounce

V

Output Voltage Release

Latch Mode

VIN Falling

−

1.55

V

LATCH−OFF

VIN OVP Debounce Time

35

24

75

−

110

26

ꢂs

VIN−OVP−Debounce

V

VIN Maximum Overvoltage Pro-

tection

V

IN−OVP−MAX

V

Turn−Off Threshold Voltage when VIN Falling in a PPS contract

in a PPS Contract

2.805

2.97

3.135

V

IN−UVP−PPS

VIN UVP SECTION

K

Ratio VIN

Under−Voltage−Protection (UVP)

to VIN

VCS = 0 mV

57.5

60

65

70

80

90

95

62.5

70

%

IN−UVP−60

IN−UVP−65

IN−UVP−70

IN−UVP−80

IN−UVP−90

IN−UVP−95

67.5

77

72.5

83

87

93

92

98

www.onsemi.com

7

FUSB15101

ELECTRICAL CHARACTERISTICS (Minimum and maximum values are at VIN = 3.135 V to 22.5 V, TA = −40°C to +105°C unless

otherwise noted. Typical values are at TA = 25°C, VIN = 5.0 V) (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIN OVP SECTION

K

Ratio VIN

Over−Voltage−Protection (OVP)

to VIN

VCS = 0 mV

102

107

112

117

122

127

132

105

110

115

120

125

130

135

108

113

118

123

128

133

138

%

IN−OVP−105

K

IN−OVP−110

IN−OVP−115

IN−OVP−120

IN−OVP−125

IN−OVP−130

IN−OVP−135

K

VDD

V

VDD Source Voltage > 6 V

VIN = 6 V to 22.5 V, IVDD = 10 mA

VIN = 3.3 V, VDD = 2.9 V

4.75

10

5.125

−

5.5

−

V

DD

I

VDD Source Current

Capability

mA

DD

TYPE−C AND PD

USB PD PHY

TRANSMITTER

UI

Unit Interval

3.03

−

3.33

−

3.7

ꢂ

s

p

Maximum Difference between the

bit−rate During the Payload and

Last 32 Bits of Preamble

0.25

%

BitRate

t

Time to Cease Driving the Line

after the End of the Last Bit of

the Frame

−

1

−

23

−

ꢂs

EndDriveBMC

t

Time to Cease Driving the Line

after the Final High−to−low

Transition

HoldLowBMC

t

Any PD Transmission Cannot be

Sent out before a Dead Time of

at Least tInterFrameGap from

Receiving or Sending a Packet

25

−

InterFrameGap

t

Fall Time

10 % and 90 % amplitude points,

minimum is under an unloaded

condition.

300

−1

−

1

ns

ꢂs

Fall−CC

t

Rise Time

10 % and 90 % amplitude points,

minimum is under an unloaded

condition.

Rise−CC

t

Time before the Start of the First

Bit of the Preamble when the

Transmitter Shall Start Driving

the Line

StartDrive

V

Z

BMC Voltage Swing

1.05

33

1.125

−

1.2

75

V

Swing

TX Output Impedance at 750 kHz

with an External 220 pF or

Equivalent Load

ꢀ

Driver

RECEIVER

C

Receiver Capacitance when

Driver isn’t Turned On

Vrms = 0.371; Vdc = 0.5 V;

Freq. = 1 MHz

−

75

−

pF

Receiver

t

Rx Bandwidth Limiting Filter

100

12

−

ns

RxFilter

t

Time Window for Detecting

Non−idle

20

ꢂ

s

TransitionWindow

Z

(Note 5) Receiver Input Impedance

1

−

Mꢀ

BmcRx

www.onsemi.com

8

FUSB15101

ELECTRICAL CHARACTERISTICS (Minimum and maximum values are at VIN = 3.135 V to 22.5 V, TA = −40°C to +105°C unless

otherwise noted. Typical values are at TA = 25°C, VIN = 5.0 V) (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

TYPE−C FRONT END

R

BLD Pin Impedance to GND

when VBUS is not Sourced

BLD = 0 V to 5.75 V; LGATE = OFF

72.4

−

kꢀ

BLD−LEAK

I

SRC 180 ꢂA CC Current (1.5 A)

SRC 330 ꢂA CC Current (3 A)

Device Pull−down Resistance

Ra

166

304

4.6

180

330

5.1

−

194

356

5.6

ꢂA

180_CCX

I

330_CCX

R

kꢀ

DEVICE

R

A

800

126

1200

−

ꢀ

Z

OPEN

CC Resistance for Disabled

State, when VDD is Valid

−

kꢀ

I

Maximum Current for VCONN

Source

VIN = 4.75 V

34

−

mA

V

VCONN

V

Source Attach Threshold for CC

Pin at 3 A Current

2.45

0.75

2.6

0.8

2.75

0.85

RdSRC3.0

Source Ra Threshold for CC Pin

at 3 A Current

V

RaSRC3.0

V

CCx OVP Threshold

5.6

2.5

−

6.0

4.5

125

−

V

OVP_CC

VCONN−OCP

CC−OVP−Debounce

t

VCONN OCP Debounce Time

CC1/CC2 OVP Debounce Time

3.5

100

15

ms

ꢂs

t

Debounce Time after CC OVP

Event

−

ms

CC−OVP−

Debounce−Recover

I

Over Current Protection (OCP)

Limit at which VCONN Switch

Shuts Off

50

−

mA

V

VCONN_OCP

V

Voltage Range for VCONN

Source

3.0

5.5

VCONN

VBUS CONTROL

LOAD SWITCH

V

Gate High Voltage at 3.3 V

Gate High Voltage at 20 V

VIN = 3.3 V

8.1

23.5

−

V

LGATE−3.3V

V

VIN = 20 V

LGATE−20V

LGATE−OVP−Max

V

Gate High Voltage

at VIN−OVP−Max

VIN = VIN−OVP−Max

31.5

BLEEDER

I

VIN Sinking Current During tBLD Bleeding current on VIN at VIN = 20 V

BLD Sinking Current During tBLD Bleeding current on BLD at BLD = 20 V

60

−

mA

VIN−Sink

I

250

BLD−Sink

VBUS MEASUREMENT

V

Safe Operating Voltage at

“Zero Volts”.

0.6

−

0.8

V

Safe0V−THR

CLOCKS

f

Low Speed Clock for Idle,

Type−C and ADC

232.8

11.4

240

12

247.2

12.6

kHz

LS_CLK

2

f

Internal Clock for PD, I C

MHz

HS_CLK

and MCU Core

TEMPERATURE PROTECTION

Temperature Threshold for

T

SHUT

−

145

10

−

°C

Internal Circuit Protection

T

HYS

Over Temperature Hysteresis

www.onsemi.com

9

FUSB15101

ELECTRICAL CHARACTERISTICS (Minimum and maximum values are at VIN = 3.135 V to 22.5 V, TA = −40°C to +105°C unless

otherwise noted. Typical values are at TA = 25°C, VIN = 5.0 V) (continued)

Symbol

BC1.2

Parameter

Conditions

Min

Typ

Max

Unit

R

DCP Emulation Resistance

V

or V = 0 V, 1.0 V,

HVDM

−

75

140

ꢀ

DCP

HVDP

ION = 2 mA

or V = 0 V − 3.6 V

HVDM

R

DP/DM Pull Down Resistance

Sink Current to Dx

V

HVDP

16

25

19.5

100

700

23

kꢀ

Dx−DWN

I

VDD = 3.0 V to 5.5 V

or V = 0 V to 3.6 V

175

1100

ꢂA

DX−SNK

R

Resistor Weak Pull−Down on D+

and D−

V

HVDP

300

kꢀ

DAT−LKG

HVDM

V

Source Voltage

VDD = 3.0 V to 5.5 V

0.5

0.6

0.7

V

Dx−SRC

USB2.0 PORT CHARACTERISTICS

I

Power−Off Leakage Current

All data ports, V

3.6 V, VDD = 0 V

or V =

HVDM

−

18

−

ꢂA

pF

V

OFF−USB

HVDP

C

USB2

HVDP/HVDM Capacitance

f=240 MHz;

2.4

V

HVDP

or V

= 400 mV Vpk−pk

HVDM

V

HVDP/DM Rising over Voltage

Threshold

4.4

−

4.55

4.35

4.7

−

OVP−VIH−USB

V

HVDP/DM Falling over Voltage

Threshold

OVP−VIL−USB

t

USB OVP Event Recovery Time

HVDP/HVDM Over Voltage debounce

USB OVP event removed

−

100

15

125

−

ꢂ

s

OVP−USB

t

ms

OVP−USB−Recover

MOISTURE DETECTION (HVDM PIN)

V

Voltage Source for Moisture

Detection

.9

1.0

300

2.5

1.1

352

2.75

V

SRC−MOIS

R

High Pull up Resistor for Moisture

Detection

250

2.25

k

ꢀ

PU−MOIS

R

Low Pull Up Resistor for Moisture

Detection

k

PU−MOS−LO

SERIAL WIRE DEBUG INTERFACE

f

Serial Wire Debug Input Clock

Frequency

−

4

−

MHz

ns

SWD−CLK

t

Serial Wire Debug Data Setup

Timing

0.25 x (1/

SWD_CLK)

SWDI−SET

t

Serial Wire Debug Data Hold

Timing

0.25 x (1/

SWD_CLK)

ns

SWDI−HOLD

V

Serial Wire Debug Input Voltage

Threshold

VIN = 3.1 V to 22.5 V

0.7 x VDD

−

0.3 x VDD

−

V

SWD−VIH

V

−

SWD−VIL

V

Serial Wire Debug Input Voltage

Hysteresis

300

mV

ꢂA

V

SWD−HYS

I

Serial Wire Debug Input Leakage VIN = 3.1 V to 22.5 V

Input Voltage 0 V to 5.5 V

−10

VDD − 0.5

−

+10

−

SWD−LKG

V

Serial Wire Debug Output

Voltage High

VIN = 3.1 V to 22.5 V, Iout = −2 mA

SWD−VOH

V

Serial Wire Debug Output

Voltage Low

VIN = 3.1 V to 22.5 V, Iout = +4 mA

0.4

V

SWD−VOL

www.onsemi.com

10

FUSB15101

ELECTRICAL CHARACTERISTICS (Minimum and maximum values are at VIN = 3.135 V to 22.5 V, TA = −40°C to +105°C unless

otherwise noted. Typical values are at TA = 25°C, VIN = 5.0 V) (continued)

Symbol

I/OS

GPIO

Parameter

Conditions

Min

Typ

Max

Unit

V

High Level Input Voltage

Low Level Input Voltage

Output High Voltage

Ouptut Low Voltage

Input Hysteresis

VIN = 3.1 V to 22.5 V

0.7 x VDD

−

V

GPIO−VIH

V

VIN = 3.1 V to 22.5 V

−

0.3 x VDD

GPIO−IL

V

VIN = 3.1 V to 22.5 V, Iout = −2 mA

VIN = 3.1 V to 22.5 V, Iout = +4 mA

VIN = 3.1 V to 22.5 V, 5.0 V Typ

VDD − 0.5

−

0.4

−

V

GPIO−VOH

V

−

V

GPIO−VOL

GPIO−HYS

300

−

mV

ꢂA

I

Input Leakage

VIN = 3.1 V to 22.5 V,

−10

5

IN−GPIO

Input Voltage 0 V to 5.5 V

I

Off Input Leakage

Pull−Down Resistance

Pull−Up Resistance

Pin Capacitance

VIN = 0 V, Input Voltage 0 V to 5.5 V

PORT_PDx = 1

−5

−

5

−

ꢂA

OFF−GPIO

R

100

5

k

ꢀ

PD−GPIO

PU−GPIO

R

PORT_PUx = 1

−

k

C

GPIO

−

pF

NTC

I

Current Source on NTCA

Current Source on NTCB

55

60

65

ꢂA

NTCA

NTCB

2

I C

IO

I

VDD Current when SDA or SCL

is HIGH

VIN = 3.1 V to 22.5 V,

VSDA/VSCL = 1.8 V

−10

−

10

ꢂA

CCTI2C

I

Input Current of SDA and SCL

Pins

VIN = 3.1 V to 22.5 V,

VI = 0 V to 5.5V

I2C

V

High−Level Input Voltage

Low−Level Input Voltage

VIN = 3.1 V to 22.5 V

1.2

−

V

IH−I2C

V

0.4

0.3

IL−I2C

V

Low−Level Output Voltage at

−

OL1−I2C

3 mA Sink Current (Open−Drain)

V

Hysteresis of Schmitt Trigger

Inputs

VIN = 3.1 V to 22.5 V

−

0.2

−

V

hys−I2C

OL−SDA

I

Low−Level Output Current

(Open−Drain)

VIN = 3.1 V to 22.5 V,

V_OL = 0.4 V (Note 4)

20

mA

V

INT_N Output Low Voltage

Capacitance for Each I/O Pin

VIN = 3.1 V to 22.5 V, I_OL = 4 mA

VIN = 3.1 V to 22.5 V

−

5

−

0.4

−

V

pF

V

OL−INT

C

I2C

OL2−I2C

V

Low−Level Output Voltage at

VIN = 3.1 V to 22.5 V

0.3

2 mA Sink Current (Open−Drain)

t

Pulse Width of Spikes that Must

Be Suppressed by the Input Filter

−

50

ns

SP−I2C

V

High−Level Input Voltage

Low−Level Input Voltage

VIN = 3.1 V to 22.5 V

1.2

−

V

IH_INT

V

0.4

IL_INT

CV/CC CONTROL

CONSTANT CURRENT SENSE SECTION

A

Current Sense Amplifier Gain

RCS = 5 m

RCS = 10 m

Constant Current Limit mode

ꢀ

−

40

20

−

V/V

A

V−CCR−40

A

ꢀ

V−CCR−20

I

Current Threshold on Sensing

0.85

1.00

1.15

CS−1A

Resistor between CSP and CSN and VCC = 5 V, 20 V

at IOUT = 1.00 A

www.onsemi.com

11

FUSB15101

ELECTRICAL CHARACTERISTICS (Minimum and maximum values are at VIN = 3.135 V to 22.5 V, TA = −40°C to +105°C unless

otherwise noted. Typical values are at TA = 25°C, VIN = 5.0 V) (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

CONSTANT CURRENT SENSE SECTION

I

Current Threshold on Sensing

Resistor between CSP and CSN and VCC = 5 V, 20 V

at IOUT = 2.00 A

Constant Current Limit mode

1.85

2.00

2.15

A

CS−2A

CS−3A

CS−4A

CS−5A

Current Threshold on Sensing

Resistor between CSP and CSN and VCC = 5 V, 20 V

at IOUT = 3.00 A

Constant Current Limit mode

2.85

3.80

4.75

48

3.00

4.00

5.00

50

3.15

4.20

5.25

52

A

Current Threshold on Sensing

Resistor between CSP and CSN and VCC = 5 V, 20 V

at IOUT = 4.00 A

Constant Current Limit mode

Current Threshold on Sensing

Resistor between CSP and CSN and VCC = 5 V, 20 V

at IOUT = 5.00 A

Constant Current Limit mode

A

I

Current Threshold on Sensing

Constant Current Limit mode

mA

CS−STEP

Resistor between CSP and CSN and VCC = 5 V

at ꢃIOUT = 50 mA

I

t

Real Current Threshold to

Enable Bleeder

VBUS_BLD_EN = 1

200

−

450

0.6

700

1

mA

ms

CS−EN−BLD

Enable Bleeder Debounce Time

VBUS_BLD_EN = 1

CS−EN−BLD

OVER CURRENT PROTECTION SENSING SECTION

V

Voltage Difference between CSP Rcs = 5 mꢀ; ccdac_refp = 10b (120%);

and CSN at Nominal 3.6 A

csa_multiplier =1 (40x)

16.92

28.5

18

30

19.08

31.5

mV

CS−3.6A

V

Voltage Difference between CSP Rcs = 5 mꢀ; ccdac_refp = 10b (120%);

CS−6A

and CSN at Nominal 6.0 A

csa_multiplier =1 (40x)

CONSTANT VOLTAGE SENSE SECTION

V

CV Reference Voltage at 3.3 V

CV Reference Voltage at 5.0 V

CV Reference Voltage at 9.0 V

CV Reference Voltage at 12 V

CV Reference Voltage at 15 V

CV Reference Voltage at 20 V

VIN = 3.3 V, VCS = 0 V

VIN = 5.0 V, VCS = 0 V

VIN = 9.0 V, VCS = 0 V

VIN = 12 V, VCS = 0 V

VIN = 15 V, VCS = 0 V

VIN = 20 V, VCS = 0 V

delta VIN = 20 mV, VCS = 0 V

0.32

0.33

0.5

0.34

V

CVR−3.3V

CVR−5.0V

CVR−9.0V

0.485

0.873

1.164

1.455

1.940

0.515

0.927

1.236

1.545

2.060

0.9

V

1.200

1.500

2.000

V

CVR−12V

CVR−15V

CVR−20V

V

CV Reference Voltage of 20 mV

Step

mV

CVR−STEP−20mV

CABLE DROP COMPENSATION

V

Cable Compensation Voltage on

VCVR for VOUT = 0 mV/A

RCS = 5 mꢀ, VCS = −5 mV

−

0

−

mV

COMR−CDC−0

V

Cable Compensation Voltage on

VCVR for VOUT = 50 mV/A

5

COMR−CDC−50

V

Cable Compensation Voltage on

VCVR for VOUT = 100 mV/A

10

15

20

25

COMR−CDC−100

COMR−CDC−150

COMR−CDC−200

COMR−CDC−250

Cable Compensation Voltage on

VCVR for VOUT = 150 mV/A

Cable Compensation Voltage on

VCVR for VOUT = 200 mV/A

Cable Compensation Voltage on

VCVR for VOUT = 250 mV/A

FEEDBACK SECTION

I

SFB Maximum Sinking Current

During Regulation

Minimum guaranteed sink current

expected from SFB pin

2

−

mA

SFB−Sink−MAX

www.onsemi.com

12

FUSB15101

ELECTRICAL CHARACTERISTICS (Minimum and maximum values are at VIN = 3.135 V to 22.5 V, TA = −40°C to +105°C unless

otherwise noted. Typical values are at TA = 25°C, VIN = 5.0 V) (continued)

Symbol

UART

Parameter

Conditions

Min

Typ

Max

Unit

V

High−Level Input Voltage

Low−Level Input Voltage

Input Hysteresis

VIN = 3.5 V − 22.5 V

2

−

0.8

−

V

UART−VIH

V

VIN = 3.5 V − 22.5 V

UART−VIL

V

VIN = 3.5 V − 22.5 V

−

200

−

mV

V

UART−HYS

UART−VOL

UART−VOH

Output Low Voltage

VIN = 3.5 V − 22.5 V, Iout = 2 mA

VIN = 3.5 V − 22.5V, Iout = −2 mA

−

0.4

−

V

UART High Output Voltage

Rise Time of UART Tx

2.9

−

V

t

10%−90%, VIN = 3.5 V − 22.5 V,

Cl = 20 pF

250

−

ns

UART−tR

t

Fall Time of UART Tx

90% to 10%, VIN = 3.5 V − 22.5 V,

Cload = 20 pF

−

250

−

ns

UART−tFall

UART−BAUD

(Note 5)

UART BAUD Rate Range

Supported

Transmit and receive fall within 10% of

BAUD Rate set, including min and max

9600

230400

bps

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

4. Note (20 mA guaranteed over −40°C to 85°C)

5. Guaranteed by Design

Arm Cortex−M0+ Processor

• Software Issued Reset − The software reset can be called

The FUSB15101 integrates an Arm Cortex−M0+

by writing to a given register in the Cortex address space.

processor with Nested Vector Interrupt Controller (NVIC),

It is typically called on exit from a processor exception.

Wake−up Interrupt Controller (WIC), and Debug Access

Software reset resets the entire chip including core,

Port (DAP). The processor uses the Thumb instruction set

peripherals, wakeup timer, and watchdog.

and is optimized for high performance with reduced code

• Watchdog Timer Reset − The watchdog timer reset is

size and low power operation. The Arm Cortex−M0+

caused by the watchdog timeout and is used to prevent

efficiently handles multiple parallel peripherals and has

errant software from locking up the device. The watchdog

integrated sleep modes. Test and debug capability are

reset resets the entire chip including core, debug port,

enhanced with the Arm Serial Wire Debug Port.

peripherals, and watchdog. The watchdog timer is

The Arm implementation in the FUSB15101 includes a

disabled upon power up and must be enabled by software.

32 kB OTP and 2 kB of SRAM. The MCU, Memory and

The watchdog is not paused when the debugger halts the

DAP are interconnected using the AMBA (Advanced

processor.

Microcontroller Bus Architecture) AHB−Lite interface and

peripherals are connected to the AHB via APB interface

(Advanced Peripheral Bus).

In addition to the base Arm Cortex−M0+ processor

Power and Sleep Behavior

The FUSB15101 has been optimized to conserve power

by utilizing peripheral interrupts and hardware autonomy.

interrupts, the FUSB15101 implements multiple external

The device can be configured via firmware to enter low

source interrupts for peripheral devices. A powerful nested,

power states, disable unneeded peripherals and scale clock

pre−emptive and priority−based interrupt handling system

frequencies based on different application needs.

assures timely and flexible response to external events.

The Type−C block is designed to function at the lowest

Low power features on FUSB15101 include the WIC,

power states and will automatically wake when a Type−C

adjustable clock rates, and different software−controlled

attach is detected. This minimizes total power consumption

power modes to maximize opportunities to save power in the

when no device is attached.

final application.

Clock Sources

FUSB15101 implements a dual oscillator architecture to

The FUSB15101 has various sources of reset including:

minimize power consumption.

Reset Sources

• Internal Power−On Reset − The Internal Power−On Reset

asserts when VIN supply is below threshold levels for

proper operation. It resets the entire chip including core,

debug port, peripherals, wakeup timer, and watchdog.

• A 12 MHz internal RC oscillator to enable full

functionality.

• A 240 kHz internal RC oscillator that can be used for very

low power sleep modes

www.onsemi.com

13

FUSB15101

Timers

Serial Wire Debug Interface (SWD)

The Arm M0+ implementation includes a Debug Access

Port (DAP). The debug mode implementation includes 4

hardware breakpoints and 2 hardware watch points. The

Debug Access Port interface implementation is the Arm

Serial Wire Debug Port (SW−DAP) connected to Pins

SWCLK and SWDIO. The Serial Wire Debug Port Interface

uses a single bi−directional data connection. Each operation

consists of three phases: Packet request, Acknowledge

response, and Data transfer phase. Use any Serial Wire

Debug (SWD) compliant hardware debugger interface to

interact with the internals of the FUSB15101.

• 32−bit General Purpose Timer − FUSB15101 has a 32−bit

down−counter that can generate an interrupt request

signal, status, when the counter reaches 0. The timing

resolution depends on the programmable clock source

and pre−scale ratios/

• 32−bit Wake−up Timer (WUT) − The main purpose of the

wakeup timer is to facilitate scheduled exit from low

power modes. It can also be used for general purpose

event timing.

• 32−bit Watchdog Timer (WDT) − The watchdog timer

applies a reset to the system in the event of a software

failure, providing a way to recover from software crashes.

The watchdog timer is disabled by default and must be

enabled through software. The watchdog is protected

with a lock mechanism to prevent rogue software from

disabling the watchdog functionality. A special value has

to be written to the lock register to access watchdog

control. The watchdog timer is clocked from the same

oscillator as the core, which can be LS_CLK or HS_CLK.

USB Type−C & PD Peripheral Overview

The USB Type−C and PD peripheral is a fully compliant

USB solution. This peripheral consists of an analog front

end and a digital state machine. Firmware implements the

higher−level protocol and policy layers whereas the analog

and digital components can perform lower−level PD

protocol and PHY layer functions.

The Type−C block includes all terminations and

comparators required for Source/Sink/DRP operation: plug

orientation detection, power capability advertisement and

power role detection.

VCONN Switch

VDD

Type−C Terminations

HVCC1

HVCC2

VDD

CC State Machine &

Comparators

LV REG

USB PD PHY

Timers

ADC

BMC

Rcvr

ARM

M0+

BMC

DRIVER

CRC32Tx

BMC

4B5B

SRAM

2KB

Encode

Type−C

USB PD

CDR

BMC

4B5B

Decode

OTP

32KB

CRC32Rx

Figure 5. USB Type−C and PD

www.onsemi.com

14

FUSB15101

VCONN Switch

VBUS Discharge

Some applications require that a VCONN voltage be

sourced in order to provide additional source capabilities

when sourcing greater than 3 A on VBUS. The level of

over−current protection on VCONN is fixed at 50 mA.

VBUS is discharged through a resistor (RBLD) via the

BLD pin of the FUSB15101 as shown in the highlighted

section in Figure 6. The external resistor RBLD value is

dependent on the total bulk capacitance (CBULK) of the

power source so that VBUS is discharged within the time

limits dictated by USB PD. A typical value for RBLD is

30 ꢀ, 1 W and in addition, there is internal resistance that

limits the discharge current within the FUSB15101

USB PD PHY State Machine Logic

The FUSB15101 PD module includes the following

digital functions to enable USB PD messaging:

• Serialization and de−serialization

• Clock and data recovery (CDR)

• 4B5B coding

(I

in the electrical tables above).

BLD−SINK

When the load current to the Sink is sufficient (exceeds

for t debounce time) such that the

I

CS−EN−BLD

internal discharge is not needed, then the FUSB15101 will

automatically disable internal discharge.

• BMC coding

• Packet CRC generation and checking

• Coding and detection of Power Delivery K−Codes

• Automatic GoodCRC packet response

Upon power up, firmware in the FUSB15101 may

discharge VBUS in case there is a voltage on VBUS since

the only way a Sink can be attached per Type C specification

is if VBUS is discharged to ground (below VSafe0V) upon

attach.

BC1.2 Support

The FUSB15101 has the circuitry to enable emulation

BC1.2, QC2.0 and 2.4A Divider Mode via firmware.

The discharge resistance limits are governed by the

Type C specification when not sourcing power on VBUS

(R

in the electrical tables above). It is preferred

BLD−LEAK

VBUS Operation

that no external load/discharge resistor is connected to

VBUS other than RBLD to the FUSB15101 discharge BLD

pin. A TVS diode connected from VBUS to ground

([SZ]ESD7241) allow operating voltages up to 24 V

covering the entire VBUS range of 3.3 V to 21 V for a USB

PD PPS contract. This can be replaced by a TVS that covers

the VBUS range for the use case of this design if needed.

Gate Driver

VBUS from the USB−C connector is typically connected

to a load switch NFET (Q1 in Figure 6) source terminal

whose gate terminal is driven by the FUSB15101 gate driver

via the LGATE pin. onsemi recommends NFETs with low

I

leakages (<1 ꢂ A) for optimal gate drive.

GSS

Voltage and Current Sensing Operation

The resistor ratio from VIN to ground formed by resistors

R2 and R3 in Figure 7 (typically 1:10 ratio) is sensed via

FUSB15101 VREF pin to set the output voltage.

For the offline design in Figure 2, this will be done via the

FUSB15101 SFB pin, the opto−coupler, resistor R1 and the

primary side PWM controller operation.

For DC−DC design in Figure 3, this will be done via the

FUSB15101 SFB pin controlling the buck−boost PWM via

its COMP pin.

The FUSB15101 will automatically control the SFB pin

based on the desired voltage as determine by the USB PD

contract and the existing VIN voltage sensed by VREF.

The external compensation network formed by C2/R2 and

R4/C1 need to be selected to achieve stable operation over

the range of VBUS voltage and current transitions as shown

in Figure 7.

Figure 6. VBUS Discharge via BLD Pin

www.onsemi.com

15

FUSB15101

Figure 7. Compensation Network for AC/DC Constant Voltage / Constant Current (CC/CV) Feedback

For the DC−DC design in Figure 3, there may be a need

for additional compensation networks from COMP pin to

ground or from COMP to the DC−DC’s supply.

current sensing if the FUSB15101 ground connection is on

the USC−C connector ground if it is more convenient in the

Printed Circuit Board (PCB) layout.

The current is sensed via a small resistor (5 mꢀ typically)

connected between the USB−C connector ground and the

main ground plane of the power source (secondary side

ground for offline design) as shown in Figure 7. The gain of

the current sense amplifier can be adjusted to work with

10 mꢀ resistors if desired.

A low pass filter formed by R5/C3 provides a stable signal

for CSP and CSN pins of the FUSB15101 to sense this

current for over−current protection for fixed voltage PD

contracts, constant current operation for PPS contracts and

cable compensation (Table 1).

When in a PPS contract, if a PPS_Status message is

requested, the firmware in the FUSB15101 will measure the

current with an internal 10−bit Analog to Digital Converter

(ADC) based on the above description and report it back to

the Sink on the PPS_Status message. The voltage is also

reported back but it is measured off VIN with the ADC not

VREF pin since the VREF pin is only used for voltage

feedback. Thus, if the voltage feedback resistor divider

connected to VREF is modified to be slightly different from

the 1:10 ratio expected, the voltage sensing for this

PPS_Status message will not be affected. BLD pin voltage

can also be monitored by the ADC and it will be accurate as

long as the discharge function is not enabled.

Table 1. CABLE DROP COMPENSATION

Symbol

Cable Drop Compensation

0 mV/A

Protection Operation

FUSB15101 has several ways it protects itself as shown

in Table 2.

V

COMR−CDC−0

50 mV/A

OVP and UVP are sensed via an internal resistor divider

that divides VIN by 10 to determine the voltage from the

power source. HVCC1, HVCC2, HVDP and HVDM are

directly sensed for over voltage. For external temperature

monitoring (E_OTP), two NTC pins are available that are

connected to NTC resistors to ground usually in parallel

with another resistor to ground for linearity. An internal

temperature monitor (I_OTP) is also used for protecting the

devince under extreme die temperatures. For all faults

capable of automatic hardware protection (when enabled),

the FUSB15101 will disable the Type C connection with the

Sink (no pull−up on CC), shut off VBUS load switch and

discharge VIN to vSafe5V.

V

100 mV/A

COMR−CDC−100

COMR−CDC15−0

COMR−CDC−200

COMR−CDC−250

150 mV/A

200 mV/A

250 mV/A

It is expected that the USB−C connector ground is

connected only to the current sense network resistors and the

connector TVS ground connections and not to the main

ground plane of the DC/DC design or secondary side power

ground for the offline design (FUSB15101 ground

connection). However, the FUSB15101 consumes very little

current and so it should have a negligible impact on this

www.onsemi.com

16

FUSB15101

Table 2. PROTECTION FEATURES

Symbol

Automatic Hardware

Protection Capable?

Description

Pin(s) Used

VIN

OVP

UVP

Output Over Voltage Protection

Output Under Voltage Protection

Over Current Protection

Yes

VIN

Firmware Controlled

OCP

CSP & CSN

N/A

Yes

I_OTP

Internal Temperature Protection

External Temperature Protection

HVCC1 or HVCC2 Over Voltage Protection

HVDP or HVDM Over Voltage Protection

VCONN Over Current Protection

VBUS or HVDM Pollution Detection

Yes

E_OTP

NTCA / NTCB

HVCC1 / HVCC2

HVDP / HVDM

CC1 / CC2

BLD / HVDM

Firmware Controlled

CC_OVP

USB_OVP

VCONN_OCP

Cable Fault

Yes

Firmware Controlled

Output Over−Voltage Protection (OVP)

FUSB15101 has built−in OVP based on firmware

programmable values. Whenever VIN, as sensed by an

For compliance with the USB PD specification, the

FUSB15101 will trigger UVP whenever VIN is below

VIN−OFF. This allows protection for a direct short of VBUS

to ground separately or in conjunction with the OCP fault

described below. If VIN < VIN−OFF fault is triggered, then

to resume normal operation, VIN has to go below

VLATCH−OFF to reset the FUSB15101 to exit this fault

condition.

internal 1:10 resistor divider, exceeds by K

(Table 3)

IN−OVP

of the requested VIN from the power source for a debounce

time of t , then the OVP fault would be

VIN−OVP−Debounce

triggered. If hardware auto−protection is enabled, the

FUSB15101 will disable the Type C connection with the

Sink (no pull−up on CC), shut off VBUS load switch and

discharge VIN to vSafe5V.

Table 4. PROGRAMMABLE UVP SETTINGS

During transitions between VIN voltages, the OVP

circuitry can be blanked or disabled via firmware to ensure

that false triggering of OVP doesn’t occur. To ensure safe

operation over all voltages of VIN, the maximum VIN

voltage is limited to VIN−OVP−MAX.

Symbol

VIN / VIN Requested

K

105%

60%

65%

70%

80%

90%

95%

IN−OVP−105

K

IN−UVP−60

IN−UVP−65

IN−UVP−70

IN−UVP−80

IN−UVP−90

IN−UVP−95

K

Table 3. PROGRAMMABLE OVP SETTINGS

Symbol

VIN / VIN Requested

K

105%

110%

115%

120%

125%

130%

135%

IN−OVP−105

K

IN−OVP−110

IN−OVP−115

IN−OVP−120

IN−OVP−125

IN−OVP−130

IN−OVP−135

Over−Current Protection (OCP) and Constant Current

Limit (CL)

K

If VBUS is shorted to ground, either the UVP fault

described above could trigger or the OCP fault, or both.

FUSB15101 senses the current via a small sense resistor

(5 mꢀ typical) as described in the Voltage and Current

Sensing section above. The OCP fault is triggered at

firmware programmed ratio of the maximum current for the

requested Power Data Object (PDO). Once this OCP fault

occurs, the FUSB15101 protects the system as described in

the Protection Operation section above. For PPS APDO’s

(Augmented Power Data Objects), Constant Current

Limiting (CL) is used as specified in the USB PD

specification where the voltage will drop to a low value

based on keeping the current constant and equal to the

requested PPS current. In this case UVP described above

will trigger if VIN drops below VIN−OFF since any voltage

from the lowest 3.3 V − 5% to the PPS requested voltage

could occur with current limiting. If the PPS current limit is

Output Under−Voltage Protection (UVP)

FUSB15101 has a built−in firmware programmable UVP.

Whenever VIN, as sensed internally, is below K

IN−UVP

(Table 4) of the requested output voltage from the power

source, then the UVP fault would be triggered. During

transitions between VIN voltages, the UVP circuitry can be

blanked or disabled via firmware to ensure that false

triggering of UVP doesn’t occur. For PPS contracts, if

current limiting causes the voltage to decrease, the UVP

fault will not trigger at a percentage of VIN since all voltages

from the requested voltage to VIN−OFF, the lowest voltage,

are valid.

www.onsemi.com

17

FUSB15101

Cable Fault

changed with a new PD Request message, the VIN voltage

may change accordingly to a new value based on the current

limiting function.

The FUSB15101 allows for foreign substance monitoring

of the Type−C receptacle via the HVDM pin.

Pollution detection on HVDM is done by applying a small

voltage and resistance to the DM pin and measuring

its voltage potential via the on−board ADC.

Over−Temperature Protection (Internal and External)

FUSB15101 has two different over temperature faults,

External and Internal. For External OTP, there are two NTC

pins that may be connected to NTC resistors in parallel with

a regular resistor for linearity. The FUSB15101 provides

separate INTC current sources (typically 60 ꢂ A) on the NTC

pins to bias these NTC resistors so that an internal A/D

converter measures the external temperature as shown in

Figure 8. The firmware can be customized to trigger a fault

on the desired application specific temperature limits. If the

second NTC pin is not used for measuring temperature, it

can be used as a general−purpose ADC channel.

−

+

!EN_RPMOS_HI

EN_RPMOS_HI

VSRC_MOS

RPU_MOS_LO

RPU_MOS_HI

To ADC CH.4

DM

BC12_SW

Figure 9. HVDM Pollution Detection

There are two pull up resistors that are selectable:

−

INTCA

+

1. EN_RPMOS_HI = 1 (RPU_MOS_HI = 300 kꢀ)

Moisture or pollutants on the Type−C connector

have been characterized as resistance to ground

smaller than ~300 kꢀ when nothing is attached.

2. EN_RPMOS_HI = 0 (RPU_MOS_LO = 2.5 kꢀ)

Certain applications prefer to detect pollution

resistance in the 200 ꢀ to ~400 ꢀ range. For that a

second pull−up resistor is included.

ADC_CH5

NTC_A/GPIO/SWCK

MUX

GPIO

R_PAR

R_NTC

PORT_CONFIG

−

INTCB

+

ADC_CH6

NTC_B/GPIO4/SWD

I²C

MUX

GPIO

R_PAR

R_NTC

The FUSB15101’s serial interface is compatible with

2

Standard, Fast, and Fast Mode Plus I C bus specifications.

PORT_CONFIG

2

The I C peripheral can be configured for either host or

device modes. The analog circuitry is firmware configurable

for the function required by the application and follows the

final BC1.2 specification.

Figure 8. External Temperature Monitoring

This NTC measured temperature is useful for dynamic

monitoring by the Sink via FUSB15101 provided PD Status

messages.

Internal OTP monitors the internal die temperature. When

the die temperature exceeds Tshut threshold for

tOTP−Debounce time, an interrupt is set to alert the core and

take action.

Bus Timing

6

As shown in Figure 10 below , for data bits, SDA must be

stable while SCL is HIGH. SDA may only transition when

SCL is LOW. Data is clocked in on the rising edge of SCL.

Typically, data transitions shortly at or after the falling edge

of SCL to allow ample time for the data to set up before the

next SCL rising edge.

2

6. Bus timing referenced from I C−bus specification Rev. 6−4 April 2014

www.onsemi.com

18

FUSB15101

Figure 10. I²C Bus Timing Definition

2

Each bus transaction begins and ends with SDA and SCL

HIGH. A transaction begins with a START condition, which

is defined as SDA transitioning from 1 to 0 with SCL HIGH.

A transaction ends with a STOP condition, which is defined

as SDA transitioning from 0 to 1 with SCL HIGH. During

a read from the FUSB15101, the host issues a Repeated Start

after sending a data command and before resending the

device address. The Repeated Start is a 1−to−0 transition on

SDA while SCL is HIGH.

a dedicated peripheral such as I C. A subset of these Pins

can also be connected as an input to the ADC. Internal

pull−up/down resistors are programmable. Pull−up resistors

are always connected to VDD.

When the PORT is configured as GPIOs it will have the

following capabilities:

• Bi−directional capability

• Push pull or open drain configuration

• Individually configurable interrupt lines

• Rising or Falling edge interrupt

• High− or Low−level interrupt

UART

The FUSB15101 implements a UART transceiver that

communicates via D+/− when enabled.

When this peripheral is disabled, it should not interfere

with D+/− charging protocols such as BC1.2− where the

ADC is sensitive to loads.

Table 5. PIN−PORT CONFIGURATION

Pin #

Name

GPIO0

Port

6

PA0

Clock Requirements and BAUD Rates

I2C_INT

GPIO1

The max BAUD rate support is dependent on the

CLK_HS speed setting. BAUD rates are supported from

9,600 to 230,400.

7

8

9

PA1

PA2

PA3

I2C_SDA

GPIO2

Automatic BAUD Rate Detection

The FUSB15101 implements automatic BAUD Rate

detection based on the first character received in a message.

The supported characters for automatic BAUD rate

detection are 0xAA or 0x55.

Automatic BAUD detection rate works up to 230,400 bps.

BAUD Rates detected outside of this range will be flagged

as errors to the core.

I2C_SCL

GPIO3

ADC_CH5

SWCK

10

GPIO4

PA4

ADC_CH6

SWD

Port Control and GPIOs

The FUSB15101 includes a number of pins that can be

configured to be used as standard GPIO or for use with

www.onsemi.com

19

FUSB15101

ADC

Output Current, two NTC temperature channels and two

The FUSB15101 allows for up to 7 signals to be measured

and converted using the internal 10−bit ADC. For most

applications, this will consist of VBUS and VIN voltages,

D+/D− BC1.2 ports. Table 6 below shows the typical

FUSB15101 configuration along with the expected settings

for the ADC module.

Table 6. ADC CONFIGURATION

ADC Channel

Pin Measurement

Resolution

10 mV

20 mV

40 mV

10 mV

20 mV

40 mV

10 mA

4 mV

Range

Full Scale Voltage

1.024 V

2.048 V

4.096 V

1.024 V

2.048 V

4.096 V

2.048 V

4.096 V

1.28 V

0

VIN

0 V to 10.23 V

0 V to 20.46 V

0 V to 40.92 V

0 V to 10.23 V

0 V to 20.46 V

0 V to 40.92 V

0 A to 10.23 A

0 V to 4.096 V

0°C to 160°C

1

BLD

2

3

4

5

6

Output Current

HVDP

HVDM

4 mV

NTCA Temperature

NTCB Temperature

1°C

1.28 V

Development Tools

Specifications References

FUSB15101 is supported by a full suite of comprehensive

tools including:

• Universal Serial Bus Power Delivery specification

revision 3.1 Version 1.0, dated May 2021

• An easy−to−use development board

• Software Development Kit (SDK) including: USB PD

protocol stacks, sample code, libraries, and

documentation

• Universal Serial Bus Type C Cable and Connection

Specification release 2.1, dated May, 2021

• USB Battery Charging Specification, revision 1.2, dated

December 7, 2010

2

• I C−bus specification Rev. 6 − 4 April 2014

USB, USB−C, USB Type−C and the USB logos are registered trademarks of USB Implementers Forum, Inc.

Arm, Cortex, and the Arm logo are registered trademarks of Arm Limited (or its subsidiaries) in the EU and/or elsewhere.

2

onsemi is licensed by the Philips Corporation to carry the I C bus protocol.

www.onsemi.com

20

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

QFN20 4x4, 0.5P

CASE 485BH−01

ISSUE O

1

DATE 19 FEB 2010

SCALE 2:1

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED TERMINAL

AND IS MEASURED BETWEEN 0.15 AND 0.30 MM

FROM TERMINAL TIP.

B

E

A

D

L

PIN ONE

REFERENCE

L1

4. COPLANARITY APPLIES TO THE EXPOSED PAD

AS WELL AS THE TERMINALS.

DETAIL A

MILLIMETERS

ALTERNATE TERMINAL

CONSTRUCTIONS

DIM MIN

MAX

1.00

0.05

A

A1

A3

b

0.80

−−−

0.20 REF

0.20

EXPOSED Cu

MOLD CMPD

0.30

D

D2

E

E2

e

K

4.00 BSC

0.15

C

2.60

2.80

4.00 BSC

C

2.60

2.80

TOP VIEW

DETAIL B

0.50 BSC

ALTERNATE

0.20

0.35

0.00

−−−

0.45

0.15

A

CONSTRUCTION

L

L1

0.10

C

A3

GENERIC

MARKING DIAGRAM*

0.08

DETAIL B

NOTE 4

A1

K

SEATING

PLANE

XXXXX

ALYWG

G

C

SIDE VIEW

DETAIL A

D2

6

XXXXX = Specific Device Code

A

L

Y

W

G

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

^20XL

11

E2

(Note: Microdot may be in either location)

1

*This information is generic. Please refer

to device data sheet for actual part

marking. Pb−Free indicator, “G”, may

or not be present.

16

20X

b

0.10

e

C

A

B

MOUNTING FOOTPRINT

0.05

NOTE 3

BOTTOM VIEW

4.30

2.80

20X

0.60

1

2.80

4.30

PACKAGE

OUTLINE

20X

0.35

0.50

PITCH

DIMENSIONS: MILLIMETERS

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98AON48317E

QFN20 4X4, 0.5P

PAGE 1 OF 1

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the

rights of others.

www.onsemi.com

onsemi,

, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates

and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.

A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any

products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the

information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use

of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products

and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information

provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may

vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license

under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems

or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should

Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

ADDITIONAL INFORMATION

TECHNICAL PUBLICATIONS:

Technical Library: www.onsemi.com/design/resources/technical−documentation

onsemi Website: www.onsemi.com

ONLINE SUPPORT: www.onsemi.com/support

For additional information, please contact your local Sales Representative at

www.onsemi.com/support/sales




型号：	FUSB15101MNTWG
厂家：	ONSEMI
描述：	Programmable USB Type-C and Power Delivery 3.1 Source Controller with PPS Support
文件：	总22页 (文件大小：411K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

FUSB15101MNTWG [ONSEMI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E