FUSB15200MNTWG_技术文档

DATA SHEET

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Dual Port USB Type-C & PD

Controller for Sink and DRP

Applications

1

40

QFN40 5x5, 0.4P

CASE 485CR

FUSB15200

The FUSB15200 is a highly integrated dual port USB Type−C and

Power Delivery Controller optimized for Sink and DRP applications.

The FUSB15200 enables a complete solution through optimized

hardware peripherals and complete open−source embedded firmware

all in a compact solution. Maximizing total system power budgets is

enabled through both hardware and firmware of the FUSB15200.

onsemi offers a complete open−source embedded firmware

solution. System designers can easily tailor this firmware to meet the

specific needs of their end application through an easy to use API for

the embedded firmware. The FUSB15200 also provides a completely

USB PD3.1 compliant solution with interoperability with leading

mobile and computing devices in the market.

MARKING DIAGRAM

1

FUSB

15200

AWLYYWW

FUSB15200 = Specific Device Code

A

= Assembly Location

= Wafer Lot

= Year

WL

YY

WW

= Work Week

Features

• Small Footprint Dual−port USB PD Controller Supporting the Most

Popular Peripherals

ORDERING INFORMATION

†

Device

FUSB15200MNTWG

Package

Shipping

♦ USB PD 3.1 & USB Type−C 2.1

2

QFN40

5000 / Tape &

Reel

♦ 4x I C Host/Device

♦ Dual USB BC1.2 Consumer/Provider

♦ USB2.0 Isolation Switches

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specifications

Brochure, BRD8011/D.

• Fully Programmable and Upgradable Open−Source Firmware

Providing API for Customer Specific Device Policy Manager

Development

• Integrated LDOs from VBUS Allows Dead−Battery Functionality

• High Voltage Protection on CC and VBUS Pins (28 V DC)

• Up to 20 GPIOs

• 10−bit ADC for High Performance System Measurements

• External Temperature Monitoring via NTC Resistors

®

• DisplayPort HPD Signal Conversion

• FastRole Swap Support

• 40−pin QFN Package (5 mm x 5 mm, 0.4 mm Pitch)

• These are Pb−free Devices

Typical Applications

• Sinks and DRP Devices

• Laptops

• Docks

1

Publication Order Number:

March, 2022 − Rev. 0

FUSB15200/D

FUSB15200

FEATURES

[

• Arm Cortex −M0+: A 32−bit core with flexible

clocking up to 24 MHz.

• Programmable VBUS discharge: Internal programmable

resistors capable of discharging up to 100 mF.

• Memories: A total of 132 KB of flash is available to store

program code. 6 KB of SRAM program memory.

• Multiple Timers: Four independent 32−bit timers are

available: 2 General Purpose, 1 Watchdog, and

1 Wake−up/General Purpose

• External NTC: Integrated current sources are used in

conjunction with the ADC to monitor a variety of NTC

resistors.

• Low Power Operation Modes: Programmable sleep

modes allowing device to minimize power usage as

needed. Automatic USB−C detection and wake−up

functionality from sleep modes.

• USB Type−C and PD: Integrated hardware USB PD PHY

and Type−C termination/comparators supporting latest

USB−IF specification.

• Integrated VCONN Switch: Provides the full 1.5 W power

to interrogate cable eMarkers and power active cables.

• BC1.2 Support: Fully programmable and capable of

presenting and detecting SDP, CDP or DCP.

• High Voltage Protection: Robust USB−C connector

interface with 28 V DC tolerant VBUS, and CC pins.

• ADC: Multi−channel 10−bit ADC for accurate

monitoring of VBUS, external temperature and voltages.

• DisplayPort Support: Configurable I/Os to support

hot−plug detect in either display sinks or display source

modes.

• Integrated LDO: Device can be powered from VBUS

input of either port allowing complete USB PD

capabilities and contract negotiation under dead battery

or no battery conditions.

2

• I C: Four serial communication ports capable of acting as

a host or device allowing control of external system

peripherals by FUSB15200.

• GPIOs: Fully programmable I/Os with internal

terminations. Configurable as input or output (CMOS or

open−drain).

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2

FUSB15200

FUSB15200 INTERNAL BLOCK DIAGRAM

FUSB15200 – Dual Port USB PD Controller

ꢀ

ARM Cortex −M0+

(24 MHz)

Interrupts

3x Timers

WDT

Flash

(132 KB)

SRAM

(6 KB)

Serial Wire Debug

AHB

Peripheral Bus

Type−C Port A

Up to 20 GPIOs

USB PD PHY

VCONN FET w/ OCP

Load Switch Control

VBUS LDO

4x I²C Master/Slave

Power Management

Internal Regulators

Reset

VBUS Discharge

Type−C Port B

USB PD PHY

VCONN FET w/ OCP

Load Switch Control

DisplayPort HPD

USB Switches

VBUS LDO

VBUS Discharge

Figure 1. FUSB15200 Block Diagram

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3

FUSB15200

PIN DIAGRAM

1

2

30

29

28

27

26

25

24

23

22

21

VBUS_A

HVCC2_A

VBUS_B

HVCC2_B

3

VCONN_B

VCONN_A

HVCC1_B

HVCC1_A

4

HPD_B/GPIO12

I2C_SDA1/GPIO11

I2C_SCL1/GPIO10

I2C_INT1/GPIO9

DP_B

VDD

5

GND

I2C_INT2/GPIO2/SWD

I2C_SDA2/GPIO3

I2C_SCL2/GPIO4

DP_A

6

7

8

9

DM_B

DM_A

10

Figure 2. Pin Diagram

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4

FUSB15200

PIN DESCRIPTION

Pin #

Name

VBUS_A

HVCC2_A

VCONN_A

HVCC1_A

VDD

Port

Power

Analog

Power

Analog

Power

PA2

Description

1

2

3

4

5

Port A VBUS. Monitoring Discharge (28 V)

Port A High Voltage Configuration Channel 2 (28 V)

Port−A VCONN Supply

Port A High Voltage Configuration Channel 1 (28 V)

Power Supply

2

6

7

I2C_INT2/GPIO2/SWD

I2C_SDA2/GPIO3

I2C_SCL2/GPIO4

DP_A

I C Port 2 Interrupt/ General Purpose I/O /Serial Wire Debug Data

2

PA3

I C Port 2 Data/ General Purpose I/O (Open Drain)

2

8

PA4

I C Port 2 Clock/ General Purpose I/O

9

Analog

PA5

Port A USB 2.0 D+ (Connector side)

Port A USB 2.0 D− (Connector side)

Port A USB 2.0 D− (Host side)

Port A USB 2.0 D+ (Host side)

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

DAP

DM_A

DM_HOST_A

DP_HOST_A

GPIO5/I2C_SDA4/SWCK

GPIO6/I2C_SCL4

GPIO7/I2C_INT4

HPD_A/GPIO8

VDDIO

2

General Purpose I/O/ I C Port 4 Data/ Serial Wire Debug Port Clock

2

PA6

General Purpose I/O I C Port 4 Clock

2

PA7

General Purpose I/O/ I C Port 4 Interrupt

PA8

Hot Plug Detect/ General Purpose I/O

I/O Voltage Supply

Power

Input

RESET_N

Active Low chip reset

DP_HOST_B

DM_HOST_B

DM_B

Analog

PA9

Port B USB 2.0 D+ (Host side)

Port B USB 2.0 D− (Host side)

Port B USB 2.0 D− (Connector side)

Port B USB 2.0 D+ (Connector side)

DP_B

2

I2C_INT1/GPIO9

I2C_SCL1/GPIO10

I2C_SDA1/GPIO11

HPD_B/GPIO12

HVCC1_B

I C Port 1 Interrupt/ General Purpose I/O

2

PA10

PA11

I C Port 1 Clock/ General Purpose I/O (Open Drain)

2

I C Port 1 Data/ General Purpose I/O

PA12

Analog

Power

Analog

Power

PA13

PA14

PA15

PA16

PA17

PA18

PA19

Analog

PA20

PA1

Hot Plug Detect/ General Purpose I/O

Port B High Voltage Configuration Channel 1 (28 V)

Port−B VCONN Supply

VCONN_B

HVCC2_B

Port B High Voltage Configuration Channel 2 (28 V)

Port B VBUS. Monitoring Discharge (28 V)

General Purpose I/O

VBUS_B

GPIO13

SRC_SNK_B/GPIO14

SNK_B/GPIO15

GPIO16

Port B Source/Sink load switch control/ General Purpose I/O

Port B Sink Control/ General Purpose I/O

General Purpose I/O

2

I2C_INT3/GPIO17

I2C_SDA3/GPIO18

I2C_SCL3/GPIO19

CAP

I C Port 3 Interrupt/ General Purpose I/O

2

I C Port 3 Data/ General Purpose I/O

2

I C Port 3 Clock/ General Purpose I/O

1.5 V capacitor

SNK_A/GPIO20

SRC_SNK_A/GPIO1

GND

Port A Sink Control/ General Purpose I/O

Port A Source/Sink load switch control/ General Purpose I/O

Ground

GND

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5

FUSB15200

APPLICATIONS DIAGRAM

The figure below shows a typical dual port DRP application.

Charger

VIN

FPF2895C+2595C

5 V

ILIM

FLAGb SRC/SNKb ONb

Supply

ONb SRC/SNKb FLAGb

VBUS_A

VBUS_B

SRC_SNK_A GPIO18

VCONN_A

VCONN_B GPIO17 SRC_SNK_B

GPIO20

GPIO19

GPIO15

GPIO13

VBUS_B

VBUS_A

HVCC1_A

HVCC2_A

HVCC1_B

HVCC2_B

DP_A

DM_A

DP_B

DM_B

VDD

I2C_INT2

I2C_SCL2

I2C_SDA2

I2C_INT2

I2C_SCL2

I2C_SDA2

FUSB15200

I2C_INT1

I2C_SCL1

I2C_SDA1

EC

Dual Port Controller

ARM−M0+

I2C_INT4

I2C_SCL4

I2C_SDA4

I2C_INT4

I2C_SCL4

I2C_SDA4

CAP

RESET_N

AC Present

VDDIO

GPIO16

HPD_B

VDDIO

GND

10

HPD_A

Display Port

Controller

Display Port

Controller

10

MUX

4

USB3.1

Figure 3. Application Diagram

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6

FUSB15200

ELECTRICAL SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS (Notes 1, 2, 3)

Symbol

Parameter

Min

−0.3

−0.5

−0.3

−0.5

−40

−

Max

28

Unit

V

VBUS

VBUS Pin Voltage

HVCC1, HVCC2 Connector Pins

DP, DM Connector Pins

I/O Voltage

V

28

V

CONNECTOR−HV

V

6.0

2.0

150

260

−

V

CONNECTOR−LV

VIO

V

VDD

VCONN

VDDIO

VCAP

Supply Voltage

V

Supply Voltage

V

VDDIO Supply

V

CAP Pin

V

T

J

Junction Temperature

Storage Temperature

°C

kV

T

STG

TL

Lead Temperature, (Soldering, 10 Seconds)

ESD

Human Body Model, ANSI/ESDA/JEDEC JS−001−2012 (Note 3)

Charged Device Model, JESD22−C101 (Note 3)

2

HBM

CDM

1

−

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. All voltage values, except differential voltages, are given with respect to the GND pin.

2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.

3. Meets JEDEC standards JS−001−2012 and JESD 22−C101.

RECOMMENDED ESD DEVICES

Function

Manufacturer

onsemi

Part Number

Type−C Connector Pins ESD

TBD

OPERATING RATINGS

Symbol

Parameter

Min

3.0

3.1

1.7

0

Typ

Max

5.5

Unit

V

CONN

Supply Voltage Range

3.3

−

V

DD

5.5

V

BUS

V

BUS

Voltage

22.05

5.5

V

DDIO

I/O Supply Voltage

−

V

Communication Channel Pins

DM, DP Pins

−

5.5

V

HVCCx

V

USB

0

−

3.6

V

IO

GPIO, I2C, RESET, HPD

0

−

5.5

V

T

A

Operating Ambient Temperature

−40

−

+85

°C

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

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7

FUSB15200

ELECTRICAL CHARACTERISTICS (Minimum and maximum values are at VDD = 2.8 V to 5.5 V, TA = −40°C to +85°C unless

otherwise noted. Typical values are at TA = 25°C, VDD = 3.3 V)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

TYPE−C AND PD SECTION

USB PD PHY

TRANSMITTER

UI

Unit Interval

3.03

−

3.33

−

3.7

ms

pBitRate

Maximum Difference between the bit−rate

During the Payload and Last 32 Bits of

Preamble

0.25

%

tEndDriveBMC

tHoldLowBMC

tInterFrameGap

Time to Cease Driving the Line after the

End of the Last Bit of the Frame

−

1

−

23

−

ms

Time to Cease Driving the Line after the

Final High−to−low Transition

Any PD Transmission Cannot be Sent

Out before a Dead Time of at Least

tInterFrameGap from Receiving or

Sending a Packet

25

−

tFall

tRise

Fall Time

300

−1

−

1

ns

ms

Rise Time

tStartDrive

Time before the Start of the First Bit of

the Preamble when the Transmitter Shall

Start Driving the Line

vSwing

zDriver

BMC Voltage Swing

1.05

33

1.125

−

1.2

75

V

TX Output Impedance at 750 kHz with

an External 220 pF or Equivalent Load

W

rFRSwapTx

Fast Role Swap Request Transmit Driver VDD = 3.0 V to 5.5 V

Resistance

−

5

−

W

RECEIVER

cReceiver

Receiver Capacitance when Driver isn’t

Turned On

Vrms = 0.371; Vdc = 0.5 V;

Freq. = 1 MHz

75

pF

tRxFilter

Rx Bandwidth Limiting Filter

100

12

−

ns

ms

tTransitionWindow Time Window for Detecting Non−idle

20

vFRSwapCableTx The Fast Role Swap Request Has to be

Below this Voltage Threshold to be

Detected

490

520

550

mV

tFRSwapRx

Fast Role Swap Request Detection Time

(Note 4)

30

1

−

50

−

ms

zBmcRx

Receiver Input Impedance (Cannot be

Tested but Can be Simulated and

Guaranteed by Design)

MW

TYPE−C FRONT END

I

SRC 80 mA CC Current (Default)

SRC 180 mA CC Current (1.5 A)

SRC 330 mA CC Current (3 A)

Device Pull−down Resistance

Powered Cable Termination

64

80

180

330

5.1

−

96

194

356

5.6

mA

kW

W

80_CCX

I

166

304

4.6

180_CCX

330_CCX

I

R

DEVICE

R

A

800

126

1200

−

zOPEN

CC Resistance for Disabled State, when

Vdd is Valid

−

kW

I

Over Current Protection (OCP) Limit at

which VCONN Switch Shuts Off over the

Entire VCONN Voltage Range

VCONN_OCP = 800 mA

600

5.6

800

−

1000

6.0

mA

V

SW_CCX

V

CC1/2 Over−Voltage Protection

CCx_OVP

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8

FUSB15200

ELECTRICAL CHARACTERISTICS (Minimum and maximum values are at VDD = 2.8 V to 5.5 V, TA = −40°C to +85°C unless

otherwise noted. Typical values are at TA = 25°C, VDD = 3.3 V)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

TYPE−C FRONT END

R

Rdson for VDD to CC1 or VDD to CC2

I

= 0 to 600 mA,

−

0.85

2.7

1.8

5

W

V

SW_CCx

SW_CCX

VCONN_OCP > 80 mA

R

Low OCP Setting Rdson for VDD to CC1

or VDD to CC2

I

= 0 to 80 mA,

−

SW_CCx_LOW_OCP

SW_CCX

VCONN_OCP ≤ 80 mA

vRdSRCUSB

Source Attach Threshold for CC Pin at

Default Current

1.5

1.6

1.65

2.75

0.25

0.45

0.85

0.7

vRdSRC1.5

vRdSRC3.0

vRaSRCUSB

vRaSRC1.5

vRaSRC3.0

vRdSNKUSB

vRdSNK1.5

vRdSNK3.0

Source Attach Threshold for CC Pin at

1.5 A Current

1.5

1.6

Source Attach Threshold for CC Pin at

3 A Current

2.45

0.15

0.35

0.75

0.61

1.16

2.04

2.6

Source Ra Threshold for CC Pin at

Default Current

0.2

Source Ra Threshold for CC Pin at

1.5 A Current

0.4

Source Ra Threshold for CC Pin at

3 A Current

0.8

Attach Threshold for CC Pin SNK

(Default Current)

0.66

1.23

2.11

Attach Threshold for CC Pin SNK

(1.5 A Current)

1.31

2.18

Attach Threshold for CC Pin SNK

(3 A Current)

vRaSNK

vSafe0V

Attach Threshold for CC Pin SRC or SNK

Safe Operating Voltage at 0 V

0.15

0.6

0.2

−

0.25

0.8

V

VBUS DISCHARGE

R

Pull−down Resistance Applied to VBUS

when Selected

VBUS = 0.8 V to 21.5 V

315

420

450

600

585

780

W

VBUS_DISCH_0

VBUS_DISCH_1

VBUS_DISCH_2

VBUS_DISCH_3

VBUS_DISCH_4

VBUS_DISCH_5

525

750

975

700

1000

2000

6.00

1300

2600

7.80

1400

4.20

kW

mA

CURRENT CONSUMPTION

I

Current Consumption when in Deep

Sleep

VDD = VDDIO = 3.0 to 5.5 V

VBUS = 0 V; Not Type−C

attached, DRP Toggling; LSOSC

enabled; BC1.2 disabled

−

75

−

SLEEP−UNATTACHE

D

I

Sleep Current

VDD = VDDIO = 3.0 to 5.5 V

700

mA

SLEEP

2

VBUS = 0; No I C traffic, LSOSC

and HSOSC running; PD

Peripheral and ADC enabled.

No PD traffic.

I

Port with PD Traffic

POR Trip point

Active and communicating via

USB PD transmitting and receiving

packets on both ports

−

4.0

−

mA

PD−ACTIVE

PMU

V

VDD Rising

1.0

3.0

−

2.4

−

V

VDD_POR

VDD_GOOD

VDDIO_GOOD

V

Minimum VDD Level for Enabling Device VDD Rising

V

VDDIO Detection Threshold Used in

Asserting PMU_STS when VDDIO is

above it

VDDIO Rising

VDD Falling

1.0

V

VDD Brown Out Threshold

2.6

−

3.0

V

VDD_BRWN

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9

FUSB15200

ELECTRICAL CHARACTERISTICS (Minimum and maximum values are at VDD = 2.8 V to 5.5 V, TA = −40°C to +85°C unless

otherwise noted. Typical values are at TA = 25°C, VDD = 3.3 V)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

PMU

V

VDD Voltage where the Device is

Powered from VDD Instead of VBUS

VDD Rising

2.6

−

3.0

V

VDD_DBAT

CLOCKS

F

Low Speed Clock for Idle, Type−C Attach

114

120

24

126

kHz

LS_CLK

HS_CLK

F

Internal Clock for Active Core and Full

Function

22.8

25.2

MHz

EXTERNAL TEMPERATURE PROTECTION

I

Current Source on NTCA

Current Source on NTCB

55

60

65

mA

NTCA

NTCB

INTERNAL TEMPERATURE MEASUREMENT

Temperature for Internal Temperature

T

SHUT

VDD = 3.0 to 5.5

−

145

10

−

°C

Protection

T

HYS

Temp Hysteresis for Internal

Temperature Protection

BC1.2 DETECTION

R

DCP Emulation Resistance

DP/DM Pull Down Resistance

DCD Source Current

VD+/D− = 0 V, 1.0 V, ION = 2 mA

VD+/− = 0 V − 3.6 V

VDD = 3.0 V to 5.5 V

5 mA pulled out of DP

5 mA pulled out of DM

V(sw) = 0 to 3.6 V

−

16

80

19.5

10

180

23

W

kW

mA

V

DCP

R

Dx_DWN

DP_SRC

I

7

13

I

Sink Current to Dx

25

75

175

2.85

36

Dx_SNK

V

Divider Mode Output Voltage

Divider Mode Resistance on DP

Divider Mode Resistance on DM

Resistor Weak Pull−down on D+ and D−

Source Voltage

2.65

24

2.75

30

DIV

R

kW

V

DIVP

DIVM

R

24

30

36

R

300

0.5

288

0.9

700

0.6

320

1.0

1100

0.7

352

1.1

DAT_LKG

V

VDD = 3.0 V to 5.5 V

Dx_SRC

PU_MOS

SRC_MOS

R

Pull−Up Moisture Detection Resistor

Voltage Source for Moisutre Detection

kW

V

SWITCH PATHS

I

Power−Off Leakage Current

USB Switch On Resistance

All data ports, vsw = 3.6, vdd = 0

−

5

18

−

mA

OFFUSB

R

Vsw− =0 V, 0.4 V, ION = 8 mA,

VDD = 3.0 to 5.0 V

W

ONUSB

C

ONUSB

DP_x, DM_x On Capacitance

Vsw = 400 mVpk−pk, f = 240 MHz,

VDD = 3.8

−

7.5

−

pF

C

DP/DM OFF Capacitance

Differential −3 db Bandwidth

f = 240 MHz, VDD = wc

−

3.3

−

pF

OFFUSB

BW

Vsw = 400 mVpk−pk, RL = 50 W,

650

MHz

USB

CL = 0 pF, VDD = 3.0 to 5.0 V

HPD

HPD_Rx

V

Low−Level Input Voltage

High−Level Input Voltage

Input Hysteresis

VDD = 2.8 V to 5.5 V,

VBUS = 3.1 V to 22.5 V, or

VDD = 0 V and VBUS = 3.1 V to

22.5 V

−

2.0

−

0.8

−

V

IL−HPD

V

VDD = 2.8 V to 5.5 V,

VBUS = 3.1 V to 22.5 V, or

VDD = 0 V and VBUS = 3.1 V to

22.5 V

IH−HPD

V

VDD = 2.8 V to 5.5 V,

280

−

mV

HYS−HPD

VBUS = 3.1 V to 22.5 V, or

VDD = 0 V and VBUS = 3.1 V to

22.5 V. Typ VDD = 3.0 V

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10

FUSB15200

ELECTRICAL CHARACTERISTICS (Minimum and maximum values are at VDD = 2.8 V to 5.5 V, TA = −40°C to +85°C unless

otherwise noted. Typical values are at TA = 25°C, VDD = 3.3 V)

Symbol

HPD_Rx

Parameter

Conditions

Min

Typ

Max

Unit

I

Input Leakage

VDD = 2.8 V to 5.5 V,

−5

−

5

mA

IN−HPD

VBUS = 3.1 V to 22.5 V, or

VDD = 0 V and VBUS = 3.1 V to

22.5 V, Input Voltage 0 V to 3.6 V

I

Off Input Leakage

Pin Capacitance

VDD = 0 V, VBUS = 0 V,

Input Voltage 0 V to 5.5 V

−5

−

5

−

mA

OFF−HPD

C

pF

IN−HPD

HPD_Tx

V

Ouptut Low Voltage

VDD = 2.8 V to 5.5 V,

−

0.4 V

3.6

−

V

OL−HPD

VBUS = 3.1 V to 22.5 V, or

VDD = 0 V and VBUS = 3.1 V to

22.5 V, Iout = +4 mA

V

Output High Voltage for HPD Output

VDD = 2.8 V to 5.5 V,

2.25

100

OH−HPD

VBUS = 3.1 V to 22.5 V, or

VDD = 0 V and VBUS = 3.1 V to

22.5 V, Iout = −2 mA

R

Pull Down resistance on HPD Pin when

Enabled

PORT’s pull−down resistance is

enabled and HPD peripheral is

enabled

kW

PD−HPD

SERIAL WIRE DEBUG INTERFACE

F

Serial Wire Debug Input Clock Frequency Core frequency = 24 MHz

Serial Wire Debug Data Setup Timing

−

10

−

MHz

ns

SWDCLK

T

0.25 * (1 /

SWCLK)

SWDI_SET

T

Serial Wire Debug Data Hold Timing

0.25 * (1 /

SWCLK)

−

ns

V

SWDI_HOLD

V

Serial Wire Debug Input Voltage

Threshold

VDDIO = 1.7 V to 5.5 V

0.7 x

VDDIO

IH−SWD

V

−

0.3 x

VDDIO

IL−SWD

V

Serial Wire Debug Input Voltage

Hysteresis

300

−

+10

−

mV

mA

V

HYS−SWD

I

Serial Wire Debug Input Leakage

VDDIO = 1.7 V to 5.5 V,

Input Voltage 0 V to 5.5 V

−10

LKG−SWD

V

Serial Wire Debug Output Voltage High

Serial Wire Debug Output Voltage Low

VDDIO = 1.7 V to 5.5 V,

Iout = −2 mA

VDDIO −

0.5 V

−

OH−SWD

V

VDDIO = 1.7 V to 5.5 V,

Iout = +4 mA

−

0.4 V

V

OL−SWD

RESET

RESET_N_VIL1

Low Level Input Voltage

High Level Input Voltage

VDD = 2.8 V to 5.5 V

−

0.3 x

VDD

V

RESET_N_VIH1

0.7 x

VDD

−

RESET_N_RPU

RESET_N_ILKG

GPIO

Internal Pull−Up Resistor to VDD

Input Leakage

−

100

−

kW

mA

−120

VI

High Level Input Voltage

Low level Input Voltage

VDDIO = 1.7 V to 5.5 V

0.7 x

VDDIO

−

V

H−GPIO

V

−

0.3 x

VDDIO

IL−GPIO

V

Output High Voltage (Not Applicable to

Open−Drain GPIO3 and GPIO10)

VDDIO = 1.7 V to 5.5 V,

Iout = −2 mA

VDDIO −

0.5

−

OH−GPIO

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11

FUSB15200

ELECTRICAL CHARACTERISTICS (Minimum and maximum values are at VDD = 2.8 V to 5.5 V, TA = −40°C to +85°C unless

otherwise noted. Typical values are at TA = 25°C, VDD = 3.3 V)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

GPIO

V

Output Low Voltage

VDDIO = 1.7 V to 5.5 V,

Iout = +4 mA

−

0.4

V

OL−GPIO

V

SNKx Pin Output High Voltage

SNKx Pin Output Low Voltage

Output High Voltage for PA4 and PA8

2.5

−

0.4

−

V

OH−SNK

V

OL−SNK

OH−NTC

V

VDD = 2.8 V to 5.5 V, Iout = −2mA

VDD –

0.5

V

Output Low Voltage for PA4 and PA8

Input Hysteresis

VDD = 2.8 V to 5.5 V, Iout = +4mA

VDDIO = 1.7 V to 5.5 V, 3.6 V Typ

−

300

−

0.4

−

V

OL−NTC

V

mV

mA

HYS−GPIO

I

Input Leakage

VDDIO = 1.7 V to 5.5 V, Input

Voltage 0 V to 5.5 V

−5

5

IN−GPIO

I

Off Input Leakage

VDDIO = 0 V, VDD = 0 V to 5.5 V,

Input Voltage 0 V to 5.5 V

−5

−

5

mA

OFF−GPIO

R

Pull−Down Resistance

PORT_PDx = 1

PORT_PUx = 1

−

100

−

kW

PD−GPIO

Pull−Up Resistance (Not Applicable to

Open−Drain GPIO3 and GPIO10)

PU−GPIO

C

GPIO

Pin Capacitance

−

5

−

pF

2

I C I/O

I

VDD Current when SDA or SCL is HIGH

Input Current of SDA and SCL Pins

High−Level Input Voltage

VDD = 2.8 to 5.5, VIN = 1.8 V

VDD = 2.8 to 5.5, VIN = 0 to 5.5 V

VDD = 2.8 to 5.5

−10

1.2

−

10

−

mA

V

CCTI2C

I

i2C

V

IH−I2C

V

Low−Level Input Voltage

VDD = 2.8 to 5.5

0.4

0.3

V

IL−I2C

V

Low−Level Output Voltage at 3 mA Sink

Current (Open−Drain)

VDD = 2.8 to 5.5

0

V

OL1−I2C

OL2−I2C

HYS−I2C

V

Low−Level Output Voltage at 2 mA Sink

Current (Open−Drain)

VDD = 2.8 V − 5.5 V

0

−

0.3

V

Hysteresis of Schmitt Trigger Inputs

Low−Level Output Current (Open−Drain)

INT_N Output Low Voltage

VDD = 2.8 to 5.5

0.1

20

−

0.2

−

V

mA

V

I

VDD = 2.8 to 5.5, VOL = 0.4 V

VDD = 2.8 to 5.5, IOL = 4 mA

VDD = 2.8 to 5.5

OLSDA

V

−

0.4

−

OL_INT

C

Capacitance for Each I/O Pin

−

5

pF

ns

I−I2C

t

SP

Pulse Width of Spikes that Must be

Suppressed by the Input Filter

0

−

50

V

High−Level Input Voltage

Low−Level Input Voltage

VDD = 2.8 to 5.5

1.2

−

V

IH_INT

V

0.4

IL_INT

FLASH

NEND

Sector Endurance

Data Retention

20,000

−

Erase/

write

cycles

T

DR

T = 25°C

T = 105°C

T = 125°C

100

20

−

years

Years

10

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

4. (SRC/SNK I/Os will switch to its new configuration based on USB_IO_CONFIG setting within tFRSwapRx(max))

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12

FUSB15200

Arm Cortex−M0+ Processor

Low power features on FUSB15200 include the WIC,

adjustable clock rates, and different software controlled

power modes to maximize opportunities to save power in the

final application.

The FUSB15200 integrates an ARM Cortex−M0+

processor with Nested Vector Interrupt Controller (NVIC),

Wake−up Interrupt Controller (WIC), and Debug Access

Port (DAP). The processor uses the Thumb instruction set

and is optimized for high performance with reduced code

size and low power operation. The ARM Cortex−M0+

efficiently handles multiple parallel peripherals and has

integrated sleep modes. Test and debug capability is

enhanced with the ARM Serial Wire Debug Port.

Power Management Unit

The Power Management Unit (PMU) provides

appropriate power to all the blocks in the FUSB15200.

The FUSB15200 is able to power from either VBUS pin

when VDD is not present (dead battery condition). When

VDD > VDD_DBAT becomes available, PMU will

automatically switch the internal power to VDD.

When device is powered from VBUS alone, the SNK pins

can be controlled without VDDIO.

The FUSB15200 power management unit prevents

system brown−outs in case VDD voltage dips below the

specified minimum voltage required for reliable operation.

Firmware may monitor the power supply and safely shutting

down the system if needed.

The ARM implementation in the FUSB15200 includes a

132KB Flash RAM and 6KB of SRAM.

The MCU, Memory and DAP are interconnected using

the AMBA (Advanced Microcontroller Bus Architecture)

AHB−Lite interface and peripherals are connected to the

AHB via APB interface (Advanced Peripheral Bus).

In addition to the base Arm Cortex−M0+ processor

interrupts, the FUSB15200 implements multiple external

source interrupts for peripheral devices. A powerful nested,

pre−emptive and priority based interrupt handling system

assures timely and flexible response to external events.

(3.0 V − 24 V)

(3.0 V − 5.5. V)

(1.7 V − 5.5 V)

VBUS_B

VBUS_A

VDD

VDDIO

POR

VDDIO Detect

VBUS_B_VAL

VBUS_A_VAL

VDDIO_GOOD

POR

V1P5_POR

1.5 V

Power

Regulator

(VCORE)

VCAP

Selection

V1P5

(5.0)

POR

VDD/

BRWNOUT

VDD_GOOD

UVLO

Figure 4. FUSB15200 PMU

Reset Sources

Software reset resets the entire chip including core,

peripherals, wakeup timer, and watchdog.

The FUSB15200 has various sources of reset including:

• Internal Power−On Reset (VDD_POR)– The VDD_POR

reset asserts when the regulated supply is below threshold

levels for proper operation. The VDD_POR resets the

entire chip including core, debug port, peripherals,

wakeup timer, and watchdog.

• Software Issued Reset – The software reset can be called

by writing to a given register in the Cortex address space.

It is typically called on exit from a processor exception.

• Watchdog Timer Reset – The watchdog timer reset is

caused by the watchdog timeout and is used to prevent

errant software from locking up the device. The

watchdog reset resets the entire chip including core,

debug port, peripherals, and watchdog. The watchdog

timer is disabled upon power up and must be enabled by

software. The watchdog is paused when the debugger

halts the processor.

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13

FUSB15200

32−bit Watchdog Timer (WDT)

• External Pin Reset – The external reset is under user

control with the external RESET_N pin. External pin

reset resets the entire chip including core, debug port,

peripherals, wakeup timer, and watchdog

The watchdog timer applies a reset to the system in the

event of a software failure, providing a way to recover from

software crashes. The watchdog timer is disabled by default

and must be enabled through software.

Power and Sleep Behavior

The watchdog is protected with a lock mechanism to

prevent rogue software from disabling the watchdog

functionality. A special value has to be written to the lock

register to access watchdog control.

The FUSB15200 has been optimized to conserve power

by utilizing peripheral interrupts and hardware autonomy.

The device can be configured via firmware to enter low

power states, disable unneeded peripherals and scale clock

frequencies based on different application needs.

The Type−C block is designed to function at the lowest

power states and will automatically wake when a Type−C

attach is detected. This minimizes total power consumption

when no device is attached.

Serial Wire Debug Interface (SWD)

The ARM M0+ implementation includes a Debug Access

Port (DAP).

The debug mode implementation includes 4 hardware

breakpoints and 2 hardware watch points.

The Debug Access Port interface implementation is the

ARM Serial Wire Debug Port (SW−DAP) connected to pins

SWCLK and SWDIO. The Serial Wire Debug Port Interface

uses a single bi−directional data connection. Each operation

consists of three phases: Packet request, Acknowledge

response, and Data transfer phase. Use any Serial Wire

Debug (SWD) compliant hardware debugger interface to

interact with the internals of the FUSB15200.

Clock Sources

FUSB15200’s implements a dual oscillator architecture to

minimize power consumption.

• A 24 MHz internal RC oscillator to enable full

functionality.

• A 120 kHz internal RC oscillator that can be used for very

low power sleep modes.

USB Type−C & PD Peripheral Overview

Timers

The USB Type−C and PD peripheral provides

the building blocks to enable a fully compliant USB Type−C

and PD solution.

This peripheral consists of an analog front end and a

digital state machine. Firmware implements higher level

protocol and policy layers whereas the analog and digital

components can perform lower level PD protocol and PHY

layer functions.

The Type−C block includes all terminations and

comparators required for Source/Sink/DRP operation: plug

orientation detection, power capability advertisement and

power role detection.

32−bit General Purpose Timers (TIM0/1)

There are two 32−bit down−counters that can generate an

interrupt request signal, status, when the counter reaches 0.

The timing resolution depends on the programmable

clock source and pre−scale ratios.

32−bit Wake−up Timer (WUT)

The main purpose of the wakeup timer is to facilitate

scheduled exit from low power modes. It can also be used

for general purpose event timing.

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14

FUSB15200

VCONN Switch

VCONN

Type−C Terminations

CC1

CC2

VDD

CC State Machine &

Comparators

LV REG

USB PD PHY

Timers

ADC

BMC

Rcvr

ARM

M0+

BMC

DRIVER

CRC32Tx

4B5B

BMC

Encode

SRAM

6 KB

Type−C

CDR

BMC

Decode

4B5B

Flash

132 KB

USB PD

CRC32Rx

Figure 5. USB Type−C and PD

VBUS Discharge

VCONN Switch

Some applications require that a VCONN voltage be

sourced in order to provide additional capabilities, such as

greater than 3 A VBUS sourcing or support for full−featured

Type−C cables.

The FUSB15200 can provide 1.5 W or more depending on

VCONN level.

The FUSB15200 is able to discharge VBUS via selectable

pull−down resistors.

Typical source applications will rely on the DC−DC

converter to transition between VBUS voltages.

If the application requires the FUSB15200 to discharge

VBUS, the firmware may select the proper resistance of the

discharge. Selection of discharge resistance needs to take

into account any capacitive load on VBUS as not to violate

VsrcSlewNeg in the USB PD spec (30 mV/ms).

Source applications, where the FUSB15200 internal

discharge is utilized, will have to isolate any large bulk

capacitances in order to prevent extreme internal

temperature rises. Typical isolated source capacitances are

around 4.7 mF.

USB PD PHY State Machine Logic

The FUSB15200 PD module includes the following

digital functions to enable USB PD messaging:

• Serialization and de−serialization

• Clock and data recovery (CDR)

• 4B5B coding

• BMC coding

The FUSB15200 is capable of discharging up to 100 mF

from VBUS in the entire operating range.

• Packet CRC generation and checking

• Coding and detection of Power Delivery K−Codes

• Automatic GoodCRC packet response

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15

FUSB15200

Fast Role Swap

Moisture detection can be turned on or off as not to

conflict with cable attach detection.

Fast Role Swap is the process of exchanging the Source

and Sink roles between Port Partners rapidly due to the

disconnection of an external power supply.

+

−

The Fast Role Swap process is intended for use by a

capable USB device that presently has an external power

supply, and is providing power both through its downstream

Ports to USB Devices and upstream to a USB Host such as

a laptop. On removal of the external power supply Fast Role

Swap enables a VBUS supply to be maintained by allowing

the USB Host to apply vSafe5V after having detected Fast

Role Swap signaling. The initial Source will signal a Fast

Role Swap request by driving CC to ground with a resistance

of less than rFRSwapTx for tFRSwapTx. The initial Source

will only signal a Fast Role Swap when it has an Explicit

Contract.

VSRC_MOS

RPU_MOS

To ADC

DP

OVP

Figure 6. Moisture Detection

Port Control and GPIOs

The FUSB15200 includes a number of pins that can be

configured to be used as standard GPIO or for use with a

2

dedicated peripheral such as I C. A subset of these pins can

The FUSB15200 has dedicated I/Os (SRC_SNK_x and

SNK) that can autonomously toggle when programmed to

detect or transmit a fast role swap signal.

also be connected as an input to the ADC. Internal

pull−up/down resistors are programmable. Pull−up resistors

are always connected to VDDIO.

When the PORT is configured as GPIOs it will have the

following capabilities:

• Bi−directional capability

Internal Protection

The FUSB15200 integrates multiple system level

protections to enable robust designs.

• Push pull or open drain configuration

• Individually configurable interrupt lines

• Rising or Falling edge interrupt

• High or Low level interrupt

VCONN Over−Current Protection

Each port’s VCONN Switch provides over−current

detection and protection for the switch that is enabled based

on the Type−C orientation and can be software configured

based on application needs. The level of OCP can be

controlled via a register setting.

NOTE:

5. PA14 and PA20’s output supply is derived from an

internal 3.0 V regulator to guarantee operation of sink

path load switch in dead battery condition.

6. GPIO3 and GPIO10 are Open−Drain and do not have

pull−up resistance.

In case of an over−current event the switch will be opened.

CC Over−Voltage Protection

Over−voltage protection on CC pins protects the internal

circuitry damage from high voltages.

Interrupts can be used to inform the software that an OVP

event has occurred and take appropriate actions.

VDDIO

RPU

Internal Over Temperature Protection

Internal over temperature protection is always on. Two

potential sources of elevated internal temperature are:

PORT_PUx

Analog

• High Current through VCONN Switch

Peripheral

GPIO

MUX

• High current through VBUS discharge

PAx

In either case, if the over temperature is triggered (T >

Tshut), both ports’ VCONN switches and VBUS discharge

circuitry will be disabled.

PORT_PDx

PORT_CFGx

Connector Moisture Detection

RPD

If moisture or pollutants are present in the connector and

the device provides VBUS, there could be a resistive short

between VBUS and other connector pins.

GND

The FUSB15200 provides a method to detect if there is

moisture or other pollutants in the connector.

Figure 7. Typical Port Configuration

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16

FUSB15200

Table 1. PIN − PORT CONFIGURATION AND POWER

DOMAIN

DOMAIN (continued)

Pin #

Name

SRC_SNK_N_A

GPIO1

Port

Power Supply

VDDIO

VDD

Pin #

Name

I2C_SCL1

GPIO10 (OD)

I2C_SDA1

GPIO11

Port

Power Supply

VDD

40

PA1

24

PA10

VDDIO

VDD

6

I2C_INT2

GPIO2

PA2

25

26

PA11

PA12

VDDIO

VDD

VDDIO

SWD

HPD_B

Internal 3.0 V

Regulator

7

8

I2C_SDA2

GPIO3 (OD)

I2C_SCL2

GPIO4

PA3

PA4

PA5

GPIO12

GPIO13

VDDIO

VDD

31

32

PA13

PA14

SRC_SNK_N_B

GPIO14

Output = Internal

3.0 V Regulator

Input = VDDIO

VDDIO

VDD

13

I2C_SDA4

GPIO5

33

SNK_B

PA15

VDDIO

VDD

VDDIO

VDD

GPIO15

SWCK

34

35

GPIO16

PA16

PA17

14

15

16

I2C_SCL4

GPIO6

PA6

PA7

PA8

I2C_INT3

GPIO17

VDDIO

VDD

VDDIO

VDD

I2C_INT4

GPIO7

36

37

39

I2C_SDA3

GPIO18

PA18

PA19

PA20

VDDIO

VDD

HPD_A

Internal 3.0 V

Regulator

I2C_SCL3

GPIO19

GPIO8

RESET_N

I2C_INT1

GPIO9

VDDIO

VDD

VDDIO

18

23

Input

PA9

SNK_A

Output = Internal

3.0 V Regulator

Input = VDDIO

VDD

GPIO20

VDDIO

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17

FUSB15200

Table 2. PORT DEFAULT CONFIGURATION

Default Configuration

on Power Up

Analog

Function

Pin #

40

6

FUSB15200 Pin Name

SRC_SNK_N_A/GPIO1

I2C_INT2/GPIO2/SWD

I2C_SDA2/GPIO3

I2C_SCL2/GPIO4

GPIO5/I2C_SDA4/SWCK

GPIO6/I2C_SCL4

GPIO7/I2C_INT4

Port

PA1

I/O State

Input Float

Input

NMI

GPIO1

SWD

PA2

7

PA3

GPIO3 (OD)

GPIO4

Input Float

Input

8

PA4

13

14

15

16

23

24

25

26

31

32

33

34

35

36

37

39

PA5

SWCK

PA6

GPIO6

Input Float

Input

PA7

GPIO7

Yes

HPD_A/GPIO8

PA8

GPIO8

I2C_INT1/GPIO9

PA9

GPIO9

I2C_SCL1/GPIO10

I2C_SDA1/GPIO11

HPD_B/GPIO12

PA10

PA11

PA12

PA13

PA14

PA15

PA16

PA17

PA18

PA19

PA20

GPIO10 (OD)

GPIO11

GPIO12

GPIO13

GPIO14

GPIO15

GPIO16

GPIO17

I2C_SDA

I2C_SCL

GPIO20

GPIO13

Yes

SRC_SNK_N_B/GPIO14

SNK_B/GPIO15/NTC_B

GPIO16

Input Float

Input

Yes

I2C_INT3/GPIO17

I2C_SDA3/GPIO18

I2C_SCL3/GPIO19

SNK_A/GPIO20/NTC_A

Input Float

Input

Input Float

Non−Maskable Interrupts (NMI)

DP Receiver Behavior

The FUSB15200 provides a method of selecting one of

four GPIOs that can be used as a source of an external

non−maskable interrupt. (See table 2)

If a non−maskable external interrupt is not required, all

GPIOs provide a method to interrupt the processor. In this

case, the Brown−Out detector can be assigned to the NMI

slot of the interrupt controller.

When the FUSB15200 is implemented in a DP Receiver,

the HPD I/O is setup as an input. Debounce timers

implemented in HW facilitates HPD IRQ and Level

detection. Please see HPD_Rx in Electrical Specifications.

DP Source Behavior

When the FUSB15200 is implemented in a DP Source, the

HPD I/O is setup as an Output.

The HPD output will be driven by the firmware. HPD IRQ

pulsewidth timer is implemented in hardware, see HPD_Tx

in Electrical Specifications.

The port mapping, power domain and default

configuration are shown in the Table 2.

HPD I/Os

HPD I/Os are used in DisplayPort (DP) applications to

signal events between the DP Source and DP Receiver.

The FUSB15200 HPD I/Os can be configured as an input

(DP receiver) or Output (DP Source).

The HPD I/Os supply is derived from an internal 3.0 V

regulator to guarantee levels in all conditions.

If the application does not have external pull−down

resistors as required by the VESA spec, internal pull downs

can be enabled via the PORT interface. When the HPD

peripheral is enabled, an additional resistance is added to the

PORT’s pull−down to achieve the minimum 100 kOhm

required (See figure 8 below).

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18

FUSB15200

VCORE

3.0 V Reg

HPD Peripheral

VDDIO

RPU

Digital Logic

HPD_IRQ

Detector

Debounce

Logic

PORT_PUx

PORT_PDx

HPD_IRQ

Generator

HPD_A/GPIO8

or

HPD_B/GPIO12

MUX

VDDIO

GPIO

RPD

HPD_RPD

HPD_EN

PORT_CFGx

GND

Figure 8. HPD I/O Configuration

External Temperature Measurements

There are two pins that can be configured to monitor

external NTC resistors that can be located near where high

temperature devices are located. A parallel resistor is

recommended for measurement linearity.

These NTC measurements are useful for monitoring

temperatures for protection due to excessive thermals.

Firmware implementation of the external temperature

measurements make NTC selection flexible.

The pull−up current sources INTCA and INTCB provide

a bias to the external NTC resistor networks. If desired, this

current source may be turned−off.

−

INTCA

+

ADC_CH3

NTC_A/GPIO8

MUX

GPIO

R_PAR

R_NTC

PORT_CONFIG

−

INTCB

+

ADC_CH7

NTC_B/GPIO4

R_NTC

MUX

GPIO

R_PAR

PORT_CONFIG

Figure 9. External NTC Diagram

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19

FUSB15200

BC1.2 Support

The FUSB15200 is capable of emulating and detecting

BC1.2 and Divider Mode.

I²C

2

The FUSB15200’s four I C serial interfaces are

compatible with Standard, Fast, and Fast Mode Plus I2C bus

specifications. The I C peripheral can be configured for

2

The following modes are supported:

either host or device modes.

• SDP

• CDP

• DCP

Bus Timing

As shown in figure below, for data bits, SDA must be

stable while SCL is HIGH. SDA may only transition when

SCL is LOW. Data is clocked in on the rising edge of SCL.

Typically, data transitions shortly at or after the falling edge

of SCL to allow ample time for the data to set up before the

next SCL rising edge.

• 2.4 A Divider Mode (Provider only)

The analog circuitry is firmware configurable for the

function required by the application and follows the final

BC1.2 specification.

Figure 10. I²C Bus Timing Definition

Each bus transaction begins and ends with SDA and SCL

HIGH. A transaction begins with a START condition, which

is defined as SDA transitioning from 1 to 0 with SCL HIGH.

A transaction ends with a STOP condition, which is

defined as SDA transitioning from 0 to 1 with SCL HIGH.

During a read from the FUSB15200, the host issues a

Repeated Start after sending a data command and before

resending the device address. The Repeated Start is a 1−to−0

transition on SDA while SCL is HIGH.

2

7. Bus timing referenced from I C−bus specification Rev. 6 – 4 April 2014

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20

FUSB15200

ADC

The FUSB15200 allows for up to 12 signals to be

measured and converted using the internal 10−bit ADC. For

most applications, this will consist of two VBUS voltages,

two NTC temperature channels, two D+/D− BC1.2 and,

optionally, two CC1/2 ports. The table below shows the

typical FUSB15200 configuration along with the expected

settings for the ADC module.

Table 3. ADC CONFIGURATION ADC CHANNEL

ADC Channel

Pin Measurement

Resolution

10 mV

20 mV

40 mV

4 mV

Range

Full Scale Voltage

1.024 V

2.048 V

4.096 V

1.28 V

0

VBUS_A

0 V to 10.23 V

0 V to 20.46 V

0 V to 40.92 V

0 V to 4.096 V

0°C to 160°C

0 V to 4.096 V

0 V to 10.23 V

0 V to 20.46 V

0 V to 40.92 V

0 V to 4.096 V

0°C to 160°C

0 V to 4.096 V

1

2

3

4

5

6

DP_A

DM_A

4 mV

NTC1 Temperature

HVCC1_A

HVCC2_A

VBUS_B

1°C

4 mV

4.096 V

1.024 V

2.048 V

4.096 V

1.28 V

4 mV

10 mV

20 mV

40 mV

4 mV

7

8

DP_B

DM_B

4 mV

9

NTC2 Temperature

HVCC1_B

1°C

10

11

4 mV

4.096 V

HVCC2_B

4 mV

Development Tools

Specifications References

FUSB15200 is supported by a full suite of comprehensive

tools including:

•

Universal Serial Bus Power Delivery specification

revision 3.1 Version 1.3, dated January 2022

• An easy−to−use development board

• Software Development Kit (SDK) including:

USB PD protocol stacks, shared capacity algorithms,

sample code, libraries, and documentation

• Universal Serial Bus Type C Cable and Connection

Specification release 2.1, dated May 2021

• USB Battery Charging Specification, revision 1.2, dated

December 7, 2010

• I2C−bus specification Rev. 6 – 4 April 2014

Arm and Cortex are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. DisplayPort is registered trademark owned by the

2

Video Electronics Standards Association (VESA®) in the United States and other countries. onsemi is licensed by the Philips Corporation to carry the I C

bus protocol.

www.onsemi.com

21

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

QFN40 5x5, 0.4P

CASE 485CR

ISSUE C

DATE 27 AUG 2013

1

40

SCALE 2:1

NOTES:

L2

A

B

D

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSIONS: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN

0.15 AND 0.30mm FROM THE TERMINAL TIP.

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

PIN ONE

LOCATION

L2

DETAIL A

E

MILLIMETERS

DIM MIN

MAX

1.00

0.05

L

A

A1

A3

b

0.80

−−−

0.15

C

0.20 REF

L1

0.15

0.25

0.15

C

D

D2

E

E2

e

L

5.00 BSC

TOP VIEW

3.40

3.60

DETAIL A

5.00 BSC

ALTERNATE TERMINAL

CONSTRUCTIONS

3.40

3.60

DETAIL B

(A3)

0.40 BSC

0.10

0.08

C

0.30

−−−

0.50

0.15

A

L1

L2

EXPOSED Cu

MOLD CMPD

0.12 REF

A1

SEATING

PLANE

NOTE 4

C

SIDE VIEW

GENERIC

MARKING DIAGRAM*

DETAIL B

ALTERNATE

M

0.10

C

A

B

1

CONSTRUCTION

D2

DETAIL A

XXXXXXXX

AWLYYWWG

G

11

M

0.10

C A B

21

E2

XXXXX = Specific Device Code

1

A

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

40

WL

YY

WW

G

40X b

40X

L

e

M

0.10

C

A B

e/2

BOTTOM VIEW

0.05

NOTE 3

(Note: Microdot may be in either location)

RECOMMENDED

SOLDERING FOOTPRINT

*This information is generic. Please refer

to device data sheet for actual part

marking.

5.30

40X

0.63

Pb−Free indicator, “G” or microdot “ G”,

3.64

may or may not be present.

1

5.30

3.64

PKG

OUTLINE

40X

0.25

0.40

PITCH

DIMENSIONS: MILLIMETERS

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98AON83971E

QFN40, 5x5, 0.4P

PAGE 1 OF 1

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the

rights of others.

www.onsemi.com

onsemi,

, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates

and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.

A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any

products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the

information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use

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ADDITIONAL INFORMATION

TECHNICAL PUBLICATIONS:

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onsemi Website: www.onsemi.com

ONLINE SUPPORT: www.onsemi.com/support

For additional information, please contact your local Sales Representative at

www.onsemi.com/support/sales




型号：	FUSB15200MNTWG
厂家：	ONSEMI
描述：	Dual Port USB Type-C & PD Controller for Sink and DRP Applications 光电二极管
文件：	总23页 (文件大小：261K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

FUSB15200MNTWG [ONSEMI]

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