FUSB301ATMX [ONSEMI]
自动 USB Type-C 控制器，带有可配置 I2C 地址;
| 型号： | FUSB301ATMX |
| 厂家： | 
ONSEMI |
| 描述： | 自动 USB Type-C 控制器，带有可配置 I2C 地址 控制器 |
| 文件： | 总13页 (文件大小：336K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUSB301A
Autonomous USB Type-C
Controller with
Configurable I2C Address
Description
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The FUSB301A is a fully autonomous Type-C controller optimized
for < 15 W applications. The FUSB301A offers CC logic detection for
Source Mode, Sink Mode, DRP, accessory detection support, and dead
2
battery support. The FUSB301A features configurable I C address
toꢀsupport multiple ports per system. The FUSB301A features an
extremely low power disable mode as well as low power during
normal operation. It is available in an ultra thin, 12-Lead TMLP
Package.
Bottom View
X2QFN12 1.6x1.6, 0.4P
CASE 722AD
Features
• Fully Autonomous Type−C Controller Supports Type−C Versions 1.1
and 1.0
ORDERING INFORMATION
See detailed ordering and shipping information on page 2
of this data sheet.
• V Operating Range, 3.0 V − 5.5 V
DD
• Low Disable Power: I = 2.0 mA (Max.)
CC
• Low Standby Power: I = 7.0 mA (Max.)
CC
• DRP Mode with Optional Accessory Support
2
• Configurable I C Address
• Capable of Supporting Try.SNK and Try.SRC
• Dead Battery Support (SINK Support when No Power Applied)
• 2 kV HBM ESD Protection
• Small Packaging, 12 Lead TMLP (1.6 mm × 1.6 mm × 0.375 mm)
Applications
• Smartphones
• Tablets
• Notebooks
• Ultra Portable Applications
Figure 1. Typical Application
© Semiconductor Components Industries, LLC, 2015
1
Publication Order Number:
June, 2018 − Rev. 0
FUSB301A/D
FUSB301A
ORDERING INFORMATION
Operating
Temperature Range
†
Part Number
Top Mark
NX
Package
Packing Method
12−Lead Ultra−thin Molded
Leadless Package (TMLP)
1.6 mm × 1.6 mm × 0.375 mm
FUSB301A
−40 to 85°C
Tape and Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
BLOCK DIAGRAM
Figure 2. Block Diagram
PIN CONFIGURATION
Figure 3. Pin Assignment (Top Through View)
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2
FUSB301A
PIN DESCRIPTIONS
Pin #
Name
Type
Description
USB Type−C Connector Interface
1, 2
CC1, CC2
VBUS
I/O
Type−C Configuration Channel
4
Input
VBUS input pin for attach and detach detection
Ground
10
GND
Ground
Power Interface
12
VDD
Power
Input Supply Voltage
Signal Interface
2
2
8
7
SCL
SDA
Input
I C serial clock signal to be connected to the I C master
2
2
Open−Drain
I C serial data signal to be connected to the I C master
I/O
6
9
5
INT_N
ID
Open−Drain
Active LOW open drain interrupt output used to prompt the processor
2
Output
to read the I C register bits
Open−Drain
Output
Used to Identify if connected device is Source or Sink. The ID Pin
can be used to interface with USB 2.0 Input on the processor.
I2CADDR
Input
Used to change bit 3 of the I2C address so that multiple addresses
can be used in a system where two device addresses conflict
3
NC1
NC2
NC
NC
No Connect − Tie to Ground or Float
No Connect − Tie to Ground or Float
11
Dead Battery
in a high impedance state by default after power−up or
device reset, and the global interrupt mask (INT_MASK in
Control register) is set. After INT_MASK bit is cleared by
the local processor, the INT_N pin stays high impedance in
preparation of future interrupts. When an interruptible event
occurs, INT_N is driven LOW and is in a high impedance
state again when the processor clears the interrupt by reading
the interrupt registers. Subsequent to the initial power up or
reset; if the processor writes a “1” to global interrupt mask
bit when the system is already powered up, the INT_N pin
stays in a high impedance state and ignores all interrupts
until the global interrupt mask bit is cleared. If an event
happens that would ordinarily cause an interrupt when the
global interrupt mask bit is set, the INT_N pin goes LOW
when the global interrupt mask is cleared.
If power is not applied to FUSB301A and it is attached to
a Source device, then the Source would pull up the CC line
connected through the cable. The FUSB301A in response
would turn on the pull−down that will bring the CC voltage
to a range that the Source can detect an attach and turn on
VBUS.
Power Up, Initialization and Reset, Interrupt Operation
When power is first applied, the FUSB301A will power
up in Sink mode with all interrupts masked. The local
processor must configure the FUSB301A to the desired
mode and clear the global interrupt mask bit, INT_MASK.
The INT_N pin is an active low, open drain output. This pin
indicates to the host processor that an interrupt has occurred
in the FUSB301A which needs attention. The INT_N pin is
Table 1. ID PIN TRUTH TABLE
Type Register (h12, bit 4)
Description
SINK Not Detected
SINK Detected
ID
Hi−Z (default)
Low
SINK = b0
SINK = b1
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Min.
−0.5
−0.5
−0.5
−65
Max.
6.0
Unit
V
V
Supply Voltage from V
VBUS Supply Voltage
DD
DD
V
28
V
BUS
CC_HDDRP
V
CC pins when configured as Host, Device or Dual Role Port
Storage Temperature Range
6.0
V
T
+150
°C
STORAGE
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3
FUSB301A
ABSOLUTE MAXIMUM RATINGS (continued)
Symbol
Parameter
Maximum Junction Temperature
Min.
Max.
+150
+260
Unit
°C
T
J
T
L
Lead Temperature (Soldering, 10 seconds)
°C
ESD
IEC 6100−4−2 System ESD
Connector
Pins (VBUS,
CC1 and CC2)
Air Gap
Contact
15
8
kV
Human Body Model, JEDEC JESD22−A114
Connector Pins (VBUS,
CC1 and CC2)
4
Others
2
1
Charged Device Model, JEDEC
LESD22−C101
All Pins
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
RECOMMENDED OPERAING CONDITIONS
Symbol
Parameter
Min.
Typ.
5.0
Max.
21
Unit
V
V
BUS
VBUS Supply Voltage
Supply Voltage
3.7
(1)
V
DD
2.8
−40
3.3
5.5
V
T
A
Operating Temperature
+85
°C
1. This is for functional operation only and isn’t the lowest limit for all subsequent electrical specifications below. All electrical parameters have
a minimum of 3 V operation.
DC AND TRANSIENT CHARACTERISTICS
Unless otherwise specified: Recommended T and T temperature ranges. All typical values are at T = 25°C and V = 3.3 V unless
A
J
A
DD
otherwise specified.
T
= −40 to +855C
A
T = −40 to +1255C
J
Min.
Typ.
Max.
Symbol
Parameter
Unit
Type C Specific Parameters
I
Source 80 mA CC Current (Default) HOST_CUR1 = 0,
64
80
96
194
356
2.18
5.6
mA
mA
mA
V
80_CCX
HOST_CUR0 = 1
I
Source 180 mA CC Current (1.5 A) HOST_CUR1 = 1,
HOST_CUR0 = 0
166
304
180
330
180_CCX
330_CCX
I
Source 330 mA CC Current (3 A) HOST_CUR1 = 1,
HOST_CUR0 = 1
V
Sink Pull−Down Voltage in Dead Battery Under all Pull−up
SOURCE Loads
SNKDB
DEVICE
R
Sink Pull−Down Resistance when V is within Operating
4.6
5.1
kW
DD
Range
zOPEN
CC Resistance for Disabled State
126
kW
vRa−SRCdef
Ra Detection Threshold for CC Pin for Source for Default
Current on VBUS
0.15
0.20
0.40
0.80
1.60
1.60
0.25
0.45
0.85
1.65
1.65
V
vRa−SRC1.5A
vRa−SRC3A
vRd−SRCdef
vRd−SRC1.5A
Ra Detection Threshold for CC Pin for Source for 1.5 A
Current on VBUS
0.35
0.75
1.50
1.50
V
V
V
V
Ra Detection Threshold for CC Pin for Source for 3 A
Current on VBUS
Rd Detection Threshold for Source for Default Current
(HOST_CUR1/0 = 01)
Rd Detection Threshold for Source for 1.5 A Current
(HOST_CUR1/0 = 10)
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4
FUSB301A
DC AND TRANSIENT CHARACTERISTICS
Unless otherwise specified: Recommended T and T temperature ranges. All typical values are at T = 25°C and V = 3.3 V unless
A
J
A
DD
otherwise specified. (continued)
T
= −40 to +855C
A
T = −40 to +1255C
J
Min.
Typ.
Max.
Symbol
Parameter
Unit
vRd−SRC3A
Rd Detection Threshold for Source for 3 A Current
(HOST_CUR1/0 = 11)
2.45
2.60
2.75
V
vRa−SNK
vRd−def
Ra Detection Threshold for CC Pin for Sink
0.15
0.61
1.16
2.04
0.20
0.66
1.23
2.11
0.25
0.70
1.31
2.18
3.7
V
V
V
V
V
Rd Default Current Detection Threshold for Sink
Rd 1.5 A Current Detection Threshold for Sink
Rd 3 A Current Detection Threshold for Sink
VBUS Threshold at which I_VBUSOK Interrupt is Triggered
vRd−1.5A
vRd−3.0A
vVBUSthr
CURRENT CONSUMPTION
T
= −40 to +855C
A
T = −40 to +1255C
J
Unit
Min.
Typ.
0.35
3.5
5
Max.
Unit
mA
Symbol
Idisable
Istby
Parameter
V
(V)
Conditions
Disabled State
Nothing attached
DD
Disabled Current
Unattached Sink
3.0 to 5.5
3.0 to 5.5
2.0
7.0
20
mA
Unattached Sink + Acc,
Source + Acc, or DRP
Nothing attached, Internally
Toggling
mA
Iattach
Attach Current (Less Host
Current)
3.0 to 5.5
Attached as a Sink
5
15
15
mA
mA
Attached as a Source
10
TIMING PARAMETERS
T
= −40 to +855C
A
T = −40 to +1255C
J
Unit
Unit
ms
Min.
Typ.
150
75
Max.
Symbol
Parameter
tCCDebounce
Debounce Time for CC (Source or Accessory)
Debounce Time for CC (Sink)
100
63
200
87
ms
tPDDebounce
tAccDetect
Debounce Time for CC Detach Detection
10
15
20
ms
Debounce Time to Detect AudioAccessory, or DebugAccessory is At-
tached
50
100
200
ms
tErrorRecovery
tVBUSondeb
tVBUSoffdeb
tDRPToggle1
Time staying in the ErrorRecovery State if sent there via the
ERROR_REC bit or by a change of Modes
25
0.167
10
50
0.200
15
100
0.375
20
ms
ms
ms
ms
Debounce Time of VBUS Detection when acting as a Sink to Signal VBUS
is present
Debounce Time of VBUS Detection when acting as a Sink to Signal VBUS
has been removed
For DRP Operation, Time Spent in Unat-
tached.Sink before going to Unattached.Source
State
DRPROGGLE = 00
DRPROGGLE = 01
DRPROGGLE = 10
DRPROGGLE = 11
35
30
25
20
70
60
50
40
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FUSB301A
TIMING PARAMETERS
Symbol
T
= −40 to +855C
A
T = −40 to +1255C
Unit
Unit
ms
J
Min.
Typ.
Max.
Parameter
tDRPToggle2
For DRP Operation, Time Spent in Unat-
tached.Source before going to Unattached.Sink
State
DRPROGGLE = 00
DRPROGGLE = 01
DRPROGGLE = 10
DRPROGGLE = 11
15
20
25
30
30
40
50
60
IO SPECIFICATIONS
T
= −40 to +855C
A
T = −40 to +1255C
J
Unit
Unit
Min.
Typ.
Max.
Symbol
Parameter
V
DD
(V)
Conditions
Host Interface Pins (ID)
V
OLID
Output Low Voltage
3.0 to 5.5
I = 4 mA
OL
0.4
V
Host Interface Pins (I2CADDR)
V
Low−Level Input Voltage
High−Level Input Voltage
3.0 to 5.5
3.0 to 5.5
0.3V
V
V
ILADDR
DD
V
0.7V
DD
IHADDR
Host Interface Pins (INT_N)
Output Low Voltage
I C Interface Pins − Fast Mode SDA, SCL
V
3.0 to 5.5
I = 4 mA
OL
0.4
0.4
V
OLINTN
2
V
Low−Level Input Voltage
High−Level Input Voltage
3.0 to 5.5
3.0 to 5.5
3.0 to 5.5
V
V
V
ILI2C
IHI2C
V
1.2
0.2
V
HYS
Hysteresis of Schmitt Trigger In-
puts
I
Input Current of SDA and SCL Pins
3.0 to 5.5
3.0 to 5.5
3.0 to 5.5
3.0 to 5.5
Input Voltage
0.26 V to 2 V
−10
10
10
0.3
10
mA
mA
V
I2C
I
VDD Current when SDA and SCL
are HIGH
Input Voltage
1.8 V
CCTI2C
V
Low−Level Output Voltage at 3 mA
Sink Current (Open−Drain)
0
OLSDA
(2)
C
Capacitance for Each I/O Pin
pF
I
2. Guaranteed by characterization. Not production tested.
FAST MODE I2C SPECIFICATIONS (Note 3)(see Figure 4)
Fast Mode
Min.
Max.
Symbol
Parameter
I2C_SCL Clock Frequency
Unit
f
0
400
kHz
ms
ms
ms
ms
ms
ns
ns
ns
SCL
t
Hold Time (Repeated) START Condition
LOW Period of I2C_SCL Clock
HIGH Period of I2C_SCL Clock
Set−up Time for Repeated START Condition
Data Hold Time
0.6
1.3
0.6
0.6
0
HD;STA
t
LOW
t
HIGH
t
SU;STA
HD;DAT
t
0.9
t
Data Set−up Time
(Note 4)
100
SU;DAT
t
r
Rise Time of I2C_SDA and I2C_SCL Signals
Fall Time of I2C_SDA and I2C_SCL Signals
(Note 5) 20*(V /5.5V)
250
250
DD
t
f
(Note 5) 20*(V /5.5V)
DD
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FUSB301A
FAST MODE I2C SPECIFICATIONS (Note 3)(see Figure 4) (continued)
Fast Mode
Min.
0.6
1.3
0
Max.
Symbol
Parameter
Set−up Time for STOP Condition
Unit
ms
t
SU;STO
t
BUS−Free Time between STOP and START Conditions
ms
BUF
t
SP
Pulse Width of Spikes that Must Be Suppressed by the Input
Filter
50
ns
3. Guaranteed by characterization. Not production tested.
2
2
4. A fast−mode I C bus device can be used in a standard−mode I C bus system, but the requirement t
≥ 250 ns must be met. This is
SU;DAT
automatically the case of the device does not stretch the LOW period of the I2C_SCL signal. If such a device does stretch the LOW period
I2C_SCL signal, it must output the next data bit to the I2C_SDA line tr_max + t
= 1000 + 250 = 1250 ns (according to the standard−mode
SU;DAT
2
I C bus specification) before the I2C_SCL line is released.
2
5. Cb equals the total capacitance of one bus line in pF. If mixed with high−speed devices, faster fall times are allowed according to the I C
specification.
Figure 4. Definition of Timing for Full−Speed Mode Devices on the I2C Bus
2
I C INTERFACE
The FUSB301A includes a full I C slave controller. The
requirements. This block is designed for fast mode.
Examples of an I C write and read sequence are shown
Figure 5 and Figure 6 respectively.
2
2
2
2
I C slave fully complies with the I C specification version 6
NOTE: Single Byte read is initiated by Master with P immediately following first data byte.
Figure 5. I2C Write Example
Register address to Read specified
Single or multi byte read executed from current register location (Single Byte read
is initiated by Master with NA immediately following first data byte)
NOTE: If Register is not specified Master will begin read from current register. In this case only sequence showing in Red bracket
is needed.
Figure 6. I2C Read Example
2
I C ADDRESS
The I2CADDR bit high or low is indicated in bit3 of the
slave address shown in Table 2.
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FUSB301A
Table 2. FUSB301A I2C SLAVE ADDRESS
Name
Size (Bits)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Slave Address
8
0
1
0
0
I2CADDR
0
1
R/W
REGISTER DEFINITIONS
Table 3. REGISTER MAP
Register
RST
Val
Name
Device ID
Modes
Address
0×01
Type
RO
R/W
R/W
W/C
W/C
X
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
12
04
03
00
00
xx
00
00
00
00
xx
Version ID [3:0]
DRP+ACC
Revision ID [3:0]
0×02
DRP
Sink+ACC
UNATT_SNK
Sink
Source+ACC
HOST_CUR0
DISABLED
Source
INT_MASK
ERROR_REC
SW_RES
0×03
Control
Manual
Reset
DRPTOGGLE
HOST_CUR1
UNATT_SRC
0×04
0×05
0×06−0×0F
0×10
Reserved
Mask
Do Not Use
M_ACC_CH
R/W
RO
RO
R/C
X
M_BC_LVL
BC_LVL1
M_DETACH
BC_LVL0
M_ATTACH
ATTACH
0×11
Status
ORIENT1
ORIENT0
Sink
VBUSOK
Source
DEBUGACC
I_DETACH
AUDIOACC
I_ATTACH
0×12
Type
I_ACC_CH
Do Not Use
I_BC_LVL
0×13
Interrupt
Reserved
0×14−0×1F
6. Do not use registers that are blank.
7. Values read from undefined register bits are invalid. Do not write to undefined registers.
Table 4. DEVICE ID
Address: 01h
Reset Value: 0×0001_0010
Type: Read Only
Bit #
Name
Size (Bits)
Description
7:4
Version ID
4
Device version ID by Trim or etc.
A_[Version ID]: 0001 (FUSB301ATMX)
3:0
Revision ID
4
Revision History of each version
[Revision ID]_revC: 0010
Table 5. MODES
Address: 02h
Reset Value: 0×0000_0100
Type: Read/Write
Bit #
Name
Size (Bits)
Description
7:6
5
Reserved
DRP+ACC
DRP
2
1
1
1
1
1
1
Do Not Use
1: Configure device as a Dual Role Port (DRP) with accessory support
1: Configure device as a Dual Role Port (DRP) without accessory support
1: Configure device as a Sink with accessory support
4
3
Sink+ACC
Sink
2
1: Configure device as a Sink without accessory support
1: Configure device as a Source with accessory support
1
Source+ACC
Source
0
1: Configure device as a Source without accessory support
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FUSB301A
Table 6. CONTROL
Address: 03h
Reset Value: 0×XX00_X011
Type: Read/Write
Bit #
7:6
Name
Size (Bits)
Description
Reserved
2
2
Do Not Use
5:4
DRPTOGGLE
Selects different timing for Dual Role Port Toggle between Unattached. Sink
State and Unattached.SOURCE State.
00: 35 ms min. in Unattached.Sink and 15 ms min. In Unattached.-
SOURCE
01: 30 ms min. In Unattached.Sink and 20 ms min. In Unattached.SOURCE
10: 25 ms min. In Unattached.Sink and 25 ms min. In Unattached.SOURCE
11: 20 ms min. In Unattached.Sink and 30 ms min. In Unattached.SOURCE
3
Reserved
1
2
Do Not Use
2:1
HOST_CUR
[1:0]
1: Controls the pull−up current when device enabled as a Source
00: No Current
01: 80 mA − Default USB Power
10: 180 mA − Medium Current Mode: 1.5 A
11: 330 mA − High Current Mode: 3 A
0
INT_MASK
1
1: Global interrupt mask to mask all interrupts
Table 7. MANUAL(Note 8)
Address: 04h
Reset Value: 0×XXXX_0000
Type: Write/Clear
Bit #
7:4
3
Name
Size (Bits)
Description
Do Not Use
Reserved
4
1
UNATT_SINK
(Note 9)
1: Put device in Unattached.Sink state as defined in the Type C spec
2
1
UNATT_SOURCE
1
1
1: Put device in Unattached.Source state as defined in the Type C spec
1: Put device in Disabled state as defined in the Type C spec
DISABLED
(Note 10)
0
ERROR_REC
1
1: Put device in ErrorRecovery state as defined in the Type C spec
st
nd
rd
8. If more than one bit is set to ‘‘b1‘‘ simultaneously then an order of priority will be used. 1 priority is DISABLED, 2 is ERROR_REC, 3
is UNATT_SOURCE, last is UNATT_SINK. The highest priority bit will take precedence and all other bits will be cleared automatically.
9. Wait 2 ms between Modes = Sink and Manual = UNATT_SINK writes.
10.The DISABLED bit must be manually cleared.
Table 8. RESET
Address: 05h
Reset Value: 0×XXXX_XXX0
Type: Write/Clear
Bit #
7:6
0
Name
Size (Bits)
Description
Reserved
SW_RES
7
1
Do Not Use
1: Reset the system and I2C Register.
Table 9. MASK
Address: 10h
Reset Value: 0×XXXX_0000
Type: Read/Write
Bit #
7:4
3
Name
Size (Bits)
Description
Reserved
4
1
Do Not Use
M_ACC_CH
1: Mask a change from Accessory Present to Attached Accessory
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FUSB301A
Table 9. MASK (continued)
Address: 10h
Reset Value: 0×XXXX_0000
Type: Read/Write
Bit #
Name
Size (Bits)
Description
2
1
0
M_BC_LVL
M_DETACH
M_ATTACH
1
1
1
1: Mask a change in I_BC_LVL interrupt bit
1: Mask the I_DETACH interrupt bit
1: Mask a change in the I_ATTACH interrupt bit
Table 10. STATUS
Address: 11h
Reset Value: 0×XX00_0000
Type: Read
Bit #
7:6
Name
Size (Bits)
Description
Reserved
2
2
Do Not Use
5:4
ORIENT[1:0]
Status to indicate which CCx pins has the CC cable connection
11: A fault has occurred during the detection
10: Cable CC is connected through the CC2 pin
01: Cable CC is connected through the CC1 pin
00: No or unresolved connection detected.
3
VBUSOK
1
2
1: Status to indicate VBUS is in the valid range
2:1
BC_LVL[1:0]
Thresholds that allow detection of current advertisement on CC line
00: Ra or unattached Sink
01: Rd threshold for Sink default current advertisement
10: RD threshold for Sink 1.5 A current advertisement
11: RD threshold for Sink 3 A current advertisement
0
ATTACH
1
1: Attached to a device or accessory of a type shown in the Type register
Table 11. TYPE
Address: 12h
Reset Value: 0×XXX0_0X00
Type: Read
Bit #
Name
Size (Bits)
Description
Do Not Use
7:5
4
Reserved
Sink
3
1
1
1
1
1
1: Indicates a Sink has been detected
1: Indicates a Source has been detected
Do Not Use
3
Source
2
Reserved
DEBUGACC
AUDIOACC
1
1: Indicates a Debug Accessory has been detected
1: Indicates a Audio Accessory has been detected
0
Table 12. INTERRUPT0
Address: 13h
Reset Value: 0×XXXX_X000
Type: Write/Clear
Bit #
7:4
3
Name
Size (Bits)
Description
Reserved
4
1
Do Not Use
I_ACC_CH
1: Interrupt flagged when a change from Accessory Present to Audio Ac-
cessory or Debug Accessory occurs.
2
I_BC_LVL
1
1: Interrupt flagged when a change in BC_LVL advertised current level has
occurred
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10
FUSB301A
Table 12. INTERRUPT0 (continued)
Address: 13h
Reset Value: 0×XXXX_X000
Type: Write/Clear
Bit #
Name
Size (Bits)
Description
1
0
I_DETACH
I_ATTACH
1
1
1: Interrupt flagged when a device or accessory has been detached
1: Interrupt flagged when a device or accessory of type indicated in the
Type register has been attached
2
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
X2QFN12 1.6x1.6, 0.4P
CASE 722AD
ISSUE O
DATE 31 OCT 2016
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