FUSB3307D6A0BFMX_技术文档

USB Power Delivery 3.0

Adaptive Source Charging

Controller

FUSB3307

FUSB3307 is a highly integrated USB Power Delivery (PD) power

source controller that can control a DC−DC port power regulator or the

opto−coupler in the secondary side of an AC−DC adapter. It

implements the Source finite state machines of USB Power Delivery

3.0 (PD 3.0) and Type−C™ which includes Programmable Power

Supplies (PPS). In order to meet the PPS specification, FUSB3307

supports minimum 3.3 V and maximum 21 V output voltage control.

It includes Constant Voltage (CV) and Constant Current Limit (CL)

control blocks. The references are supported from internal D/A

converters.

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14

1

SOIC−14 NB

CASE 751A−03

QFNW20 4x4, 0.5P

CASE 484AT

(In Development)

FUSB3307 supports various protections, Under Voltage Protection

(UVP), Over Voltage Protection(OVP), Over Current Protection

(OCP), CC1 and CC2 Over Voltage Protection (CC_OVP), VCONN

Over Current Protection (VCONN_OCP), and internal and external

Over Temperature protection (I_OTP and E_OTP). With a 10−bit A/D

converter, output voltage, output current, IC internal temperature and

external temperature via an NTC resistor can be monitored.

FUSB3307 is capable of controlling a single or back−to−back

N−Channel MOSFETs as a load switch, which results in a lower cost

and easier design.

GENERIC MARKING DIAGRAMS

14

3307

FUSB3307D6MX

AWLYWW

D6x

ALYWG

G

1

FUSB3307D6MX = Specific Device Code

= Assembly Location

WL, L = Wafer Lot

= Year

WW, W = Work Week

A

Y

Features

G

= Pb−Free Package

• PD 3.0 v2.0 and Type−C 2.0 Compliant

(Note: Microdot may be in either location)

• Constant Voltage (CV) and Constant Current Limit (CL) Regulation

• Small Current Sensing Resistor (5 mW) for High Efficiency

• Gate Driver for N−Channel MOSFET as a Load Switch

• CC1/CC2 Pin Protection up to 26 V

PIN DESCRIPTION

See detailed pin description information on page 5 of this

data sheet.

• Selectable Resistor Divider or Battery Charging (BC1.2) Modes

• Built−in Output Capacitor Discharging Resistance

• Adaptive UVP, Adaptive OVP, I_OTP, E_OTP, CC_OVP and

VCONN_OCP Fault Detection

ORDERING INFORMATION

See detailed ordering and shipping information on page 5 of

this data sheet.

• 14−pin SOIC and 20−pin QFN Packages Available

Applications

• Wall Chargers for Tablet PC’s and Laptop Batteries

• AC−DC PD 3.0 Compliant Adapters

• DC−DC Car Chargers for Individual Port Power Control

This document contains information on some products that are still under development.

ON Semiconductor reserves the right to change or discontinue these products without

notice.

1

Publication Order Number:

July, 2020 − Rev. 0

FUSB3307/D

FUSB3307

APPLICATION DIAGRAM

Figure 1. Offline Application Diagram

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2

FUSB3307

Figure 2. Automotive Application Diagram

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3

FUSB3307

VDD

VCC GATE DISC

D+/PDIV1 D−/PDIV0

vdd

PDIV1

PDIV0

GND

Resistor

Divider / BC 1.2

Option

Gate Driver

vdd

9R

R

V

/

IN−ON

Discharge

FAULT

IN−OFF

CC1

CC2

V

CS−AMP

Trigger

_BLD

RESET

Protection

vdd

CC State Machine &

Comparators

vdd

1.1V REG

IFB

IS+

X A

VCCR

R c v r

B M C

V

CS−AMP

Policy

Engine

IS−

VCCR

vdd

BMC

Cable Drop

Compensation

Option

DRIVER

(+Timers)

Protection

PDIV0

CRC32

Tx

VFB

V

COMR

BMC

S

4B5B

FAULT

Encode

CDR

Device

Protocol

VCVR

Protection

Block

Policy

(+Timers)

PDIV1

Manager

OVP/UVP/

OCP

BMC

(DPM)

Decode

V

PDIV2

IN−1:10

State

Machine

CRC32

Rx

V

vdd

V

COMR

FAULT

CS−AMP

Protection

V

CS−AMP

Band

Gap

Analog to Digital

Converter

NTC

LF

Osc.

IN−1:10

PD

Trim

Osc.

Internal temp.

CATH

Figure 3. Block Diagram

VCC

GND

GATE

VDD

1

2

3

4

5

6

7

14 CATH

20 19 18 17 16

DISC

IFB

13

12

11

10

9

1

2

3

4

5

N/C

D−/PDIV0

CC1

15

GND

VCC

N/C

FUSB3307

QFN

14

13

FUSB3307

SOIC

VFB

GND

IS−

D+/PDIV1

D−/PDIV0

CC1

GND

12 CATH

Top View

CC2

11

DISC

IS+

CC2

10

6

7

8

9

8

Top View

14

13

12

11

10

9

1

2

3

4

5

6

7

VCC

CATH

DISC

IFB

16 17 18 19 20

GND

1

2

3

4

5

15

14

13

N/C

GND

VCC

N/C

FUSB3307

QFN

GATE

VDD

D−/PDIV0

FUSB3307

SOIC

VFB

IS−

CC1

GND

CC2

GND

D+/PDIV1

CATH 12

11

Bottom View

DISC

IS+

D−/PDIV0

10

9

8

7

6

CC1

8

CC2

Bottom View

Figure 4. Pin Diagrams

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4

FUSB3307

PIN FUNCTION DESCRIPTION

SOIC Pin

Number

QFN Pin

Number

Pin Name

I/O Type

Description

1

14

VCC

Supply

Output voltage (Input voltage to the FUSB3307). This pin is tied to the output of

the power source to monitor its output voltage and supply internal bias to the

FUSB3307 via the VDD pin.

4

2

19

VDD

GND

CATH

Supply

Ground

Internal supply voltage regulator output. This pin should be connected to an 1 mF

external capacitor

4, 15,

DAP

Ground

14

12

Open Drain Feedback to control the power supply. Typically an opto−coupler cathode on the

Output

secondary side is connected to this pin to provide feedback signal to the primary

side PWM controller. Alternatively, this can be connected to the error amplifier

output of a DC−DC regulator (often called the compensation pin) or with an invert-

ing circuit to the DC−DC feedback (FB) pin.

11

12

8

9

VFB

IFB

Input

Output Voltage Sensing Signal. This pin is used for constant voltage (CV) regula-

tion, and it is tied to the internal CV loop amplifier non−inverting input terminal. It

is tied to the output voltage external 1:10 resistor divider and a compensation

circuit

Input

Constant Current Amplifying Signal. The voltage level at this pin is the amplified

current sense signal used for providing an external compensation circuit. Internal-

ly this pin is tied to the non−inverting input of the current loop error amplifier.

10

9

7

6

IS−

Input

Current sensing amplifier negative terminal. Connect this pin directly to the nega-

tive end of the current sense resistor with a short PCB trace

IS+

Current sensing amplifier positive terminal. Connect this pin directly to the posi-

tive end of the current sense resistor with a short PCB trace

3

17

11

GATE

DISC

Output

Gate drive signal to drive the gate of an NFET load switch

13

Open Drain Discharge pin. This pin should be tied to a small (40 W) external resistor that is

I/O

connected to VBUS after the load switch to discharge VBUS at the connector

7

8

5

3

5

CC1

CC2

I/O

Configuration Channel 1. This pin is used to detect USB Type−C devices and

communicate over USB PD

I/O

Configuration Channel 2. This pin is used to detect USB Type−C devices and

communicate over USB PD

20

D+/PDIV1

D+: I/O

Different functionality available with Trim option (see Application Information

PDIV1: Input section and note at the bottom of Table 6 below):

D+: Connected to D+ for BC1.2 or resistor divider mode

PDIV1: Programmable pin to select different USB Power Delivery Power (PDP)

values

6

2

D−/PDIV0

D−: I/O

Different functionality available upon request:

PDIV0: Input D−: Connected to D− for BC1.2 or resistor divider mode

PDIV0: Programmable pin to select different USB Power Delivery Power (PDP)

values

N/A

10

16

PDIV2

NTC

Input

I/O

Programmable pin to select different USB Power Delivery Power (PDP) values

Pin connected to external NTC resistor to sense PCB or connector temperature

ORDERING INFORMATION

Part Number

Top Mark

Operating Temperature Range

Package

Packing Method

FUSB3307D6MX

−40°C to 85°C

SOIC−14 NB

(Pb−Free)

Tape and Reel

FUSB3307D6VMNWTWG

(In Development)

3307

D6V

−40°C to 105°C

−40°C to 85°C

QFNW20

(Pb−Free)

Tape and Reel

FUSB3307D6MNWTWG

(In Development)

3307

D6

QFNW20

(Pb−Free)

Other trim (see note at the

bottom of Table 6) or

package options

Please contact

ON Semiconductor sales

−

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5

FUSB3307

Table 1. MAXIMUM RATINGS (Notes 1, 2)

Rating

Symbol

Value

−0.3 to 26

−0.3 to 30

−0.3 to 6

1.5

Unit

V

VCC, CATH, DISC, CC1, CC2 Pin Voltage

GATE Pin Voltage

V

CC

V

GATE

V

IFB, VFB, IS+, IS−, NTC, D+/PDIV1, D−/PDIV0, PDIV2 Pin Voltage

V

I/O

DD

VDD Pin Voltage

V

Power Dissipation (T = 25°C)

P

D

W

°C

kV

A

Operating Junction Temperature

T

J

−40 to 150

260

Storage Temperature Range

T

STG

Lead Temperature, (Soldering, 10 Seconds)

Human Body Model, ANSI/ESDA/JEDEC JS−001−2012 (Note 3)

Charged Device Model, JESD22−C101 (Note 3)

TL

ESD

2

HBM

CDM

ESD

0.5

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. All voltage values, except differential voltages, are given with respect to the GND pin.

2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.

3. Meets JEDEC standards JS−001−2012 and JESD 22−C101.

Table 2. THERMAL CHARACTERISTICS (Note 4)

Rating

Symbol

Value

Unit

R

Thermal Characteristics,

Thermal Resistance, Junction−to−Air, SOIC14

Thermal Reference, Junction−to−Top, SOIC14

Thermal Resistance, Junction−to−Air, QFNW20

Thermal Reference, Junction−to−Top, QFNW20

75

q

JA

JT

JA

JT

R

41.6

36.1

2.3

q

°C/W

R

q

4. T =25°C unless otherwise specified with JEDEC 2S2P board with no thermal vias.

A

Table 3. RECOMMENDED OPERATING RANGES

Rating

Symbol

Min

Max

Unit

V

Input Voltage

V

CC

3.3 − 5%

21 + 5%

5

Output Current Through Load Switch

Adjustable Type−C Connector VBUS Output Voltage

Ambient Temperature

I

A

OUT

VBUS

3.3 − 5%

−40

21 + 5%

V

T

A

85 (Commercial)

105 (Automotive)

°C

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

Table 4. ELECTRICAL CHARACTERISTICS V = 5 V, T = −40°C to 125°C unless otherwise specified.

CC

J

Parameter

Test Conditions

Symbol

Min

Typ

Max

Unit

VDD SECTION

VDD Operating Voltage at VCC = 20 V

VDD Source Current

V

= 20 V, I

= 0 mA

V

4.75

10

5.2

5.5

V

CC

VDD

DD

= 3.3 V, V = 2.9 V

I

mA

CC

DD

VCC SECTION

Continuous Operating Voltage (Note 5)

Operating Supply Current at 5 V

V

21 + 5%

V

CC−OP

V

= 5 V, sense resistor voltage dif-

I

2.4

mA

CC

CC−OP−5V

ference (V ) = 25 mV, sense resistor

CS

(R ) = 5 mW

CS

Operating Supply Current at 20 V

Turn−On Threshold Voltage

Turn−Off Threshold Voltage

Turn−Off to Turn−On Hysteresis

V

CC

V

CC

V

CC

V

CC

= 20 V, V = 25 mV, Rcs = 5 mW

I

CC−OP−20V

3.1

3.2

mA

V

CS

increasing

V

2.9

2.80

100

3.4

3.10

360

CC−ON

decreasing after V w V

V

2.87

260

V

CC

CC−ON

CC−OFF

CC−OFF_HYS

V

decreasing after V w V

mV

CC

CC−ON

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FUSB3307

Table 4. ELECTRICAL CHARACTERISTICS V = 5 V, T = −40°C to 125°C unless otherwise specified.

CC

J

Parameter

Test Conditions

Symbol

Min

Typ

Max

Unit

VCC SECTION

Standby Operating Supply Current

V

= 5 V, V = 0 mV (I

P−CC2−330

I

0.85

1.1

mA

CC

CS

P−CC1−330

CC−STBY

and I

not flowing since CC1

and CC2 are HIGH)

VCC−UVP SECTION

Ratio V Under−Voltage−Protection (UVP)

V

CS

= 0 mV

K

CC−UVP

60

65

70

%

CC

to V

CC

UVP Debounce Time

t

45

60

75

ms

D−UVP

UVP Blanking Time during a Voltage Tran- Whenever a voltage change occurs

sition

t

160

200

240

BNK−UVP

from lower VBUS to a higher VBUS

VCC−OVP SECTION

Ratio V Over−Voltage−Protection (OVP)

V

CS

= 0 mV

K

CC- OVP

116.0

121

127.0

%

CC

to V

CC

V

Maximum Over−Voltage−Protection

23

35

23.8

75

7

24.8

110

V

CC−OVP−MAX

CC

OVP Debounce Time

t

ms

D−OVP

OVP Blanking Time during a Voltage Tran- VBUS voltage transition step (V

sition (Note 5)

)

t

STEP

BNK−OVP1

BNK−OVP2

BNK−OVP3

BNK−OVP4

v 0.5 V, Final VBUS > 13 V

OVP Blanking Time during a Voltage Tran-

sition (Note 5)

V

STEP

V

STEP

V

STEP

v 0.5 V, Final VBUS < 13 V

19

56

ms

OVP Blanking Time during a Voltage Tran-

sition (Note 5)

> 0.5 V, Final VBUS > 13 V

> 0.5 V, Final VBUS < 13 V

OVP Blanking Time during a Voltage Tran-

sition (Note 5)

221

CONSTANT CURRENT LIMIT SENSING SECTION (100% Constant Current)

Current−Sense Amplifier Gain (Note 5)

R

= 5 mW

A

40

V/V

A

CS

V−CCR

Current threshold on sensing resistor be-

Constant Current Limit mode and

V = 5 V, 20 V

CC

I

0.85

1.85

2.85

3.80

4.75

48

1.00

1.15

2.15

3.15

4.20

5.25

52

CS−1A

CS−2A

CS−3A

CS−4A

CS−5A

tween IS+ and IS− at I

= 1.00 A

OUT

Current threshold on sensing resistor be-

tween IS+ and IS− at I = 2.00 A

Constant Current Limit mode and

= 5 V, 20 V

2.00

3.00

4.00

5.00

50

A

V

CC

OUT

Current threshold on sensing resistor be-

tween IS+ and IS− at I = 3.00 A

Constant Current Limit mode and

= 5 V, 20 V

V

CC

OUT

Current threshold on sensing resistor be-

tween IS+ and IS− at I = 4.00 A

Constant Current Limit mode and

= 5 V, 20 V

A

V

CC

OUT

Current threshold on sensing resistor be-

tween IS+ and IS− at I = 5.00 A

Constant Current Limit mode and

= 5 V, 20 V

A

V

CC

OUT

Current threshold on sensing resistor be-

tween IS+ and IS− at DI = 50 mA

Constant Current Limit mode and

= 5 V

I

mA

CS−STEP

V

CC

OUT

OVER CURRENT PROTECTION SENSING SECTION

Over Current Protection (OCP) threshold on Constant Voltage mode, PD Request

I

3.42

5.7

50

3.60

6.0

3.78

6.3

70

A

CS−3A

sensing resistor between IS+ and IS− Message = 3 A and V = 5 V

CC

Over Current Protection (OCP) threshold on Constant Voltage mode, PD Request

CS−5A

sensing resistor between IS+ and IS−

Message = 5 A and V = 5 V

CC

OCP Debounce Time

t

60

ms

OCP−DEB

Current threshold on sensing resistor be-

tween IS+ and IS− for enabling discharge

on DISC pin during a voltage transition

VBUS is decreasing

I

330

mA

CS−EN−DSCG

Debounce time for enabling discharge on

DISC pin during a voltage transition

t

0.6

1.0

ms

V

CS−EN−DSCG

CONSTANT VOLTAGE SENSING SECTION

VFB Reference Voltage at 3.3 V

V

CC

= 3.3 V, V = 0 V

V

CVR−3.3V

0.320

0.330

0.340

CS

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FUSB3307

Table 4. ELECTRICAL CHARACTERISTICS V = 5 V, T = −40°C to 125°C unless otherwise specified.

CC

J

Parameter

Test Conditions

Symbol

Min

Typ

Max

Unit

CONSTANT VOLTAGE SENSING SECTION

VFB Reference Voltage at 5.0 V

(Power−on reset, default)

V

CC

= 5.0 V, V = 0 V

V

CVR−5.0V

0.485

0.500

0.515

V

CS

VFB Reference Voltage at 9 V

VFB Reference Voltage at 12 V

VFB Reference Voltage at 15 V

VFB Reference Voltage at 20 V

VFB Reference Voltage of 20 mV step

FEEDBACK SECTION

V

= 9 V, V = 0 V

V

0.873

1.164

1.455

1.940

0.900

1.200

1.500

2.000

0.927

1.236

1.545

2.060

V

CC

CS

CVR−9V

CVR−12V

CVR−15V

CVR−20V

= 12 V, V = 0 V

V

CS

= 15 V, V = 0 V

V

CS

= 20 V, V = 0 V

V

CS

V

CVR−STEP−20mV

DV = 20 mV, V = 0 V

mV

CC

CS

CATH Pin Sink Current (Note 5)

Minimum guaranteed sink current ex-

pected from CATH pin

I

2

mA

CATH−Sink

DISCHARGE SECTION

VBUS to GND leakage resistance when

VBUS is not being sourced

GATE = 0 V

R

72.4

170

250

155

kW

mA

DISC−BUS

I

VCC −Sink

VCC Pin Sink Current when discharging

(Note 5)

Discharging current on VCC after a

fault has triggered at VCC = 20 V

DISC Pin Sink Current when discharging

(Note 5)

Discharging current on DISC during a

voltage transition at VCC = 20 V,

I

DISC −Sink

I

< I

OUT

CS−EN−DSCG

Discharge Time (Note 5)

VBUS voltage transition step (V

)

t

7

ms

STEP

DISC1

v 0.5 V, Final VBUS > 13 V,

I

< I

CS−EN−DSCG

OUT

Discharge Time (Note 5)

V

v 0.5 V, Final VBUS < 13 V,

< I

CS−EN−DSCG

t

19

56

ms

STEP

OUT

DISC2

DISC3

DISC4

I

V

> 0.5 V, Final VBUS > 13 V,

STEP

OUT

I

< I

CS−EN−DSCG

V

> 0.5 V, Final VBUS < 13 V,

221

STEP

OUT

I

< I

CS−EN−DSCG

OVER TEMPERATURE PROTECTION SECTION

Current Source on NTC pin (Note 6)

Resistance to ground on NTC =

3.293 kW

I

55

60

90

65

mA

ms

°C

NTC

Debounce time for External Over Tempera-

ture Protection (E_OTP) (Note 6)

t

NTC−DEB

Internal Die Warning Temperature Thresh-

old (Note 5)

T

125

135

I_WARN

Internal Die Over−Temperature Threshold

(Note 5)

T

I_OTP

PROTECTION RECOVERY SECTION

VCC Voltage Release Threshold

UVP fault causing release when VCC

< V

V

LATCH

0.9

1.8

LATCH

Duration for Disabling Load Switch When

Fault Removed in Normal Mode (Note 5)

After fault OVP, UVP, OCP, E_OTP,

I_OTP or CC_OVP has recovered

t

2

2.2

0.4

sec

ms

2S_AR_NM

2S_SR_DM

Duration for Disabling Load Switch When

Fault Removed in Debug Test Mode

100

INPUTS SECTION

PDIV2, PDIV1 and PDIV0 input LOW volt-

age

Input LOW

V

IL

V

− 0.4

PDIV2, PDIV1 and PDIV0 input HIGH volt- Input HIGH

age

DD

IH

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8

FUSB3307

Table 4. ELECTRICAL CHARACTERISTICS V = 5 V, T = −40°C to 125°C unless otherwise specified.

CC

J

Parameter

TYPE C SECTION

Test Conditions

Symbol

Min

Typ

Max

Unit

330 mA Source Current on CC1 Pin

180 mA Source Current on CC1 Pin

V

= 5 V, V

= 0 V

I

304

166

330

180

356

194

mA

CC

CC1

P−CC1−330

Used for USB PD to signal that the

Sink can communicate, V = 5 V,

P−CC1−180

CC

V

CC1

= 0 V

330 mA Source Current on CC2 Pin

180 mA source current on CC2 Pin

V

= 5 V, V

= 0 V

I

304

166

330

180

356

194

mA

CC

CC2

P−CC2−330

Used for USB PD to signal that the

Sink can communicate, V = 5 V,

P−CC2−180

CC

V

= 0 V

CC2

Input Impedance on CC1 Pin

Input Impedance on CC2 Pin

= 0 V, Sourcing 330 mA on CC1

= 0 V, Sourcing 330 mA on CC2

Z

126

0.75

kW

V

CC

OPEN−CC1

OPEN−CC2

Ra Impedance Detection Voltage Threshold

on CC1 Pin

V

= 5 V, V

= 5 V, Decreasing

= 5 V,

V

0.80

2.60

150

0.85

2.75

200

CC2

CC1

CC2

RA−CC1

RA−CC2

RD−CC1

RD−CC2

CC1

Ra Impedance Detection Voltage Threshold

on CC2 Pin

V

= 5 V, V

0.75

2.45

V

CC

CC2

Rd Impedance Detection Voltage Threshold

on CC1 Pin

V

CC

= 5 V, V

Decreasing V

CC1

Rd Impedance Detection Voltage Threshold

on CC2 Pin

V

CC

= 5 V, V

= 5 V,

CC2

CC1

Decreasing V

Sink Attach Debounce Time (Note 5)

GATE High Voltage at 3.3 V

GATE High Voltage at 21 V

V

CC

V

CC

V

CC

V

CC

= 5 V

t

100

5.3

ms

V

CCDebounce

= 3.3 V

= 21 V

V

GATE−3.3V

V

24.5

V

GATE-21V

GATE High Voltage at V

= V

V

30

V

IN−OVP−MAX

CC−OVP−MAX

GATE−MAX

V

supply voltage

OCP voltage

V

3.0

50

5.5

V

CONN

CONN_OCP

I

mA

ms

mA

V

OCP debounce time

supply current

t

2.6

34

3.6

4.7

VCONN_OCP

V

= 4.75 V, VCONN = 3 V

IV

CONN

CC

CC1 Pin Over−Voltage Protection

CC2 Pin Over−Voltage Protection

CC1/CC2 OVP Debounce Time

Safe Operating Voltage at 0 V

USB PD BMC TRANSMITTER SECTION

Unit internal

V

5.5

5.75

28

6.0

CC1−OVP

CC2−OVP

V

t

ms

V

-

CC OVP−DEB

VSafe0V

0.66

0.73

0.80

1/fBitRate

tUI

3.03

1.05

3.70

1.2

ms

V

Logic High Voltage

IOH = −165 mA or 293 mA

IOL = 763 mA

V

1.125

OH

Logic Low Voltage

V

0.075

700

75

V

OL

Rise−TX

Rise time

VDD = 4.7 mF

t

300

33

500

ns

W

Fall time

VDD = 4.7 mF

t

Fall−TX

Transmitter output impedance

USB PD BMC RECEIVER SECTION

Rx bandwidth limiting filter

CC receiver capacitance

Receiver Input Impedance

zDriver

t

100

1

ns

pF

RxFilter

cReceiver

zBmcRx

15

MW

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

5. Guaranteed by Design

6. QFN package only where NTC pin is available

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9

FUSB3307

Application Information

FUSB3307 has the entire PD Device Policy Manager

where the FUSB3307 directly controls the DC/DC

controller. In the descriptions that follow, both of these

designs are discussed when describing the operation of the

FUSB3307. Interspersed within these descriptions is how it

relates to USB Power Delivery (PD) and Type C

specifications. These are just two example designs since

there are considerably more use cases of the FUSB3307 in

reference designs for power source applications. For more

information on specific design needs, please contact your

ON Semiconductor field application engineers.

(DPM), PD Policy Engine, Protocol and PHY layers within

hardware and it responds to all the messages typical for PD

Power Sources. No external processor is needed and it is

completely USB PD 3.0 with PPS compliant.

Two Reference Design Examples

Below are two reference design example applications of

the FUSB3307. One is an AC/DC design on the secondary

side of the offline design and the other is a DC/DC design

FDMC012N03

VCC

Q1

ESD

7272

C8

GATE

C1

R4

C4

USB Type−C

Detection

and Gate

Drivers

VCC

R5

VBUS

DISC

CC2

R1

C9

Sync. Rec.

Ctrl (e.g.

IS+

PD 3.0

Device Policy

Manager,

Policy

NCP430x)

D−/PDIV0

D+/PDIV1 ^R3

R2

IS−

R10

PWM Controller

(e.g. NCP1345,

NCP12601)

CC1

C2

R11

Engine,

CATH

IFB

C10

VDD

Protocol &

PHY Layers

C3

R6

C5

R8

ESD

7272

ESD

7272

C6

CV/CC

C7

Regulation

R7

26V

VFB

2 ESDM3551’s

FUSB3307

R9

Figure 5. Offline Reference Design Example

CSN1

CSP2 CSN2

CSP1

NVMFS5A140PLZ

VSW1

VSW2

HSG2

NVTFS4C10N

HSG1

SZ1SMB

30CAT3G

C8

26V

NVTFS4C10N

SZMM3Z

18VT1G

NVTFS002N04CL

VCC599

LSG1

LSG2

2 x

NVTFS4C10N

NSVR

0240

V2

Q1

SZESD

7272

BST1

BST2

V1

HSG1

LSG1

HSG2

LSG2

HSG1

LSG1

HSG2

LSG2

VCC599

VCCD

VDRV

VCC

GATE

VCC

VBUS

NCV81599

DISC

CC2

EN

R1

USB Type−

PGND1

VCC599

5V

VSW1

VSW2

VSW1

VSW2

C

PGND2

CSP1

CSN1

CSP2

CSN2

FB

R4

R5

Detection

and Gate

Drivers

CSP1

CSN1

CSP2

CSN2

D−_HOST

D−/

PDIV0

D+/

D−

PDRV

D+_HOST

NIV1241

D+

PDIV1

IS+

GND

SDA

C4

PD3.0

Device

Policy

CC1

SCL

CLIND

ADDR

IS−

CS1

CS2

Manager,

Policy

COMP

AGND GND

C1

SZESD

7272

Engine,

Protocol&

PHY

SZESD

C2

CATH

IFB

7272

Layers

R6

C5

R12

VDD3307

C6

CV/CC

Regulation

PDIV2

OTP

C7

R14

R16

R15

R8

R7

FUSB3307

VDD3307

C3

NTC

R13

VDD

VFB

GND

R9

Figure 6. Automotive DC/DC Reference Design Example

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10

FUSB3307

Power Up and Assumptions

typical default operation. However this buck−boost resistor

divider is set to 1:50 ratio to set the upper limit of the voltage

while the FUSB3307 directly controls the PWM operation

within the buck−boost. If direct COMP pin control of the

buck−boost is not desirable, then the FUSB3307 can control

the FB pin via a simple external circuit. Please contact

ON Semiconductor Field Application Engineers for more

details.

FUSB3307 will not attach to any Sink devices unless 5 V

(4.75 V to 5.5 V voltage range) is first attained on its VCC

pin since that is the basis of both the USB Type C and USB

Power Delivery (PD) specifications. From this 5 V on VCC,

the FUSB3307 derives its VDD voltage which is used for

powering the internal circuitry as illustrated by this section

of the block diagram shown in Figure 8.

For Figure 5, the focus is on only the secondary side of this

power source and only on the interactions with the

FUSB3307 device. For Figure 6, only the interconnections of

the FUSB3307 with the buck−boost shown will be discussed,

not the buck−boost operation. It is assumed all other

functionality of these AC/DC and DC/DC designs is known.

For Figure 5, upon application of an AC source, the

secondary side VCC starts at 5 V and for Figure 6, upon

application of input VBAT, the buck−boost regulates VCC

at 5 V for USB−C operation. The FUSB3307 takes its input

from the resistor divider ratio comprising of R8 and R9 in

Figure 5 and Figure 6 above. In Figure 5, FUSB3307

controls the CATH pin current through the opto−coupler,

R11 and R10 resistors for providing the feedback to the

primary side controller to regulate to 5 V as shown in

Figure 7.

Figure 7. Constant Voltage / Constant Current

(CV/CC) section of Application Diagram

Figure 8. VDD Generation with FUSB3307

In Figure 6, FUSB3307 controls the CATH pin voltage

which is tied to the COMP pin of the buck−boost which

directly regulates the output voltage to 5 V. The ratio of

R9:(R8+R9) is expected to be 1:10 to achieve 5 V on VCC

upon power up which is typically R8 = 120 kohms and R9

= 13.3 kohms.

It is expected that a capacitor, C3 is connected externally

(typically 1 mF) from VDD to ground to provide energy

storage. VDD is regulated to be at the appropriate voltage for

the internal circuitry for any USB PD contract from 3.3 V

when in a USB PD Programmable Power Supply (PPS)

contract to the highest PPS voltage of 21 V.

In Figure 6, the buck−boost has its feedback FB pin which

has the resistor that also expects a 1:10 resistor divider in

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11

FUSB3307

CC1 and CC2 Lines and USB−C Receptacle Assumptions

C1

If a USB−C receptacle is used, CC1 and CC2 are

connected from the receptacle to the FUSB3307’s CC1 and

CC2 pins. If a hardwired connection (called “captive cable”

in Type−C and USB PD specifications) is desired, the CC

line is connected to CC1 (or CC2 if more convenient for

routing) and the VCONN line is connected to CC2 (or CC1)

pin not used above.

The design in the figures above assumes a Type C

receptacle (as opposed to captive cable) and all the following

descriptions are consistent with this configuration. Also

assumed is USB 2.0 only receptacle (D+ and D−) for a power

source application without data (that is, the USB D+ and D−

do not go to a USB PHY). All SuperSpeed lines (TX1+,

TX1−, RX1+, RX1−, TX2+, TX2−, RX2+, RX2−) are left

unconnected and the SBU1 (Side Band Use) and SBU2 pins

are not used.

USB Type−C

Detection

and Gate

Drivers

VBUS

DISC

CC2

R1

PD 3.0

Device Policy

Manager,

Policy

Engine,

Protocol &

PHY Layers

D−/PDIV0

D+/PDIV1 R3

R2

CC1

C2

VDD

C3

ESD

7272

ESD

7272

CV/CC

Regulation

2 ESDM3551’s

FUSB3307

Figure 9. CC1 and CC2 Proximity to VBUS Within

Type−C Connector

Internally, the FUSB3307 pulls up CC1 and CC2

individually to VDD with currents that advertise 3 A

capability for this power source per USB Type C

specification. When a Sink device is connected to the

USB−C receptacle, the voltages on CC1 and CC2 will drop

down per Type C specification. The FUSB3307 will detect

a legitimate attach with the Sink and accordingly turn on the

VBUS FET Q1 (see VBUS Operation descriptions below).

If this design needs high−voltage, short−to−VBUS

protection on CC1 and CC2, the FUSB3307 protects the

CC1 and CC2 lines internally to the highest VBUS voltage

that is possible for USB PD. FUSB3307 also detects CC1

and CC2 pins in this over−voltage state and goes into the

Type C Disabled state. But it will take a finite amount of time

to detect an over−voltage event on CC1 or CC2, turn off the

load switch FET Q1 and discharge VBUS and thus the

over−voltage protection on CC1 and CC2 to protect these

I/Os. The CC1 and CC2 connector pins are physically close

to the VBUS connector pins which is why this need arises

more often than not as highlighted in Figure 9.

For USB PD traffic, per specification, the CC1 (and CC2)

line needs a capacitor to ground that is between 200 pF and

600 pF to minimize noise coupling from other signals within

the connector (especially if D+ and D− USB 2.0 data is sent

through the USB−C connector). Since the FUSB3307 has

very little internal capacitance on the CC1 and CC2 lines

(cReceiver in the electrical tables above), most of this has

to be supplied externally. The recommended value is 390 pF

capacitors from CC1 to ground and CC2 line to ground (C1

and C2 in Figure 5 and Figure 6) and the voltage rating is

dependent on the decision for high voltage protection above.

VBUS Operation

VBUS from the USB−C connector is typically connected

to a load switch NFET (Q1) source terminal whose gate

terminal is driven by the FUSB3307 gate driver via the

GATE pin. There isn’t a need for putting a resistor between

GATE pin and the gate of Q1 since when the load switch is

first turned on, upon attach of a Sink device via the USB−C

connector, the Sink device is not allowed to draw more than

500 mA. However, if desired for a soft turn−on of the FET,

a small (10 ohms typical) resistor can be placed between the

FUSB3307 GATE pin and the gate terminal of Q1. The drain

terminal of Q1 is connected to the power VCC which is at

5 V in the normal detached operation or in an initial USB−C

attach.

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12

FUSB3307

Figure 10. VBUS Discharge by FUSB3307 via DISC Pin

VBUS is discharged through a resistor (R1) via the DISC

pin of the FUSB3307 as shown in the highlighted section in

Figure 10.

The external resistor R1 value is dependent on the total

bulk capacitance (C8) of this power source so that VBUS is

discharged within the time limits dictated by USB PD. A

typical value for R1 is 39 W, 1 W and in addition, there is

internal resistance that causes a expected discharge current

USB Type C specification requires that the supply voltage

is not sourced on VBUS until an attach per Type C

specification has been determined. Dual back−to−back

FET’s for the load switch are not needed for reverse voltage

protection since it is unlikely that VBUS is charged from an

external source. For interoperability with legacy connectors,

there is a case where a Type A to Type C cable is first plugged

into a Type A port of a power source which then supplies 5 V

on VBUS of the cable. Then the Type C connector is plugged

into this design which is not plugged into the AC outlet nor

gets it power from the DC input depending on the design.

The 5 V from the cable will forward conduct through the Q1

FET and charge the bulk capacitor C8. This doesn’t cause an

issue, since the FUSB3307 will power up, check the CC1

and CC2 lines and realize it is not a legitimate Sink device

plugged in and stay detached. Upon unplugging the A to C

within the FUSB3307 in its discharge path (I

in the

DISC −Sink

electrical tables above). If the load current to the Sink is

sufficient (exceeds for

I

t

CS−EN−DSCG

debounce time) such that the internal discharge is not

needed, then the FUSB3307 will automatically disable

internal discharge.

Upon power up, the FUSB3307 will discharge VBUS in

case there is any voltage on VBUS since the only way a Sink

can be attached per Type C specification is if VBUS is

discharged to ground (below VSafe0V) upon attach. The

discharge resistance limits are governed by the Type C

specification when not sourcing power on VBUS

cable, the discharge resistance (R

in the electrical

DISC−BUS

tables above) will discharge VBUS to ground if the input

voltage is still unavailable. Even if the input power is

supplied to this design during this incorrect connection,

VCC will regulate to 5 V which will prevent the previously

forward bias body diode of Q1 FET from conducting and the

FUSB3307 will wait for a legitimate Sink to be attached

before turning on FET Q1. The maximum bulk capacitance

is specified in the Type C specification to handle this fault

case as shown in Table 5 from the USB Type C specification

so as to allow for just one FET use for optimum efficiency.

(R

DISC−BUS

in the electrical tables above). It is preferred that

no external load/discharge resistor is connected to VBUS

other than R1 to the FUSB3307 discharge DISC pin.

A TVS diode connected from VBUS to ground and shown

in the figures ([SZ]ESD7241) allow operating voltages up

to 24 V covering the entire VBUS range of 3.3 V to 21 V for

a USB PD PPS contract. This can be replaced by a TVS that

covers the VBUS range for the use case of this design if

needed.

Table 5. TYPE−C SPECIFICATION FOR VBUS BULK CAPACITANCE

Symbol

Notes

Min

Max

Units

VBUS

Capacitance

Capacitance for source−only ports between VBUS and GND pins on

receptacle when VBUS is not being sourced.

3000

mF

Capacitance for DRP ports between VBUS and GND pins on recep-

tacle when VBUS is not being sourced.

10

mF

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13

FUSB3307

Capacitance to ground on the connector side VBUS

The current is sensed via a small resistor R4 (5 mW

typically) connected between the USB−C connector ground

and the main ground plane of the power source (secondary

side ground for offline design) as shown in Figure 12.

connection (source of Q1) can be added if needed but it

hasn’t been shown in the application diagrams above. If

added, it is recommended it doesn’t exceed 1 mF for

recovery from the source−source case mentioned above.

Voltage and Current Sensing Operation

As mentioned above (see Power Up and Assumptions),

the resistor ratio from VCC to ground formed by resistors R8

and R9 (typically 1:10 ratio where R8=120k and R9=13.3k)

and sensed via FUSB3307 VFB pin will sense the voltage

for VCC in order to set a new voltage. For Figure 5 offline

design, this will be done via the FUSB3307 CATH pin, the

opto−coupler, resistor R10 and the primary side PWM

controller operation. R11 provides a bias current to the

CATH pin feedback circuit within the FUSB3307 and is

optional. For Figure 6 buck−boost design, this will be done

via the FUSB3307 CATH pin controlling the buck−boost

PWM via its COMP pin. The FUSB3307 will automatically

control the CATH pin based on the desired voltage as

determine by the USB PD contract and the existing VCC

voltage sensed by VFB. If FUSB3307’s PD communication

is not responded to by the Sink upon initial attach, the

FUSB3307 will continue with 5 V VBUS Type C operation

until the Sink detaches. The external compensation network

formed by C6/R7/C7 and R6/C5 need to be selected to

achieve stable operation over the range of VBUS voltage

and current transitions as shown in Figure 11.

Figure 12. Current Sense Network

A low pass filter formed by R5/C4 provides a stable signal

for IS+ and IS− pins of the FUSB3307 to sense this current

for over−current protection for fixed voltage PD contracts,

constant current operation for PPS contracts and cable

compensation if selected from the trim table (Table 6). It is

expected that the USB−C connector ground is connected

only to the current sense network resistors R4 and R5 and the

connector TVS ground connections and not to the main

ground plane of the NCV81599 for the DC/DC design or

secondary side power ground for the offline design

(FUSB3307 ground connection). However, the FUSB3307

consumes very little current and so it should have a

negligible impact on this current sensing if the FUSB3307

ground connection is on the USC−C connector ground if it

is more convenient in the Printed Circuit Board (PCB)

layout.

When in a PPS contract, if a PPS_Status message is

requested, the FUSB3307 will measure the current with an

internal 10−bit Analog to Digital Converter (ADC) based on

the above description and report it back to the Sink on the

PPS_Status message. The voltage is also reported back but

it is measured off VCC with the ADC not VFB pin since the

VFB pin is only used for voltage feedback. Thus if the

voltage feedback resistor divider connected to VFB is

modified to be slightly different from the 1:10 ratio

expected, the voltage sensing for this PPS_Status message

will not be affected.

Figure 11. Compensation Network for Constant

Voltage / Constant Current (CV/CC) Feedback

For the offline design, C10 may be needed as well. For the

DC/DC design, there may be a need for additional

compensation networks from COMP pin to ground or from

COMP to the NCV81599 supply.

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14

FUSB3307

USB 2.0 Data Lines

2.0 data signals. For the automotive buck−boost design

(Figure 6), short−to−VBUS protection is shown via the

NIV1241 that contain TVS diodes and FETs to keep the

FUSB3307 D+ and D− lines less than 5 V as shown in

Figure 13.

The USB 2.0 Data Lines D+ and D− can be externally

connected together via a 100 ohms resistor to provide the

maximum power, a legacy USB device can take, which is

1.5 A per USB Battery Charging v1.2 (BC1.2) specification.

This will usually be the case when a USB−C to micro−B

cable is plugged into this design where this adapter cable has

the required Sink Rd resistors within it to allow the

FUSB3307 to recognize a Type C attach and to source 5 V

on VBUS. The Sink will go through BC1.2 steps of primary

and secondary detection to detect a Dedicated Charging Port

(DCP) via this resistor connection of D+ and D− and takes

1.5 A maximum from VBUS.

Figure 13. D+ and D− Pin Protection Provided by the

If selected by the Trim table (Table 6), to attach to certain

phones that require resistor dividers on D+ and D− then

connect D+ and D− to the FUSB3307 with small (22 W

typical) resistors which auto−detects which type of legacy

Sink is plugged in and automatically provides the legacy

device with the appropriate power level it needs to charge.

Note this power level is controlled by the device itself not the

power source which is typical of most legacy USB power

systems. The FUSB3307 will allow for 5 V at a maximum

of 3 A for even legacy devices which will take at most either

1.5 A or 2.4 A for most legacy devices.

D+ and D− can also be connected to a USB Physical Layer

(PHY) controller for using these lines for data traffic. In that

case, the USB PHY is expected to advertise itself as a

Charging Downstream Port (CDP) per BC1.2 so that the

Sink can take a maximum of 1.5 A of power.

NIV1241

Power Delivery Operation

FUSB3307 advertises source capabilities and responds to

PD message completely autonomously following the USB

PD 3.0 with PPS and Type C specifications. For more details

on the USB PD messages please refer to the specification

references mentioned below (See Specification References

on page 19). Similarly the references mention the Type C

and the BC1.2 specifications as well for further information.

To allow for a variety of designs, the following table has

a number of trim options to accommodate almost every

design. The following Table 6 lists out the various options.

While all these options exist, they can only be obtained from

ON Semiconductor if requested and once delivered, the trim

option cannot be changed. The default trim option column

below is for a 60 W design that uses 3 A cables and is for a

USB Power Delivery (PD) 3.0 design with Programmable

Power Supplies (PPS) and Fixed Supplies. In the future

more default options will be available for general purpose

use with likely 30 W, 45 W and 90 W power levels in

addition to the 60 W option.

D+ and D− are low voltage pins (6 V absolute maximum

voltage) and are not expected to be shorted to VBUS when

VBUS goes higher than 6 V. The TVS diodes connected to

D+ and D− shown in the figure (ESD7104) allow operating

voltages up to 5 V for the offline design (Figure 5) and

typically D+ and D− are 3.3 V signals when used for USB

Table 6. FUSE TRIM (NOTE 7) OPTION TABLE

#

1

2

3

Function

Trim Option

Default Option

60 W

Output Power

PD Power (PDP) from 16 W to 100 W in 1W increments

Four choices of 50 mV/A, 100 mV/A, 150 mV/A and Disabled

Cable Compensation

5 A Power Source

Disabled

0 = Max current is 3 A, no eMarker detection

1 = Max current is 5 A, eMarker detection needed

0 = Max current = 3 A,

no eMarker detection

4

5

6

Charging Output OVP

Charging Output UVP

Four choices of OVP thresholds: 115%, 120%, 125% and 130%

Four choices of UVP thresholds: 60%, 65%, 70% and Disabled

120% OVP

65% UVP

D+/D− versus

PDIV0/PDIV1

00: D+/PDIV1=D+, D−/PDIV0=D− (SOIC package without PDIV2 pin)

01: D+/PDIV1=PDIV1, D−/PDIV0=PDIV0 (SOIC package without PDIV2 pin)

10: D+/PDIV1=PDIV1, D−/PDIV0=PDIV0 PDIV2 standalone pin

(QFN package)

00 for SOIC package

11 for QFN package

11: D+/PDIV1=D+, D−/PDIV0=D− PDIV2 standalone pin (QFN package)

7

Support PD 3.0

0 = Enable PD 2.0

1 = Enable PD 3.0

7. ”Trim Options” means feature programmability to create new functional options in a manufacturing test program by trimming semiconductor

fuses.

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15

FUSB3307

When a Sink device is connected via the USB−C

as the FUSB303. Subsequent to the initial attach, the

FUSB3307 will send out PD packets to advertise source

capabilities as selected by the trim options in Table 6. Using

the Default FUSB3307 Trim options, the FUSB3307 will

source 60 W by sending out a PD Source_Capabilities

message on the CC line (either CC1 or CC2 depending on

connector plug orientation) using PD communication

messages. The supplies advertised for the default trim option

are fixed supplies and PPS supplies shown in Table 7:

connector, as mentioned above, the FUSB3307 will detect

a legitimate Type C attach and drive the GATE pin to turn on

the VBUS load switch Q1. The initial voltage on VBUS is

always 5 V (4.75 V to 5.5 V voltage range) and the CC pin

will advertise 3 A capability which is the maximum power

allowed by a Type C (without PD) port. FUSB3307 is not

expected to be used below 15 W power level since

ON Semiconductor has other Type C only controllers such

Table 7. DEFAULT TRIM OPTION ADVERTISED PD SOURCE CAPABILITIES

[Augmented] Power Data Object

Output Voltage

Maximum Sink Current Expected

Current Protection

Over Current Protection

Current Limit Protection

PDO1

PDO2

PDO3

PDO4

PDO5

APDO1

5 V

3 A

9 V

12 V

15 V

20 V

3.3 V min, 21 V max

The Sink will select one of these offerings and enter into

a PD explicit contract with the FUSB3307 which is the first

step of all subsequent PD communication. If the Sink selects

an illegal data object number or requests an illegal current

level, the FUSB3307 will reject the request. A short amount

of time after this reject message is sent, the FUSB3307 will

resend its Source_Capabilties message and expect a valid

request.

If a 5 A capability is chosen from the trim table (Table 6)

above then the FUSB3307 will use USB PD Discover

Identity messages to interrogate the capabilities of the cable

attached to it to ensure that it is a 5 A capable cable before

the FUSB3307 advertises 5 A source capabilities. The

FUSB3307 supplies the VCONN power needed to support

this discovery process as specified in the USB PD and

Type C specification which eliminates the need for an

external VCONN power source and multiple power

switches. If the cable is only 3 A, even though the

FUSB3307 can support 5 A, the advertised capabilities will

all drop down to 3 A. This will be done on the first source

capabilities advertised but there is an indication in the USB

PD Status message sent to indicate that the source is 5 A

capable but the cable has limited the source capabilities to

3 A. In Table 8 the section of the SOP Status Data Block

(SDB) is shown that communicates this power limitation.

The FUSB3307 follows all USB PD specifications

including dropping down to USB PD 2.0 operation when it

detects a USB PD 2.0 Sink and a USB PD 2.0 cable eMarker

(if applicable). All subsequent operation will follow the

USB PD 2.0 specification until the FUSB3307 is reset via a

Hard Reset message or undergoes a power cycle.

Standby Operation

When the FUSB3307 is in standby, where the source

power supply still has to be maintained at 5 V via the CATH

pin for a typical Type C connection but no Sink device has

been attached to the FUSB3307, then the current consumed

is just I

( < 870 mA typical). This low standby

CC−GREEN

current allows for all the energy standard specifications to be

well exceeded for offline designs (typically the FUSB3307

within the offline design can achieve 21 mW standby

power).

PDIV0, PDIV1 and PDIV2 Options

FUSB3307 can adjust the output power from the trim

table (Table 6) to have any PDP (Power Delivery Power)

from 16 W to 100 W (called TrimPDP here) in 1 W

increments. However, in some applications in may be

advantageous to trim all FUSB3307 devices to 60 W PDP

and use them in both single port and dual port

configurations. For the dual port configuration, the PDP

would need to be halved for assured capacity charger ports

and PDIV2 pin does just that – cuts the trimmed 60 W PDP

in half to 30 W. For further divider ratios, PDIV1 and PDIV0

can be used as well.

PDIV2 is available only in the QFN version of the

FUSB3307 while PDIV0 and PDIV1 share their

functionality with the D− and D+ pins respectively in both

the QFN and SOIC package options. For the PDIV2 pin, the

selection of power is shown in Table 9.

Table 8. PD Status Message to Sink Showing Power is

Limited by the Cable

Offset

Field

Bit

0

Description

5

Power

Status

...

1

Source power limited due to

cable supported current

2

...

6...7

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16

FUSB3307

In all the above calculations, no Advertised PDP will ever

Table 9. PDIV2 Pin Changing Advertised PD Power

go below 16 W minimum if in a USB PD contract. For

example, if TrimPDP=100 and when PDIV0, PDIV1 and

PDIV2 Pin State

Advertised PDP (Power Delivery Power)

100% of TrimPDP

1

0

PDIV2

pins

are

available

and

they

are

50% of TrimPDP

[PDIV2:PDIV1:PDIV0] = 001 then Advertised PDP is

25 W (100W*25%). However if TrimPDP=60, then

Advertised PDP is 16 W not 15 W (60W*25%).

With the SOIC package and PDIV0 and PDIV1 pins

selected, the power can be controlled as shown below. In this

case there is no PDIV2 pin and the PDIV0 and PDIV1 pins

are used to trim power, as shown in Table 10.

When any of these pins, PDIV0, PDIV1 and PDIV2 are

changed, the connected PD Sink has to ask for Source

Capabilities to get these new capabilities or if this Sink or the

FUSB3307 executes a Soft_Reset or Hard Reset which causes

the new advertised capabilities to be sent by the FUSB3307.

Alternatively recovery from any protection operation would

cause the FUSB3307 to advertise the new PDP values based

on the PDIV0, PDIV1 and PDIV2 pins setting.

Table 10. PDIV0 and PDIV1 Pins Changing Advertised

PD Power

Advertised PDP

(Power Delivery Power)

100% of TrimPDP

75% of TrimPDP

PDIV1 Pin State PDIV0 Pin State

1

0

1

0

Protection Operation

FUSB3307 has a number of ways it protects itself as

shown in Table 12.

50% of TrimPDP

25% of TrimPDP

If PDIV2 is also available (i.e. QFN package) and in the

above trim table (Table 6) the pins D+/PDIV1 and

D−/PDIV0 allow PDIV0 and PDIV1 to be available as pins,

then this is the PDP advertised, as shown in Table 11.

Table 11. PDIV0, PDIV1 and PDIV2 Pins Changing

Advertised PD Power

PDIV2

Pin State

PDIV1

Pin State

PDIV0

Pin State

Advertised PDP (Pow-

er Delivery Power)

1

0

1

0

1

0

1

0

1

0

1

0

1

0

100% of TrimPDP

87.5% of TrimPDP

75% of TrimPDP

62.5% of TrimPDP

50% of TrimPDP

37.5% of TrimPDP

25% of TrimPDP

12.5% of TrimPDP

Table 12. Protection Modes Available

Symbol

Description

Pin(s) Used

VCC

Package

OVP

UVP

Output Voltage Over Voltage Protection

Output Voltage Under Voltage Protection

Over Current Protection

SOIC & QFN

QFN only

VCC

OCP

IS+ & IS−

none

I_OTP

Internal Over Temperature Protection

External Over Temperature Protection

CC1 or CC2 Over Voltage Protection

CC1 or CC2 VCONN Over Current Protection

E_OTP

CC_OVP

VCONN_OCP

NTC

CC1 / CC2

SOIC & QFN

www.onsemi.com

17

FUSB3307

OVP and UVP are sensed via an internal resistor divider

For compliance with the USB PD specification, the

FUSB3307 will trigger UVP whenever VCC is below

that divides VCC by 10 to determine the voltage from the

power source. CC1 and CC2 are directly sensed for over

voltage. For E_OTP (QFN package option only), a pin NTC

is available that is connected to an NTC resistor to ground

usually in parallel with another resistor to ground for

linearity. For I_OTP (SOIC and QFN packages), an internal

temperature monitor is used. For all faults except

VCONN_OCP fault, upon detection, the FUSB3307 will

disable the Type C connection with the Sink (no pull−up on

CC), shut off VBUS load switch and keep monitoring the

fault. Once the fault has been removed, the FUSB3307 starts

V

CC

. This allows protection for a direct short of VBUS

−OFF

to ground separately or in conjunction with the OCP fault

described below. If VCC < V fault is triggered, then

−OFF

CC

to resume normal operation, VCC has to go below V

LATCH

to reset the FUSB3307 to exit this fault condition.

Over Current Protection (OCP) and Constant Current

Limit (CL)

If VBUS is shorted to ground, either the UVP fault

described above could trigger or the OCP fault, or both.

FUSB3307 senses the current via a small R4 resistor (5 mW

typical) as described in the Voltage and Current Sensing

section above. The OCP fault is triggered at 120% of the

maximum current for the requested Power Data Object

up at 5 V after t

Sink.

seconds and reconnects with the

2S_AR_NM

Output Over Voltage Protection (OVP)

(PDO) for fixed supplies only (I

typically 3.6 A for a

FUSB3307 has built−in OVP based on the Trim Table

(Table 6). For the default OVP case, whenever VCC, as

sensed by an internal 1:10 resistor divider, exceeds

CS−3A

3 A maximum fixed supply current). Once this OCP fault

occurs, the FUSB3307 protects the system as described in

the Protection Operation section above. An Alert message

is sent upon the FUSB3307 establishing an explicit contract

with the Sink and a PD “Status” message from the

FUSB3307 will include the OCP history.

For PPS APDO’s (Augmented Power Data Objects),

Constant Current Limiting (CL) is used as specified in the

USB PD specification where the voltage will drop to a low

value based on keeping the current constant and equal to the

requested PPS current. In this case UVP described above

K

(typically 120%) of the requested VCC from the

CC−OVP

power source for a debounce time of t , then the OVP

D−OVP

fault would be triggered. Upon detection, the FUSB3307

will disable the Type C connection with the Sink (no pull−up

on CC), shut off VBUS load switch and keep monitoring

VCC to determine if the OVP is still present. When OVP is

removed, a timer is started which when expired in t

2S_AR

seconds, causes the FUSB3307 to reestablish the Sink Type

C connection with the initial 5 V VBUS supplied as if it were

initially attached.

will trigger if VCC drops below V

since any voltage

−OFF

CC

from the lowest 3.3 V – 5% to the PPS requested voltage

could occur with current limiting. If the PPS current limit is

changed with a new PD Request message, the VCC voltage

may change accordingly to a new value based on the current

limiting function. An Alert message is sent whenever there

is a switch from Constant Current Limit (CL) to Constant

Voltage (CV) mode and vice versa. For PPS_Status

messages, this flag that shows whether the FUSB3307 is in

CL or CV mode, is sent along with the VCC voltage and load

current as sensed by R4 to monitor the FUSB3307 while it

provides PPS voltages and currents.

During transitions between VCC voltages, the OVP

circuitry is blanked or disabled for t

time to ensure

BNK−OVP

that false triggering of OVP doesn’t occur. To ensure safe

operation over all voltages of VCC, the maximum VCC

voltage is limited to V

CC−OVP−MAX.

Output Under Voltage Protection (UVP)

FUSB3307 has a built−in UVP based on the Trim Table

(Table 6). For the default UVP case, whenever VCC, as

sensed internally, is below K

(typically 65%) of the

CC−UVP

requested output voltage from the power source for a

debounce time of t , then the UVP fault would be

D−UVP

Over Temperature Protection (I_OTP and E_OTP)

FUSB3307 has two different over temperature faults,

E_OTP and I_OTP. For E_OTP, when the QFN package is

used, there is a NTC pin that is expected to be connected to

an NTC resistor in parallel with a regular resistor for

triggered. No PD Alert messages are sent for this fault.

During transitions between VCC voltages, the UVP

circuitry is blanked or disabled for t

time to ensure

BNK−UVP

that false triggering of UVP doesn’t occur.

For PPS contracts, if current limiting causes the voltage to

decrease, the UVP fault will not trigger at 65% of VCC since

linearity. The FUSB3307 provides a I

current source

NTC

(typically 60 mA) on the NTC pin to bias this NTC resistor

so that an internal A/D converter measures the external

temperature as shown in Figure 14.

all voltages from the requested voltage to V

lowest voltage, are valid.

the

−OFF,

CC

www.onsemi.com

18

FUSB3307

VCC

FAULT

9R

R

Protection

Block

V

IN−1:10

OVP/UVP/

OCP

V

vdd

V

CS−AMP

COMR

Protection

V

CS−AMP

Analog to Digital

Converter

NTC

IN−1:10

Internal temp.

CATH

Figure 14. Protection Section of Block Diagram for UVP, OVP, OCP, and OTP Faults

This NTC measured temperature is useful for dynamic

to start protecting the system when the CC voltage is beyond

it normal operating range. If the CC voltage is above

monitoring by the Sink via FUSB3307 provided PD Status

messages which contains this NTC temperature in this

package option. If this temperature exceeds a warning

threshold (100°C for a NTC resistor of 100 kW 1%, B25/50

= 4300K 1% to ground in parallel with a 20 kW 1% to

V

(if CC is CC1 pin) or above V

(if CC is

CC1−OVP

CC2−OVP

CC2 pin) threshold for t

debounce time, then

CC−OVP−DEB

the FUSB3307 protects the system by triggering this fault

and executing protection as described in Protection

Operation section above.

ground) for t

debounce time, then a PD Alert

NTC−DEB

message is sent to the Sink indicating this temperature

warning. If however, the E_OTP threshold is exceeded

(110°C for a NTC resistor of 100 kW 1%, B25/50 = 4300K

1% to ground in parallel with a 20 kW 1% to ground) for

VCONN Over Current Protection (VCONN_OCP)

FUSB3307 will turn on VCONN whenever it needs to

read the eMarker in the cable only if 5 A capability is chosen

from the trim table (Table 6) above and this design has a

Type C connector and not a hardwired captive cable. When

VCONN is sourced, per USB PD specification only

100 mW maximum (5 V with 20 mA for the FUSB3307)

needs to be supplied for a USB 2.0 source application. If the

t

debounce time, then an E_OTP fault is triggered

NTC−DEB

as described in the Protection Operation section above.

Upon re−establishing an explicit contract with the Sink, the

FUSB3307 sends an Alert to let the Sink know it previously

experienced an Over Temperature Protection event.

The SOIC package version of the FUSB3307 doesn’t have

an NTC pin and so the internal die temperature is monitored.

VCONN current exceeds I

(typical 50 mA) for

CONN_OCP

t

then the FUSB3307 will disable the VCONN

VCONN_OCP

supply and abort the eMarker discovery process. The default

maximum current of 3 A will be used for all source

capabilities for USB PD messages in the latter case and the

normal PD messaging will occurs without interruption. No

Alert messages will be sent but the PD Status message will

have a bit to indicate that the cable limited the FUSB3307

from advertising 5 A source capabilities.

When the die temperature exceeds T

threshold for

INT−W

t

debounce time, then a PD Alert message is sent to

NTC−DEB

the Sink indicating this temperature warning. If however, the

threshold is exceeded for t debounce

T

INT−OTP

NTC−DEB

time, then an I_OTP fault is triggered and executing

protection as described in Protection Operation section

above. The FUSB3307 sends an Alert to let the Sink know

it previously experienced an Over Temperature Protection

event. This internal die temperature is monitored also in the

QFN package option and either an E_OTP fault (based off

the NTC pin voltage) or an I_OTP fault causes the

FUSB3307 to disconnect and shut off VBUS. The

temperature warning for the QFN package is only triggered

via the NTC resistor not the internal die temperature.

Specifications References

• Universal Serial Bus Power Delivery specification

revision 3.0 version 2.0 + ECNs up to 07 February, 2020

• Universal Serial Bus Type C Cable and Connection

Specification release 2.0, dated August, 2019

• USB Battery Charging Specification, revision 1.2,

dated December 7, 2010

CC1 and CC2 Over Voltage Protection (CC_OVP)

FUSB3307 protects against the CC1 and CC2 connector

pins being shorted to VBUS up to 26 V and it has the ability

• Universal Serial Bus Power Delivery specification

revision 2.0 version 1.3, dated 12 January, 2017

www.onsemi.com

19

FUSB3307

PACKAGE DIMENSIONS

SOIC−14 NB

CASE 751A−03

ISSUE L

NOTES:

D

A

B

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE PROTRUSION

SHALL BE 0.13 TOTAL IN EXCESS OF AT

MAXIMUM MATERIAL CONDITION.

4. DIMENSIONS D AND E DO NOT INCLUDE

MOLD PROTRUSIONS.

14

8

7

A3

E

H

5. MAXIMUM MOLD PROTRUSION 0.15 PER

SIDE.

L

DETAIL A

1

MILLIMETERS

DIM MIN MAX

INCHES

MIN MAX

13X b

M

B

0.25

A

A1

A3

b

D

E

1.35

0.10

0.19

0.35

8.55

3.80

1.75 0.054 0.068

0.25 0.004 0.010

0.25 0.008 0.010

0.49 0.014 0.019

8.75 0.337 0.344

4.00 0.150 0.157

M

S

0.25

C A

B

DETAIL A

h

A

X 45

_

e

H

h

L

1.27 BSC

0.050 BSC

6.20 0.228 0.244

0.50 0.010 0.019

1.25 0.016 0.049

5.80

0.25

0.40

0

0.10

M

A1

e

M

7

0

7

_

SEATING

PLANE

C

SOLDERING FOOTPRINT*

6.50

14X

1.18

1

1.27

PITCH

14X

0.58

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

www.onsemi.com

20

FUSB3307

PACKAGE DIMENSIONS

QFNW20 4x4, 0.5P

CASE 484AT

ISSUE O

ON Semiconductor and

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21


型号：	FUSB3307D6A0BFMX
厂家：	ONSEMI
描述：	USB Power Delivery 3.0 Adaptive Source Charging Controller
文件：	总21页 (文件大小：616K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

FUSB3307D6A0BFMX [ONSEMI]

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