FXLA102L8X_技术文档

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FXLA102

Low-Voltage Dual-Supply2-Bit VoltageTranslator with

Configurable Voltage Supplies and Signal Levels,

3-State Outputs, and Auto Direction Sensing

Features

Description

.

Bi-Directional Interface betw een Tw o Levels:

from 1.1 V to 3. 6V

The FXLA102 is a configurable dual-voltage supply

translator for both uni-directional and bi-directional

voltage translation betw een tw o logic levels. The device

allow s translation betw een voltages as high as 3.6 V to

as low as 1.1 V. The A port tracks the V_CCAlevel and the

B port tracks the V_CCBlevel. This allow s for bi-directional

voltage translation over a variety of voltage levels:

1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V.

Fully Configurable: Inputs and Outputs Track V_CC

Level

Non-Preferential Pow er-Up; Either V_CCMay Be

Pow ered Up First

.

Outputs Sw itch to 3-State if Either V_CCis at GND

Pow er-Off Protection

The device remains in three-state as long as either

V_CC=0 V, allow ing either V_CCto be pow ered up first.

Internal pow er-dow n control circuits place the device in

3-state if either V_CCis removed.

Bus-Hold on Data Inputs Eliminates the Need for

Pull-Up Resistors; Do Not Use Pull-Up Resistors on

A or B Ports

The /OE input, w hen HIGH, disables both the A and B

ports by placing them in a 3-state condition. The /OE

.

Control Input (/OE) Referenced to V_CCAVoltage

Packaged in MicroPak^TM8 (1.6 mm x 1.6 mm)

Direction Control Not Necessary

input is supplied by V_CCA

.

The FXLA102 supports bi-directional translation w ithout

the need for a direction control pin. The tw o ports of the

device have auto-direction sense capability. Either port

may sense an input signal and transfer it as an output

signal to the other port.

100 Mbps Throughput w hen Translating Betw een

1.8 V and 2.5 V

.

ESD Protection Exceeds:

- 15 kV HBM ((B Port I/O to GND) per JESD22-

A114 & Mil Std 883e 3015.7)

- 8 kV HBM ((A Port I/O to GND) per JESD22-A114

& Mil Std 883e 3015.7)

- 2 kV CDM (per ESD STM 5.3)

Ordering Information

Operating

Temperature

Range

Top

Mark

Packing

Package

Part Number

Method

5 K Units Tape

FXLA102L8X

XF

-40 to 85°C

8-Lead MicroPak^TM1.6 mm x 1.6 mm Package

and Reel

October-2017, Rev. 2

Publication Order Number:

FXLA102/D

Pin Configuration

B₀

B₁OE

7

6

5

8

1

4

GND

V_CCB

2

3

V_CCAA₀

A₁

Figure 1. Pin Configuration (Top Through View)

Pin Definitions

Pin #

Name

V_CCA

A₀

Description

1

2

3

4

5

6

7

8

A-Side Pow er Supply

A Side Input or 3-State Output

Ground

A₁

GND

/OE

B₁

Output Enable Input

B Side Input or 3-State Output

B Side Pow er Supply

B₀

V_CCB

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2

Functional Diagram

V_CCA

V_CCB

OE

A₀

B₀

A₁

B₁

Figure 2. Functional Diagram

Function Table

Control

Outputs

/OE

L

Normal Operation

3-State

H

H = HIGH Logic Level

L = LOW Logic Level

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3

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only.

Symbol

Parameter

Conditions

Min.

-0.5

Max.

4.6

Unit

V_CCA

V_CCB

V_CC

Supply Voltage

V

4.6

I/O Ports A and B

Control Input (/OE)

Output 3-State

Output Active (A_n)

Output Active (B_n)

V_I<0V

4.6

V_I

DC Input Voltage

Output Voltage⁽2⁾

V

4.6

V_O

V_CCA+0.5

V_CCB+0.5

-50

I

IK

DC Input Diode Current

mA

V_O<0V

-50

I_OK

DC Output Diode Current

DC Output Source/Sink Current

V_O>V_CC

+50

I_OH/I_OL

I_CC

-50

-65

+50

mA

°C

DC V_CCor Ground Current (per Supply Pin)

Storage Temperature Range

Pow er Dissipation

±100

+150

5

T_STG

P_D

mW

B Port I/O to GND

A Port I/O to GND

15

Human Body Model, JESD22-A114

Charged Device Model, JESD22-C101

ESD

8

kV

2

Notes:

1. I_Oabsolute maximum ratings must be observed.

2. All unused inputs and input/outputs must be held at V_CCior GND.

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. ON Semiconductor

does not recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol

Parameter

Conditions

Operating V_CCAor V_CCB

Ports A and B

Min.

1.1

0

Max.

3.6

V_CCA

±12

±8

Unit

V_CC

Pow er Supply

V

V_IN

Input Voltage

Control Input (/OE)

V_CC= 3.0 V to 3.6 V

V_CC= 2.3 V to 2.7 V

V_CC= 1.65 V to 1.95 V

V_CC= 1.40 V to 1.65 V

V_CC=1.1 V to 1.4 V

V_CC=1.1 V to 3.6 V

0

Dynamic Output Current I_OH/I_OL

±5

mA

±3

±2

Static Output Current

±4

µA

°C

T_A

dt/dV

_JA

Operating Temperature, Free Air

Maximum Input Edge Rate

Thermal Resistance

-40

+85

10

V_CCA/B=1.1 to 3.6 V

ns/V

°C/W

280

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4

Power-Up/Power-Down Sequence

FXL translators offer an advantage in that either V_CC

may be pow ered up first. This benefit derives from the

chip design. When either V_CCis at 0 V, outputs are in a

high-impedance state. The control input (/OE) is

designed to track the V_CCAsupply. A pull-up resistor

tying /OE to V_CCAshould be used to ensure that bus

contention, excessive currents, or oscillations do not

occur during pow er-up or pow er-dow n. The size of the

pull-up resistor is based upon the current-sinking

capability of the device driving the /OE pin.

The recommended pow er-dow n sequence is:

1. Drive /OE input HIGH to disable the device.

2. Remove pow er from either V_CC

3. Remove pow er from other V_CC.

.

Pull-Up/Pull-Down Resistors

Do not use pull-up or pull-dow n resistors. This device

has bus-hold circuits: pull-up or pull-dow n resistors are

not recommended because they interfere w ith the

output state. The current through these resistors may

The recommended pow er-up sequence is:

exceed the hold drive, I

currents. The bus-hold feature eliminates the need for

extra resistors.

and/or I

bus-hold

I(HOLD)

I(OD)

1. Apply pow er to the first V_CC

2. Apply pow er to the second V_CC

3. Drive the /OE input LOW to enable the device.

.

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5

DC Electrical Characteristics

T_A=-40 to 85°C.

Symbol

Parameter

Conditions

V_CCA(V)

2.70 to 3.60

2.30 to 2.70

V_CCB(V)

Min.

2.00

1.60

Typ. Max. Units

Data Inputs A_n

Control Pin /OE

V_IHA

1.65 to 2.30 1.10 to 3.60 .65xV_CCA

V

1.40 to 1.65

1.10 to 1.40

.65xV_CCA

.90xV_CCA

2.00

High-Level Input Voltage

2.70 to 3.60

2.30 to 2.70

1.60

V_IHB

V_ILA

V_ILB

Data Inputs B_n

1.10 to 3.60 1.65 to 2.30 .65xV_CCB

1.40 to 1.65 .65xV_CCB

1.10 to 1.40 .90xV_CCB

2.70 to 3.60

V

.80

.70

2.30 to 2.70

Data Inputs A_n

Control Pin /OE

1.65 to 2.30 1.10 to 3.60

1.40 to 1.65

.35xV_CCA

.10xV_CCA

.80

V

1.10 to 1.40

Low -LevelInput Voltage

2.70 to 3.60

2.30 to 2.70

.70

Data Inputs B_n

1.10 to 3.60 1.65 to 2.30

1.40 to 1.65

.35xV_CCB

.10xV_CCB

1.10 to 1.40

V_OHA

V_OHB

V_OLA

V_OLB

I_OH=-4 µA

I_OH=-4µ A

I_OL=4 µA

1.10 to 3.60 1.10 to 3.60 V_CCA- .40

1.10 to 3.60 1.10 to 3.60 V_CCB- .40

1.10 to 3.60 1.10 to 3.60

High-Level Output

Voltage⁽3⁾

V

.4

Low -LevelOutput

Voltage⁽3⁾

I_OL=4 µA

V_IN=0.80 V

V_IN=2.00 V

V_IN=0.70 V

V_IN=1.60 V

V_IN=0.57 V

V_IN=1.07 V

V_IN=0.49 V

V_IN=0.91 V

V_IN=0.11 V

V_IN=0.99 V

3.00

2.30

1.65

1.40

1.10

3.00

2.30

1.65

1.40

1.10

75.0

-75.0

45.0

-45.0

25.0

Bus-Hold Input Minimum

Drive Current

I

µA

I(HOLD)

-25.0

11.0

-11.0

4.0

-4.0

Continued on following page…

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6

DC Electrical Characteristics (Continued)

T_A=-40 to 85°C.

Symbol

Parameter

Conditions

V_CCA(V)

3.60

V_CCB(V)

3.60

Min.

450.00

300.00

200.00

120.00

80.00

Max. Units

2.70

Bus-Hold Input

I

Data Inputs A_n, B_n

1.95

µA

I(ODH)

Overdrive High

Current⁽⁴⁾

1.60

1.40

3.60

-450.00

-300.00

-200.00

-120.00

-80.00

2.70

Bus-Hold Input

Overdrive Low

Current⁽5⁾

I

Data Inputs A_n, B_n

1.95

µA

I(ODL)

1.60

1.40

Control Inputs /OE,

V_I=V_CCAor GND

I

Input Leakage Current

1.10 to 3.60

3.60

±1.0

µA

I

A_nPort V_O=0V to 3.6 V

B_nPort V_O=0V to 3.6 V

0

3.6

0

±2.0

Pow er-Off Leakage

Current

I_OFF

3.60

Data Outputs A_n, B_n

V_O=0 V or 3.6 V,

/OE=V_IH

3.60

0

3.60

0

±5.0

Data Outputs Data

Outputs A_nV_O=0 V or

3.6 V, /OE=GND

3-State Output

Leakage

I_OZ

µA

Data Outputs B_n

V_O=0 V or 3.6 V,

/OE=GND

3.60

V_I=V_CCIor GND; I_O=0,

/OE=GND

I_CCA/B

I_CCZ

1.10 to 3.60 1.10 to 3.60

10.0

µA

Quiescent Supply

Current⁽6^,7⁾

V_I=V_CCIor GND; I_O=0,

/OE=V_IH

0

1.10 to 3.60

-10.0

10.0

-10.0

10.0

V_I=V_CCBor GND; I_O=0

B-to-A Direction,

/OE=GND

I_CCA

µA

1.10 to 3.60

0

Quiescent Supply

Current

0

V_I=V_CCAor GND; I_O=0,

A-to-B Direction,

/OE=GND

I_CCB

1.10 to 3.60

Notes:

3. This is the output voltage for static conditions. Dynamic drive specifications are given in the Dynamic Output

Electrical Characteristics table.

4. An external drive must source at least the specified current to sw itch LOW-to-HIGH.

5. An external drive must source at least the specified current to sw itch HIGH-to-LOW.

6. V_CCIis the V_CCassociated w ith the input side.

7. Reflects current per supply, V_CCAor V_CCB

.

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7

Dynamic Output Electrical Characteristic

A Port (A_n)

Output Load: C_L=15 pF, R_LM (C_I/O=4 pF), T_A=-40 to 85°C

V_CCA=3.0 V

to 3.6 V

V_CCA=2.3 V V_CCA=1.65 V V_CCA=1.4 V V_CCA=1.1 V

to 2.7 V

to 1.95 V

to 1.6 V

to 1.3 V

Symbol Parameter

Units

Typ. Max. Typ. Max. Typ. Max Typ. Max.

Typ.

Output Rise

t_rise

3.0

3.5

4.0

5.0

7.5

ns

Time A Port⁽9⁾

Output Fall

t_fall

Time A

3.0

3.5

4.0

5.0

Port⁽¹⁰⁾

Dynamic

Output

I_OHD

-11.4

+11.4

-7.5

-4.7

-3.2

-1.7

mA

Current

High⁽9⁾

Dynamic

Output

I_OLD

+7.5

+4.7

+3.2

+1.7

Current

Low ⁽¹⁰⁾

B Port (B_n)

Output Load: C_L=15 pF, R_LM (C_I/O=5 pF), T_A=-40 to 85°C

V_CCB=3.0 V V_CCB=2.3 V V_CCB=1.65 V V_CCB=1.4 V V_CCB=1.1 V

to 3.6 V

to 2.7 V

to 1.95 V

to 1.6 V

to 1.3 V

Symbol Parameter

Units

Typ. Max. Typ. Max. Typ. Max Typ. Max.

Typ.

Output Rise

t_rise

3.0

3.5

4.0

5.0

7.5

ns

Time B Port⁽9⁾

Output Fall

t_fall

Time B

Port⁽¹⁰⁾

Dynamic

Output

I_OHD

-12.0

+12.0

-7.9

-5.0

-3.4

-1.8

mA

Current

High⁽9⁾

Dynamic

Output

I_OLD

+7.9

+5.0

+3.4

+1.8

Current

Low ⁽¹⁰⁾

Notes:

8. Dynamic output characteristics are guaranteed, but not tested.

9. See Figure 7.

10. See Figure 8.

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8

AC Characteristics

V_CCA= 3.0 V to 3.6 V, T_A=-40 to 85°C

V_CCB=3.0 V V_CCB=2.3 V V_CCB=1.65 V V_CCB=1.4 V V_CCB=1.1 V

to 3.6 V

to 2.7 V

to 1.95 V

to 1.6 V

to 1.3 V

Symbol Parameter

Units

Min. Max. Min. Max. Min. Max Min. Max.

Typ.

A to B

t_PLH,t_PHL

0.2

3.5

0.3

0.2

3.9

3.8

0.5

0.3

5.4

5.0

0.6

0.5

6.8

6.0

10.0

7.0

ns

B to A

/OE to A,

t_PZL,t_PZH

1.7

0.5

1.7

0.5

1.7

0.5

1.7

1.0

1.7

1.0

µs

ns

/OE to B

A Port,

t_SKEW

B Port⁽¹¹⁾

V_CCA= 2.3 V to 2.7 V, T_A=-40 to 85°C

V_CCB=3.0 V V_CCB=2.3 V V_CCB=1.65 V V_CCB=1.4 V V_CCB=1.1 V

to 3.6 V

to 2.7 V

to 1.95 V

to 1.6 V

to 1.3 V

Symbol Parameter

Units

Min. Max. Min. Max. Min. Max Min. Max.

Typ.

A to B

t_PLH,t_PHL

0.2

0.3

3.8

3.9

0.4

4.2

0.5

5.6

5.5

0.8

0.5

6.9

6.5

10.5

7.0

ns

B to A

/OE to A,

t_PZL,t_PZH

1.7

0.5

1.7

0.5

1.7

0.5

1.7

1.0

1.7

1.0

µs

ns

/OE to B

A Port,

t_SKEW

B Port⁽¹¹⁾

V_CCA= 1.65 V to 1.95 V, T_A=-40 to 85°C

V_CCB=3.0 V V_CCB=2.3 V V_CCB=1.65 V V_CCB=1.4 V V_CCB=1.1 V

to 3.6 V

to 2.7 V

to 1.95 V

to 1.6 V

to 1.3 V

Symbol Parameter

Units

Min. Max. Min. Max. Min. Max Min. Max.

Typ.

11.0

7.0

A to B

t_PLH,t_PHL

0.3

0.5

5.0

5.4

0.5

5.5

5.6

0.8

6.7

0.9

1.0

7.5

7.0

ns

B to A

/OE to A,

t_PZL,t_PZH

1.7

0.5

1.7

0.5

1.7

0.5

1.7

1.0

1.7

1.0

µs

ns

/OE to B

A Port,

t_SKEW

B Port⁽¹¹⁾

Note:

11. Skew is the variation of propagation delay betw een output signals and applies only to output signals on the same

port (A_nor B_n) and sw itching w ith the same polarity (LOW-to-HIGH or HIGH-to-LOW) (see Figure 10).

Skew is guaranteed, but not tested.

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9

AC Characteristics (Continued)

V_CCA= 1.4 V to 1.6 V, T_A=-40 to 85°C

V_CCB=3.0 V V_CCB=2.3 V V_CCB=1.65 V V_CCB=1.4 V V_CCB=1.1 V

to 3.6 V

to 2.7 V

to 1.95 V

to 1.6 V

to 1.3 V

Symbol Parameter

Units

Min. Max. Min. Max. Min. Max Min. Max.

Typ.

A to B

t_PLH,t_PHL

0.5

0.6

6.0

6.8

0.5

0.8

6.5

6.9

1.0

0.9

7.0

7.5

1.0

8.5

11.5

9.0

ns

B to A

/OE to A,

t_PZL,t_PZH

1.7

1.0

1.7

1.0

1.7

1.0

1.7

1.0

1.7

1.0

µs

ns

/OE to B

A Port,

t_SKEW

B Port⁽¹²⁾

V_CCA= 1.1 V to 1.3 V, T_A=-40 to 85°C

V_CCB=3.0 V V_CCB=2.3 V V_CCB=1.65 V V_CCB=1.4 V V_CCB=1.1 V

to 3.6 V

to 2.7 V

to 1.95 V

to 1.6 V

to 1.3 V

Symbol

Parameter

Units

Typ.

7.1

Typ.

6.5

Typ.

7.0

Typ.

7.1

Typ.

13.5

1.7

A to B

ns

µs

ns

t_PLH,t_PHL

B to A

10.3

1.7

10.5

1.7

10.8

1.7

11.3

1.7

t_PZL,t_PZH/OE to A, /OE to B

t_SKEW

A Port, B Port⁽¹²⁾

Note:

1.0

12. Skew is the variation of propagation delay betw een output signals and applies only to output signals on the same

port (A_nor B_n) and sw itching w ith the same polarity (LOW-to-HIGH or HIGH-to-LOW) (see Figure 10).

Skew is guaranteed, but not tested.

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Maximum Data Rate

T_A=-40 to 85°C.

V_CCB=3.0 V V_CCB=2.3 V V_CCB=1.65 V V_CCB=1.4 V V_CCB=1.1V to

to 3.6 V

to 2.7 V

Min.

120

to 1.95 V

Min.

100

to 1.6 V

Min.

80

1.3 V

Typ.

40

V_CCA

Units

Min.

140

120

100

80

Mbps

V_CCA=3.00 V to 3.60 V

V_CCA=2.30 V to 2.70 V

V_CCA=1.65 V to 1.95 V

V_CCA=1.40 V to 1.60 V

120

100

80

40

100

80

60

40

80

60

40

Typ.

V_CCA=1.10 V to 1.30 V

40

Mbps

Notes:

13. Maximum data rate is guaranteed, but not tested.

14. Maximum data rate is specified in megabits per second (see Figure 9). It is equivalent to tw o times the F-toggle

frequency, specified in megahertz. For example, 100 Mbps is equivalent to 50 MHz.

Capacitance

T_A=+25°C

Typical

Symbol

Parameter

Conditions

Units

pF

C

IN

Input Capacitance Control Pin (/OE) V_CCA=V_CCB=GND

A_n

Input / Output Capacitance

3

4

5

C

I/O

V_CCA=V_CCB=3.3 V, /OE=V_CCA

pF

B_n

V_CCA=V_CCB=3.3 V, V_I=0 V or V_CC

f=10 MHz

,

C_pd

Pow er Dissipation Capacitance

25

pF

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11

I/O Architecture Benefit

The FXLA102 I/O architecture benefits the end user,

beyond level translation, in the follow ing three w ays:

hold.” “Static Mode” is w hen only the bus hold drives the

channel. The bus hold can be over ridden in the event of

a

direction change. The strong driver allow s the

Auto Direction w ithout an external direction pin.

FXLA102 to quickly charge and discharge capacitive

transmission lines during dynamic mode. Static mode

conserves pow er, w here I_CCis typically < 5 µA.

Drive Capacitive Loads. Automatically shifts to a

higher current drive mode only during “Dynamic Mode”

or HL / LH transitions.

Bus Hold Minimum Drive Current

Lower Power Consumption. Automatically shifts to

low -pow er mode during “Static Mode” (no transitions),

low ering pow er consumption.

Specifies the minimum amount of current the bus hold

driver can source/sink. The bus hold minimum drive

current (II_HOLD) is V_CCdependent and guaranteed in the

DC Electrical tables. The intent is to maintain a valid

output state in a static mode, but that can be overridden

w hen an input data transition occurs.

The FXLA102 does not require a direction pin. Instead,

the I/O architecture detects input transitions on both

side and automatically transfers the data to the

corresponding output. For example, for a given channel,

if both A and B side are at a static LOW, the direction

has been established as A  B, and a LH transition

Bus Hold Input Overdrive Drive Current

Specifies the minimum amount of current required (by

an external device) to overdrive the bus hold in the

event of a direction change. The bus hold overdrive

(II_ODH, II_ODL) is V_CCdependent and guaranteed in the DC

Electrical tables.

occurs on the

B port; the FXLA102 internal I/O

architecture automatically changes direction from A  B

to B  A.

During HL / LH transitions, or “Dynamic Mode,” a strong

output driver drives the output channel in parallel w ith a

Dynamic Output Current

The strength of the output driver during LH / HL

transitions is referenced on page 8, Dynamic Output

Electrical Characteristics, I_OHD, and I_OLD

w eak output driver. After

a

typical delay of

approximately 10 ns – 50 ns, the strong driver is turned

off, leaving the w eak driver enabled for holding the logic

state of the channel. This w eak driver is called the “bus

.

www.onsemi.com

12

Test Diagrams

V

CC

TEST

DUT

SIGNAL

C1

R1

Figure 3. Test Circuit

Table 1. AC Test Conditions

Test

t_PLH, t_PHL

t_PZL

Input Signal

Data Pulses

0 V

Output Enable Control

0 V

HIGH to LOW Sw itch

t_PZH

V_CCI

Table 2. AC Load

V_CCO

C1

R1

15 pF

1.2 V 0.1 V

1.5 V 0.1 V

1.8 V  0.15 V

2.5 V  0.2 V

3.3 V  0.3 V

1 M

V

CCI

DATA

V

mi

V

IN

GND

t

pxx

V

CCO

DATA

OUT

mo

Figure 4. Waveform for Inverting and Non-Inverting Functions

Notes:

15. Input t_R= t_F= 2.0 ns, 10% to 90%.

16. Input t_R= t_F= 2.5 ns, 10% to 90%, at V_I= 3.0 V to 3.6 V only.

www.onsemi.com

13

Figure 5. 3-State Output Low Enable Time

Notes:

17. Input t_R= t_F= 2.0 ns, 10% to 90%.

18. Input t_R= t_F= 2.5 ns, 10% to 90%, at V_I= 3.0 V to 3.6 V only.

Figure 6. 3-State Output High Enable Time

Notes:

19. Input t_R= t_F= 2.0 ns, 10% to 90%.

20. Input t_R= t_F= 2.5 ns, 10% to 90%, at V_I= 3.0 V to 3.6 V only.

Table 3. Test Measure Points

Symbol

V_CC

(21)

V_MI

V_CCI/2

V_CCo/2

V_MO

V_X

V_Y

0.9 x V_CCo

0.1 x V_CCo

Note:

21. V_CCI=V_CCAfor control pin /OE or V_MI=(V_CCA/2).

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14

t

rise

V

OH

80% x V

CCO

V_OUT

20% x V

Time

CCO

V

OL

V_OUT

t

(20%  80%) V_CCO

I_OHD (C_L C_{I /O})

 (C_L C_{I /O})

t_RISE

Figure 7. Active Output Rise Time and Dynamic Output Current High

V

OH

t

fall

80% x V

CCO

V_OUT

20% x V

CCO

V

OL

Time

 (C_LC_{I /O})

V_OUT

t

(80% 20%)V_CCO

I_OLD (C_LC_{I /O})

t_FALL

Figure 8. Active Output Fall Time and Dynamic Output Current Low

t

W

V

CCI

DATA

IN

V /2

CCI

V

/2

CCI

GND

Maximum Data Rate, f = 1/t

W

Figure 9. Maximum Data Rate

V

CCO

DATA

OUTPUT

V

mo

GND

t

skew

V

CCO

DATA

OUTPUT

V

mo

V

mo

GND

Figure 10.Output Skew Time

Note:

22. t_SKEW= (t_pHLmax– t_pHLmin) or (t_pLHmax– t_pLHmin

)

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15

Physical Dimensions

2X

C

0.10

A

1.6

B

1.6

INDEX AREA

C

0.10

2X

TOP VIEW

0.55 MAX

0.05 C

Recommended Landpattern

C

0.05

0.00

C

(0.20)

0.35

0.25

DETAIL A

8X(0.09)

1.0

0.5

1

2

3

(0.1)

4

8

4

(0.15)

0.35

0.25

7

6

5

0.35

0.15

0.25

8X

DETAIL A

PIN #1 TERMINAL

SCALE: 2X

0.25

(0.2)

0.10

0.05

C A B

C

3X

BOTTOM VIEW

Notes:

1. PACKAGE CONFORMS TO JEDEC MO-255 VARIATION UAAD

2. DIMENSIONS ARE IN MILLIMETERS

3. DRAWING CONFORMS TO ASME Y.14M-1994

4. PIN 1 FLAG, END OF PACKAGE OFFSET

5. DRAWING FILE NAME: MKT-MAC08AREV4

MAC08AREV4

Figure 11.8-Lead, MicroPak™, 1.6mm Wide

Package drawings are providedas a service to customers considering ON Semiconductor components. Drawings may change in

any manner without notice. Please notethe revision and/or dateon the drawing andcontact a ON Semiconductor representative to

verify or obtain the most recent revision. Packagespecifications donot expandthe terms ofON Semiconductor’s worldwide terms and

conditions, specifically the warranty therein, which covers ON Semiconductor products.

www.onsemi.com

16

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17


型号：	FXLA102L8X
厂家：	ONSEMI
描述：	低压双电源 2 位电压转换器，带自动方向感应接口集成电路转换器
文件：	总18页 (文件大小：871K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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