FXLA104UM12X_技术文档

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FXLA104

Low-Voltage Dual-Supply 4-Bit Voltage Translator with

Configurable Voltage Supplies and Signal Levels,

3-State Outputs, and Auto Direction Sensing

Features

Description

.

Bi-Directional Interface between Two Levels:

from 1.1V to 3.6V

The FXLA104 is a configurable dual-voltage supply

translator for both uni-directional and bi-directional

voltage translation between two logic levels. The device

allows translation between voltages as high as 3.6V to

as low as 1.1V. The A port tracks the V_CCAlevel and the

B port tracks the V_CCBlevel. This allows for bi-directional

voltage translation over a variety of voltage levels: 1.2V,

1.5V, 1.8V, 2.5V, and 3.3V.

.

Fully Configurable: Inputs and Outputs Track V_CC

Non-Preferential Power-Up; Either V_CCMay Be

Powered Up First

.

Outputs Switch to 3-State if Either V_CCis at GND

Power-Off Protection

The device remains in three-state as long as either

Bus-Hold on Data Inputs Eliminates the Need for

Pull-Up Resistors; Do Not Use Pull-Up Resistors on

A or B Ports

V_CC=0V, allowing either V_CCto be powered up first.

Internal power-down control circuits place the device in

3-state if either V_CCis removed.

.

Control Input (/OE) Referenced to V_CCAVoltage

The /OE input, when HIGH, disables both the A and B

ports by placing them in a 3-state condition. The /OE

Available in 16-Terminal UMLP (1.8mm x 2.6mm)

and 12-Terminal, Quad UMLP, 1.8 x 1.8mm

Packages

input is supplied by V_CCA

.

The FXLA104 supports bi-directional translation without

the need for a direction control pin. The two ports of the

device have auto-direction sense capability. Either port

may sense an input signal and transfer it as an output

signal to the other port.

.

Direction Control Not Necessary

100Mbps Throughput when Translating Between

1.8V and 2.5V

.

ESD Protection Exceeds:

- 8kV HBM (per JESD22-A114 & Mil Std 883e

3015.7)

- 2kV CDM (per ESD STM 5.3)

Applications

.

Cell Phone, PDA, Digital Camera, Portable GPS

Ordering Information

Operating

Part Number Temperature Top Mark

Range

Packing

Package

Method

FXLA104UMX

XJ

16-Terminal UMLP 1.8 x 2.6mm Package

12-Terminal, Quad UMLP, 1.8 x 1.8mm Package

5K Units Tape

and Reel

-40 to 85°C

FXLA104UM12X

Publication Order Number:

September-2017, Rev. 2

FXLA104 /D

Pin Configuration

B0 B1 B2 B3

12

11

10

9

13

14

15

8

7

V_CCB

/OE

GND

NC

6

5

V_CCA

NC

16

1

2

3

4

A0 A1 A2 A3

Figure 1. 16-Pin UMLP (Top Through View)

Figure 2. 12-Pin UMLP (Top Through View)

Pin Definitions

16 Pin #

12 Pin #

Name

A0

Description

1

2

3

4

5

6

A-Side Inputs or 3-State Outputs

No Connect

A1

3

A2

4

A3

5

NC

GND

/OE

B3

6,7

8

7

8

Ground

Output Enable Input

9

B-Side Inputs or 3-State Outputs

B-Side Power Supply

10

11

12

13

14,15

16

10

11

12

1

B2

B1

B0

V_CCB

NC

V_CCA

No Connect

2

A-Side Power Supply

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2

Functional Diagram

Figure 3. Functional Diagram

Function Table

Control

Outputs

/OE

LOW Logic Level

HIGH Logic Level

Normal Operation

3-State

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3

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only.

Symbol

Parameter

Conditions

Min.

-0.5

Max.

4.6

Unit

V_CCA

V_CCB

V_CC

Supply Voltage

V

4.6

I/O Ports A and B

Control Input (/OE)

Output 3-State

Output Active (A_n)

Output Active (B_n)

V_IN<0V

4.6

V_I

DC Input Voltage

Output Voltage⁽²⁾

V

4.6

V_O

V_CCA+0.5

V_CCB+0.5

-50

I_IK

DC Input Diode Current

mA

V_O<0V

-50

I_OK

DC Output Diode Current

V_O>V_CC

+50

I_OH/I_OL

I_CC

DC Output Source/Sink Current

-50

-65

+50

mA

°C

DC V_CCor Ground Current (per Supply Pin)

Storage Temperature Range

Power Dissipation

±100

+150

17

T_STG

P_D

mW

Human Body Model (per JESD22-

A114 & Mil Std 883e 3015.7)

8

2

Electrostatic Discharge

Capability

ESD

kV

Charged Device Model

(per ESD STM 5.3)

Notes:

1. I_Oabsolute maximum ratings must be observed.

2. All unused inputs and input/outputs must be held at V_CCior GND.

Symbol

Parameter

Conditions

Operating V_CCAor V_CCB

Ports A and B

Min.

1.1

0

Max.

3.6

Unit

V

V_CC

Power Supply

3.6

V

V_IN

Input Voltage

Control Input (/OE)

0

V_CCA

+85

10

V

T_A

Operating Temperature, Free Air

Minimum Input Edge Rate

-40

°C

ns/V

dt/dV

V_CCA/B= 1.1 to 3.6V

UMLP-16

315

300

155

165

Thermal Resistance:

Junction-to-Ambient

°C/W

Θ_JA

Θ_JC

UMLP-12

UMLP-16

Thermal Resistance:

Junction-to-Case

UMLP-12

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4

Power-Up/Power-Down Sequence

FXL translators offer an advantage in that either V_CC

may be powered up first. This benefit derives from the

chip design. When either V_CCis at 0V, outputs are in a

high-impedance state. The control input (/OE) is

designed to track the V_CCAsupply. A pull-up resistor

tying /OE to V_CCAshould be used to ensure that bus

contention, excessive currents, or oscillations do not

occur during power-up or power-down. The size of the

pull-up resistor is based upon the current-sinking

capability of the device driving the /OE pin.

The recommended power-down sequence is:

1. Drive /OE input HIGH to disable the device.

2. Remove power from either V_CC

.

3. Remove power from other V_CC.

Pull-Up/Pull-Down Resistors

Do not use pull-up or pull-down resistors. This device

has bus-hold circuits: pull-up or pull-down resistors are

not recommended because they interfere with the

output state. The current through these resistors may

exceed the hold drive, I_I(HOLD)and/or I_I(OD)bus-hold

currents, resulting in data transition and/or auto-

direction sensing failures. The bus-hold feature

eliminates the need for extra resistors.

The recommended power-up sequence is:

1. Apply power to the first V_CC

2. Apply power to the second V_CC

3. Drive the /OE input LOW to enable the device.

.

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5

DC Electrical Characteristics

T_A=-40 to 85°C

Symbol

Parameter

Conditions

V_CCA(V)

2.70 to 3.60

2.30 to 2.70

V_CCB(V)

Min.

2.00

1.60

Typ. Max. Units

Data Inputs A_n

Control Pin /OE

V_IHA

1.65 to 2.30 1.10 to 3.60 .65xV_CCA

V

1.40 to 1.65

1.10 to 1.40

.65xV_CCA

.90xV_CCA

2.00

High-Level Input Voltage

2.70 to 3.60

2.30 to 2.70

1.60

V_IHB

V_ILA

V_ILB

Data Inputs B_n

1.10 to 3.60 1.65 to 2.30 .65xV_CCB

1.40 to 1.65 .65xV_CCB

1.10 to 1.40 .90xV_CCB

2.70 to 3.60

V

.80

.70

2.30 to 2.70

Data Inputs A_n

Control Pin /OE

1.65 to 2.30 1.10 to 3.60

1.40 to 1.65

.35xV_CCA

.10xV_CCA

.80

V

1.10 to 1.40

Low-Level Input Voltage

2.70 to 3.60

2.30 to 2.70

.70

Data Inputs B_n

1.10 to 3.60 1.65 to 2.30

1.40 to 1.65

.35xV_CCB

.10xV_CCB

1.10 to 1.40

V_OHA

V_OHB

V_OLA

V_OLB

I

_OH=-4µA

1.10 to 3.60 1.10 to 3.60 V_CCA-.4

1.10 to 3.60 1.10 to 3.60 V_CCB- .4

1.10 to 3.60 1.10 to 3.60

High-Level Output

Voltage⁽³⁾

V

I_OH=-4µA

I_OL=4µA

.4

Low-Level Output

Voltage⁽³⁾

I_OL=4µA

V_IN=0.8V

V_IN=2.0V

V_IN=0.7V

V_IN=1.6V

V_IN=0.57V

V_IN=1.07V

V_IN=0.49V

V_IN=0.91V

V_IN=0.11V

V_IN=0.99V

3.00

2.30

1.65

1.40

1.10

3.00

2.30

1.65

1.40

1.10

75.0

-75.0

45.0

-45.0

25.0

-25.0

11.0

-11.0

Bus-Hold Input Minimum

Drive Current

I_I(HOLD)

µA

4.0

-4.0

Note:

3. This is the output voltage for static conditions. Dynamic drive specifications are given in the Dynamic Output

Electrical Characteristics table.

Continued on following page…

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6

DC Electrical Characteristics (Continued)

T_A=-40 to 85°C.

Symbol

Parameter

Conditions

V_CCA(V)

3.60

V_CCB(V)

3.60

Min.

450.0

300.0

200.0

120.0

80.0

Max. Units

2.70

Bus-Hold Input

Overdrive High

Current⁽⁴⁾

I_I(ODH)

Data Inputs A_n, B_n

1.95

µA

1.60

1.40

3.60

-450.0

-300.0

-200.0

-120.0

-80.0

2.70

Bus-Hold Input

Overdrive Low

Current⁽⁵⁾

I_I(ODL)

Data Inputs A_n, B_n

1.95

µA

1.60

1.40

Control Inputs /OE,

V_I=V_CCAor GND

I_I

Input Leakage Current

1.10 to 3.60

3.60

±1.0

µA

A_nV_O=0V to 3.6V

B_nV_O=0V to 3.6V

0

3.60

0

±2.0

Power-Off Leakage

Current

I_OFF

3.60

A_n, B_nV_O=0V or 3.6V,

/OE=V_IH

3.60

0

3.60

0

±5.0

10.0

3-State Output

Leakage

A_nV_O=0V or 3.6V,

/OE=GND

I_OZ

µA

B_nV_O=0V or 3.6V,

/OE=GND

3.60

V_I=V_CCIor GND; I_O=0,

/OE=GND

I_CCA/B

I_CCZ

1.10 to 3.60 1.10 to 3.60

µA

Quiescent Supply

Current^{(6, 7)}

V_I=V_CCIor GND; I_O=0,

/OE=V_IH

V_I=V_CCBor GND; I_O=0

B-to-A Direction,

/OE=GND

0

1.10 to 3.60

-10.0

10.0

-10.0

10.0

I_CCA

µA

V_I=V_CCAor GND; I_O=0

A-to-B Direction

1.10 to 3.60

0

Quiescent Supply

Current

V_I=V_CCAor GND; I_O=0,

A-to-B Direction,

/OE=GND

0

I_CCB

V_I=V_CCBor GND; I_O=0

B-to-A Direction

1.10 to 3.60

Notes:

4. An external drive must source at least the specified current to switch LOW-to-HIGH.

5. An external drive must source at least the specified current to switch HIGH-to-LOW.

6. V_CCIis the V_CCassociated with the input side.

7. Reflects current per supply, V_CCAor V_CCB

.

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7

Dynamic Output Electrical Characteristic

A Port (A_n)

Output Load: C_L=15pF, R_L≥ MΩ (C_I/O=4pF), T_A=-40 to 85°C

V_CCA=3.0V

to 3.6V

V_CCA=2.3V

to 2.7V

V_CCA=1.65V

to 1.95V

V_CCA=1.4V

to 1.6V

V_CCA=1.1V

to 1.3V

Symbol Parameter

Units

Typ. Max. Typ. Max. Typ. Max Typ. Max.

Typ.

Output Rise

t_rise

3.0

3.5

4.0

5.0

7.5

ns

Time A Port⁽⁹⁾

Output Fall

t_fall

Time A

3.0

3.5

4.0

5.0

7.5

Port⁽¹⁰⁾

Dynamic

Output

Current

High⁽⁹⁾

I_OHD

-11.4

-7.5

-4.7

-3.2

-1.7

mA

Dynamic

Output

I_OLD

+11.4

+7.5

+4.7

+3.2

+1.7

Current

Low⁽¹⁰⁾

B Port (B_n)

Output Load: C_L=15pF, R_L≥ MΩ (C_I/O=5pF), T_A=-40 to 85°C

V_CCB=3.0V

to 3.6V

V_CCB=2.3V

to 2.7V

V_CCB=1.65V

to 1.95V

V_CCB=1.4V

to 1.6V

V_CCB=1.1V

to 1.3V

Symbol Parameter

Units

Typ. Max. Typ. Max. Typ. Max Typ. Max.

Typ.

Output Rise

t_rise

3.0

3.5

4.0

5.0

7.5

ns

Time B Port⁽⁹⁾

Output Fall

t_fall

Time B

3.0

3.5

4.0

5.0

7.5

Port⁽¹⁰⁾

Dynamic

Output

Current

High⁽⁹⁾

I_OHD

-12.0

-7.9

-5.0

-3.4

-1.8

mA

Dynamic

Output

I_OLD

+12.0

+7.9

+5.0

+3.4

+1.8

Current

Low⁽¹⁰⁾

Notes:

8. Dynamic output characteristics are guaranteed, but not tested.

9. See Figure 8.

10. See Figure 9.

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8

AC Characteristics

V_CCA= 3.0V to 3.6V, T_A=-40 to 85°C

V_CCB=3.0V

to 3.6V

V_CCB=2.3V

to 2.7V

V_CCB=1.65V

to 1.95V

V_CCB=1.4V

to 1.6V

V_CCB=1.1V

to 1.3V

Symbol Parameter

Units

Min. Max. Min. Max. Min. Max Min. Max.

Typ.

6.9

A to B

B to A

0.2

4.0

0.3

0.2

4.2

4.1

0.5

0.3

5.4

5.0

0.6

0.5

6.8

6.0

ns

t_PLH,t_PHL

4.5

/OE to A,

/OE to B

t_PZL,t_PZH

t_SKEW

1.7

0.5

1.7

0.5

1.7

0.5

1.7

1.0

1.7

1.0

µs

ns

A Port,

B Port⁽¹¹⁾

V_CCA= 2.3V to 2.7V, T_A=-40 to 85°C

V_CCB=3.0V

V_CCB=2.3V

to 2.7V

V_CCB=1.65V

to 1.95V

V_CCB=1.4V

to 1.6V

V_CCB=1.1V

to 1.3V

to 3.6V

Symbol Parameter

Units

Min. Max. Min. Max. Min. Max Min. Max.

Typ.

7.0

A to B

B to A

0.2

0.3

4.1

4.2

0.4

4.5

0.5

5.6

5.5

0.8

0.5

6.9

6.5

ns

t_PLH,t_PHL

4.8

/OE to A,

/OE to B

t_PZL,t_PZH

t_SKEW

1.7

0.5

1.7

0.5

1.7

0.5

1.7

1.0

1.7

1.0

µs

ns

A Port,

B Port⁽¹¹⁾

V_CCA= 1.65V to 1.95V, T_A=-40 to 85°C

V_CCB=3.0V

V_CCB=2.3V

to 2.7V

V_CCB=1.65V

to 1.95V

V_CCB=1.4V

to 1.6V

V_CCB=1.1V

to 1.3V

to 3.6V

Symbol Parameter

Units

Min. Max. Min. Max. Min. Max Min. Max.

Typ.

7.5

A to B

B to A

0.3

0.5

5.0

5.4

0.5

5.5

5.6

0.8

6.7

0.9

1.0

7.5

7.0

ns

t_PLH,t_PHL

t_PZL,t_PZH

5.4

/OE to A,

/OE to B

1.7

0.5

1.7

0.5

1.7

0.5

1.7

1.0

1.7

1.0

µs

ns

A Port,

t_SKEW

Note:

B Port⁽¹¹⁾

11. Skew is the variation of propagation delay between output signals and applies only to output signals on the

same port (A_nor B_n) and switching with the same polarity (LOW-to-HIGH or HIGH-to-LOW) (see Figure 11).

Skew is guaranteed, but not tested.

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9

AC Characteristics (Continued)

V_CC=1.4V to 1.6V, T_A=-40 to 85°C

V_CCB=3.0V

to 3.6V

V_CCB=2.3V

to 2.7V

V_CCB=1.65V

to 1.95V

V_CCB=1.4V

to 1.6V

V_CCB=1.1V

to 1.3V

Symbol Parameter

Units

Min. Max. Min. Max. Min. Max Min. Max.

Typ.

7.9

A to B

B to A

0.5

0.6

6.0

6.8

0.5

0.8

6.5

6.9

1.0

0.9

7.0

7.5

1.0

8.5

ns

t_PLH,t_PHL

6.1

/OE to A,

/OE to B

t_PZL,t_PZH

t_SKEW

1.7

1.0

1.7

1.0

1.7

1.0

1.7

1.0

1.7

1.0

µs

ns

A Port,

B Port⁽¹²⁾

V_CCA=1.1V to 1.3V, T_A=-40 to 85°C

V_CCB=3.0V V_CCB=2.3V V_CCB=1.65V V_CCB=1.4V V_CCB=1.1V

to 3.6V

to 2.7V

to 1.95V

to 1.6V

to 1.3V

Symbol

Parameter

Units

Typ.

4.6

Typ.

4.8

Typ.

5.4

Typ.

6.2

Typ.

9.2

A to B

B to A

ns

µs

ns

t_PLH,t_PHL

6.8

7.0

7.4

7.8

9.1

t_PZL,t_PZH/OE to A, /OE to B

t_SKEW

A Port, B Port⁽¹²⁾

Note:

1.7

1.0

12. Skew is the variation of propagation delay between output signals and applies only to output signals on the

same port (A_nor B_n) and switching with the same polarity (LOW-to-HIGH or HIGH-to-LOW) (see Figure 11).

Skew is guaranteed, but not tested.

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10

Maximum Data Rate^{(13, 14)}

T_A=-40 to 85°C

V_CCB=3.0V

to 3.6V

V_CCB=2.3V

to 2.7V

V_CCB=1.65V

to 1.95V

V_CCB=1.4V V_CCB=1.1V to

to 1.6V

Min.

80

1.3V

Typ.

40

V_CCA

Units

Min.

120

100

80

Min.

100

80

V_CCA=3.00V to 3.60V

V_CCA=2.30V to 2.70V

V_CCA=1.65V to 1.95V

V_CCA=1.40V to 1.60V

140

120

100

80

Mbps

80

40

60

40

60

40

Typ.

V_CCA=1.10V to 1.30V

40

Mbps

Notes:

13. Maximum data rate is guaranteed, but not tested.

14. Maximum data rate is specified in megabits per second (see Figure 10). It is equivalent to two times the

F-toggle frequency, specified in megahertz. For example, 100Mbps is equivalent to 50MHz.

Capacitance

T_A=+25°C

Typical

Symbol

C_IN

Parameter

Conditions

Units

pF

Input Capacitance Control Pin (/OE) V_CCA=V_CCB=GND

A_n

3

4

C_I/O

Input/Output Capacitance

V_CCA=V_CCB=3.3V, /OE=V_CCA

pF

B_n

Power Dissipation Capacitance

5

C_pd

V_CCA=V_CCB=3.3V, V_I=0V or V_CC, f=10MHz

25

pF

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11

I/O Architecture Benefit

The FXLA104 I/O architecture benefits the end user,

beyond level translation, in the following three ways:

hold.” “Static Mode” is when only the bus hold drives the

channel. The bus hold can be over ridden in the event

of a direction change. The strong driver allows the

FXLA104 to quickly charge and discharge capacitive

transmission lines during dynamic mode. Static mode

conserves power, where I_CCis typically < 5µA.

Auto Direction without an external direction pin.

Drive Capacitive Loads. Automatically shifts to a

higher current drive mode only during “Dynamic Mode”

or HL / LH transitions.

Bus Hold Minimum Drive Current

Lower Power Consumption. Automatically shifts to

low-power mode during “Static Mode” (no transitions),

lowering power consumption.

Specifies the minimum amount of current the bus hold

driver can source/sink. The bus hold minimum drive

current (II_HOLD) is V_CCdependent and guaranteed in the

DC Electrical tables. The intent is to maintain a valid

output state in a static mode, but that can be overridden

when an input data transition occurs.

The FXLA104 does not require a direction pin. Instead,

the I/O architecture detects input transitions on both

side and automatically transfers the data to the

corresponding output. For example, for a given channel,

if both A and B side are at a static LOW, the direction

has been established as A  B, and a LH transition

occurs on the B port; the FXLA104 internal I/O

architecture automatically changes direction from A  B

to B  A.

Bus Hold Input Overdrive Drive Current

Specifies the minimum amount of current required (by

an external device) to overdrive the bus hold in the

event of a direction change. The bus hold overdrive

(II_ODH, II_ODL) is V_CCdependent and guaranteed in the DC

Electrical tables.

During HL / LH transitions, or “Dynamic Mode,” a strong

output driver drives the output channel in parallel with a

Dynamic Output Current

The strength of the output driver during LH / HL

transitions is referenced on page 8, Dynamic Output

weak output driver. After

a

typical delay of

approximately 10ns – 50ns, the strong driver is turned

off, leaving the weak driver enabled for holding the logic

state of the channel. This weak driver is called the “bus

Electrical Characteristics, I_OHD, and I_OLD

.

www.onsemi.com

12

Test Diagrams

V

CC

TEST

DUT

SIGNAL

C1

R1

Figure 4. Test Circuit

Table 1.

AC Test Conditions

Test

t_PLH, t_PHL

t_PZL

Input Signal

Data Pulses

0V

Output Enable Control

0V

HIGH to LOW Switch

t_PZH

V_CCI

Table 2.

AC Load

V_CCo

C1

R1

15pF

1.2V 0.1V

1.5V 0.1V

1.8V 0.15V

2.5V 0.2V

3.3V 0.3V

1MΩ

V

CCI

DATA

IN

V

mi

V

GND

t

pxx

V

CCO

DATA

OUT

mo

Figure 5. Waveform for Inverting and Non-Inverting Functions

Notes:

15. Input t_R= t_F= 2.0ns, 10% to 90%.

16. Input t_R= t_F= 2.5ns, 10% to 90%, at V_I= 3.0V to 3.6V only.

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13

Figure 6. 3-State Output Low Enable Time for Low Voltage Logic

Notes:

17. Input t_R= t_F= 2.0ns, 10% to 90%.

18. Input t_R= t_F= 2.5ns, 10% to 90%, at V_I= 3.0V to 3.6V only.

Figure 7. 3-State Output High Enable Time for Low Voltage Logic

Notes:

19. Input t_R= t_F= 2.0ns, 10% to 90%.

20. Input t_R= t_F= 2.5ns, 10% to 90%, at V_I= 3.0V to 3.6V only.

Table 3.

Test Measure Points

Symbol

V_DD

(21)

V_MI

V_CCI/2

V_CCo/2

V_MO

V_X

V_Y

0.9 x V_CCo

0.1 x V_CCo

Note:

21. V_CCI=V_CCAfor control pin /OE or V_MI(V_CCA/2).

www.onsemi.com

14

t

rise

V

OH

80% x V

CCO

V_OUT

20% x V

Time

CCO

V

OL

ΔV_OUT

Δt

(20% − 80%) •V_CCO

I_OHD≈ (C_L+ C_{I /O})×

= (C_L+ C_{I /O})×

t_RISE

Figure 8. Active Output Rise Time and Dynamic Output Current High

V

OH

t

fall

80% x V

CCO

V_OUT

20% x V

CCO

V

OL

Time

= (C_L+ C_{I /O})×

ΔV_OUT

Δt

(80% − 20%)•V_CCO

I_OLD≈ (C_L+C_{I /O})×

t_FALL

Figure 9. Active Output Fall Time and Dynamic Output Current Low

t

W

V

CCI

DATA

IN

V

/2

CCI

V

/2

CCI

GND

Maximum Data Rate, f = 1/t

W

Figure 10.Maximum Data Rate

V

CCO

DATA

OUTPUT

V

mo

GND

t

skew

V

CCO

DATA

OUTPUT

V

mo

GND

Figure 11.Output Skew Time

Note:

22. t_SKEW= (t_pHLmax– t_pHLmin) or (t_pLHmax– t_pLHmin

)

www.onsemi.com

15

Physical Dimensions

2.10

0.563(15X)

0.10

2X

C

1.80

A

B

0.663

0.40

1

2.60

2.90

PIN#1 IDENT

0.10

C

TOP VIEW

0.225 (16X)

2X

RECOMMENDED

LAND PATTERN

0.55 MAX.

0.152

0.10

0.08

C

TERMINAL SHAPE VARIANTS

SEATING

PLANE

C

0.05

0.00

0.40

0.60

SIDE VIEW

0.30

0.50

0.15

0.25

0.15

0.25

0.10

15X

0.45

0.10

0.35

PIN 1

NON-PIN 1

5

Supplier 1

9

0.40

0.30

0.50

0.15

0.25

0.15

15X

0.25

0.30

0.50

15X

1

PIN 1

NON-PIN 1

PIN#1 IDENT

Supplier 2

13

0.25

0.15

16

0.55

0.45

0.10

0.05

C

A B

BOTTOM VIEW

R0.20

PACKAGE

EDGE

NOTES:

A. PACKAGE DOES NOT FULLY CONFORM TO

JEDEC STANDARD.

LEAD

OPTION 2

SCALE : 2X

LEAD

OPTION 1

SCALE : 2X

B. DIMENSIONS ARE IN MILLIMETERS.

C. DIMENSIONS AND TOLERANCES PER

ASME Y14.5M, 1994.

D. LAND PATTERN RECOMMENDATION IS

BASED ON FSC DESIGN ONLY.

E. DRAWING FILENAME: MKT-UMLP16Arev4.

F. TERMINAL SHAPE MAY VARY ACCORDING

TO PACKAGE SUPPLIER, SEE TERMINAL

SHAPE VARIANTS.

Figure 12.16-Lead, UMLP, QUAD, Ultra-Thin MLP, 1.8 X 2.6mm

www.onsemi.com

16

Physical Dimensions

(11X)

0.563

2.10

1.80

A

B

0.10

C

0.588

0.40

2X

1

1.80

2.10

PIN#1 IDENT

0.10 C

(12X)

0.20

TOP VIEW

2X

RECOMMENDED

LAND PATTERN

0.55 MAX.

0.152

0.10 C

0.08

0.45

0.35

C

0.10

0.05

0.00

SEATING

PLANE

C

0.10

SIDE VIEW

DETAIL A

SCALE : 2X

0.35

(11X)

NOTES:

0.45

3

6

A. PACKAGE DOES NOT FULLY CONFORM TO

JEDEC STANDARD.

0.40

B. DIMENSIONS ARE IN MILLIMETERS.

DETAIL A

C. DIMENSIONS AND TOLERANCES PER

ASME Y14.5M, 1994.

1

PIN#1 IDENT

D. LAND PATTERN RECOMMENDATION IS

BASED ON FSC DESIGN ONLY.

12

9

0.25

0.15

(12X)

BOTTOM VIEW

0.10

C A B

E. DRAWING FILENAME: MKT-UMLP12Arev4.

0.05

C

PACKAGE

EDGE

LEAD

OPTION 2

SCALE : 2X

OPTION 1

SCALE : 2X

Figure 13.12-Lead, UMLP, QUAD, JEDEC MO-252 1.8 x 1.8mm Package

www.onsemi.com

17

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型号：	FXLA104UM12X
厂家：	ONSEMI
描述：	低电压双电源 4 位电压转换器转换器
文件：	总19页 (文件大小：280K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

FXLA104UM12X [ONSEMI]

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