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July 2012

FXMA2104

Dual-Supply, 4-Bit Voltage Translator / Buffer /

Repeater / Isolator for Open-Drain Applications

Features

Description

The FXMA2104 is

a

4-bit high-performance,

.

Bi-Directional Interface between Any Two Levels:

1.65V to 5.5V

configurable dual-voltage supply, open-drain translator

for bi-directional voltage translation over a wide range of

input and output voltages levels.

.

Direction Control not Needed

System GPIO Resources Not Required when OE

Tied to V_CCA

I²C 400pF Buffer / Repeater

I²C-Bus^®Isolation

Intended for use as a voltage translator in applications

using the I²C-Bus^®interface, the input and output

voltage levels are compatible with I²C device

specification voltage levels. External pull-up resistors

are required.

.

A/B Port V_OL= 175mV (Typical), V_IL= 150mV,

I_OL= 6mA

The device is designed so that the A port tracks the

V_CCAlevel and the B port tracks the V_CCBlevel. This

allows for bi-directional A/B port voltage translation

between any two levels from 1.65V to 5.5V. V_CCAcan

equal V_CCBfrom 1.65V to 5.5V.

.

Open-Drain Inputs / Outputs

Accommodates Standard-Mode and Fast-Mode

I²C-Bus Devices

Non-preferential power-up means either V_CCcan be

powered-up first. Internal power-down control circuits

place the device in 3-state if either V_CCis removed.

.

Supports I²C Clock Stretching & Multi-Master

Fully Configurable: Inputs and Outputs Track V_CC

The two ports of the device have automatic direction-

sense capability. Either port may sense an input signal

and transfer it as an output signal to the other port.

Non-Preferential Power-Up; Either V_CCMay Be

Powered-Up First

.

Outputs Switch to 3-State if Either V_CCis at GND

Tolerant Output Enable: 5V

Packaged in 12-Lead Ultrathin MLP

(1.8mm x 1.8mm)

.

ESD Protection Exceeds:

- 5kV HBM ESD (per JESD22-A114)

- 2kV CDM (per JESD22-C101)

Ordering Information

Operating

Temperature

Range

Top

Mark

Packing

Part Number

Package

Method

5000 Units on

Tape and Reel

FXMA2104UMX

-40 to +85°C

BX

12-Lead, Ultrathin, MLP, 1.8mm x 1.8mm

FXMA2104 • Rev. 1.0.1

www.fairchildsemi.com

Block Diagram

OE

V_CCB

Dynamic Driver

Internal Direction

Generator &

Control

(with Time Out)

V_biasB

V_biasA

B

A

V_CCA

Internal Direction

Generator &

Control

Dynamic Driver

(with Time Out)

Figure 1. Block Diagram, 1 of 4 Channels

FXMA2104 • Rev. 1.0.1

www.fairchildsemi.com

2

Pin Configuration

Figure 2. UMLP (Top-Through View)

Pin Definitions

Pin #

Name

Description

1

V_CCB

V_CCA

B-Side Power Supply

A-Side Power Supply

2

3, 4, 5, 6

A₀, A_1,A₂, A₃

GND

A-Side Inputs or 3-State Outputs

Ground

7

8

OE

Output Enable Input

9, 10, 11, 12

B₃, B_2,B₁, B_0,

B-Side Inputs or 3-State Outputs

Truth Table

Control

Outputs

OE

LOW Logic Level

HIGH Logic Level

3-State

Normal Operation

Note:

1. If the OE pin is driven LOW, the FXMA2104 is disabled and the A₀, A₁, A₂, A₃, B₀, B₁, B₂and B₃pins (including

dynamic drivers) are forced into 3-state.

FXMA2104 • Rev. 1.0.1

www.fairchildsemi.com

3

Absolute Maximum Ratings

Stresses exceeding the Absolute Maximum Ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only.

Symbol

Parameter

Min.

-0.5

Max.

Units

V_CCA, V_CCBSupply Voltage

7.0

A Port

V

V_IN

DC Input Voltage

Output Voltage⁽²⁾

B Port

7.0

Control Input (OE)

A_nOutputs 3-State

B_nOutputs 3-State

A_nOutputs Active

B_nOutputs Active

At V_IN< 0V

7.0

V_O

V

V_CCA+ 0.5V

V_CCB+ 0.5V

-50

I_IK

DC Input Diode Current

DC Output Diode Current

mA

At V_O< 0V

-50

I_OK

At V_O> V_CC

+50

I_OH/ I_OL

I_CC

DC Output Source/Sink Current

-50

-65

+50

mA

mW

°C

DC V_CCor Ground Current per Supply Pin

±100

0.129

+150

5

P_D

Power Dissipation

At 400KHz

T_STG

Storage Temperature Range

Human Body Model, JESD22-A114

Charged Device Mode, JESD22-C101

Electrostatic Discharge

Capability

ESD

kV

2

Note:

2. I_Oabsolute maximum rating must be observed.

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol

Parameter

Min.

1.65

0

Max.

5.50

5.5

Units

V_CCA, V_CCBPower Supply Operating

V

A Port

V_IN

Input Voltage

B Port

0

5.5

V

Control Input (OE)

0

V_CCA

Thermal Resistance

301.5

+85

C°/W

°C

Θ_JA

T_A

Free Air Operating Temperature

-40

Note:

3. All unused inputs and I/O pins must be held at V_CCIor GND, V_CCIis the V_CCassociated with the input side.

FXMA2104 • Rev. 1.0.1

www.fairchildsemi.com

4

Functional Description

Power-Up/Power-Down Sequencing

FXM translators offer an advantage in that either V_CC

may be powered up first. This benefit derives from the

chip design. When either V_CCis at 0V, outputs are in a

high-impedance state. The control input (OE) is

designed to track the V_CCAsupply. A pull-down resistor

tying OE to GND should be used to ensure that bus

contention, excessive currents, or oscillations do not

occur during power-up/power-down. The size of the pull-

down resistor is based upon the current-sinking

capability of the device driving the OE pin.

The recommended power-up sequence is:

1. Apply power to the first V_CC

2. Apply power to the second V_CC

.

3. Drive the OE input HIGH to enable the device.

The recommended power-down sequence is:

1. Drive OE input LOW to disable the device.

2. Remove power from either V_CC

.

3. Remove power from other V_CC

.

Note:

4. Alternatively, the OE pin can be hardwired to V_CCA

to save GPIO pins. If OE is hardwired to V_CCA

either V_CCcan be powered up or down first.

,

Application Circuit

Figure 3. Application Circuit

FXMA2104 • Rev. 1.0.1

www.fairchildsemi.com

5

Application Information

The FXMA2104 has open-drain I/Os and requires

external pull-up resistors on the eight data I/O pins, as

shown in Figure 3. If a pair of data I/O pins (A_n/B_n) is not

used, both pins should be tied to GND (or both to V_CC).

In this case, pull-down or pull-up resistors are not

required. The recommended values for the pull-up

resistors (RPUs) are 1KΩ to 10K, depending on the total

bus capacitance, the user is free to vary the pull-up

resistor value to meet the maximum I²C edge rate per

the I²C specification (UM10204 rev. 03, June 19, 2007).

For example, the maximum edge rate (30% - 70%)

during Fast Mode (400kbit/s) is 300ns. If bus

capacitance is approaching the maximum 400pF, lower

the RPU value to keep the rise time below 300ns (Fast

Mode). Section 7.1 of the I²C specification provides an

excellent guideline for pull-up resistor sizing.

between the ports until either of the port’s V_CC/2

thresholds are reached. After the RC time constant has

reached the V_CC/2 threshold of either port, the port’s

edge detector triggers both dynamic drivers to drive

their respective ports in the LOW-to-HIGH (LH)

direction, accelerating the rising edge. The resulting rise

time resembles the scope shot in Figure 4. Effectively,

two distinct slew rates appear in rise time. The first slew

rate (slower) is the RC time constant of the bus. The

second slew rate (much faster) is the dynamic driver

accelerating the edge.

If both the A and B ports of the translator are HIGH, a

high-impedance path exists between the A and B ports

because both the Npassgates are turned off. If a master

or slave device decides to pull SCL or SDA LOW, that

device’s driver pulls down (I_sink) SCL or SDA until the

edge reaches the A or B port V_CC/2 threshold. When

either the A or B port threshold is reached, the port’s

edge detector triggers both dynamic drivers to drive

their respective ports in the HIGH-to-LOW (HL)

direction, accelerating the falling edge.

Theory of Operation

The FXMA2104 is designed for high-performance level

shifting and buffer / repeating in an I²C application.

Figure 1 shows that each bi-directional channel contains

two series-Npassgates and two dynamic drivers. This

hybrid architecture is highly beneficial in an I²C

application where auto-direction is a necessity.

For example, during the following three I²C protocol

events:

.

Clock Stretching

Slave’s ACK Bit (9^thbit = 0) following a Master’s

Write Bit (8^thbit = 0)

.

Clock Synchronization and Multi Master

Arbitration

the bus direction needs to change from master-to-slave

to slave-to-master without the occurrence of an edge. If

there is an I²C translator between the master and slave

in these examples, the I²C translator must change

direction when both A and B ports are LOW. The

Npassgates can accomplish this task very efficiently

because, when both A and B ports are LOW, the

Npassgates act as a low resistive short between the two

(A and B) ports.

Due to I²C’s open-drain topology, I²C masters and

slaves are not push-pull drivers. Logic LOWs are “pulled

down” (I_sink), while logic HIGHs are “let go” (3-state). For

example, when the master lets go of SCL (SCL always

comes from the master), the rise time of SCL is largely

determined by the RC time constant, where R = R_PUand

C = the bus capacitance. If the FXMA2104 is attached

to the master [on the A port] and there is a slave on the

B port, the Npassgates act as a low resistive short

Figure 4. Waveform C: 600pF, Total R_PU: 2.2KΩ

FXMA2104 • Rev. 1.0.1

www.fairchildsemi.com

6

V_OLvs. I_OL

Buffer / Repeater Performance

The I²C specification mandates a maximum V_IL(I_OLof

3mA) of V_CC• 0.3 and a maximum V_OLof 0.4V. If there

is a master on the A port of an I²C translator with a V_CC

of 1.65V and a slave on the I²C translator B port with a

V_CCof 3.3V, the maximum V_ILof the master is (1.65V x

0.3) 495mV. The slave could legally transmit a valid

logic LOW of 0.4V to the master.

If the I²C translator’s channel resistance is too high, the

voltage drop across the translator could present a V_ILto

the master greater than 495mV. To complicate matters,

the I²C specification states that 6mA of I_OLis

recommended for bus capacitances approaching

400pF. More I_OLincreases the voltage drop across the

I²C translator. The I²C application benefits when I²C

translators exhibit low V_OLperformance. Figure 5

depicts typical FXMA2104 V_OLperformance vs. a

competitor, given a 0.4V V_IL.

The FXMA2104 dynamic drivers have enough current-

sourcing capability to drive a 400pF capacitive bus. This

is beneficial when an I²C buffer / repeater is required.

The I²C specification stipulates

a maximum bus

capacitance of 400pF. If an I²C segment exceeds

400pF, an I²C buffer / repeater is required to split the

segment into two segments, each of which is less than

400pF. Figure 4 is a scope shot of an FXMA2104

driving a lumped load of 600pF. Notice the (30% - 70%)

rise time is only 112ns (total R_PU= 2.2K). This is well

below the maximum edge rate of 300ns. Not only does

the FXMA2104 drive 400Pf; it also provides excellent

headroom below the I²C specification maximum edge

rate of 300ns.

V_OL: FXMA2104 vs. Device B, V_IL= 0.4V

0.65

0.6

0.55

0.5

Device B

VIL = 0.4V

FXMA2104

VIL = 0.4V

0.45

0.4

0

2

4

6

8

10

I_OL(mA):

Figure 5. V_OLvs. I_OL

FXMA2104 • Rev. 1.0.1

www.fairchildsemi.com

7

condition from slave #2 to slave #1 as well as the

master. However, if the OE pin is pulled LOW

(disabled), both ports (A and B) are 3-stated. This

results in the FXMA2104 isolating slave #2 from the

master and slave #1, allowing full communication

between the master and slave #1.

I²C Bus Isolation

The FXMA2104 supports I²C-Bus^®isolation for the

following conditions:

. Bus isolation if bus clear

. Bus isolation if either V_CCgoes to ground

Bus Clear

Either V_CCto GND

If slave #2 is a camera that is suddenly removed from

the I²C bus, resulting in V_CCBtransitioning from a valid

V_CC(1.65V – 5.5V) to 0V; the FXMA2104 automatically

forces all I/Os on both its A and B ports into 3-state.

Once V_CCBhas reached 0V, full I²C communication

between the master and slave #1 remains undisturbed.

Because the I²C specification defines the minimum SCL

frequency of DC, the SCL signal can be held LOW

forever; however, this condition shuts down the I²C bus.

The I²C specification refers to this condition as Bus

Clear. In Figure 6, if slave #2 holds down SCL forever,

the master and slave #1 are not able to communicate

because the FXMA2104 passes the SCL stuck-LOW

Slave#1

V_CC= 3.3V

V_CC= 1.8V

VCCA

VCCB

SCL1

SDA

SCL1

SDA

SCL1

Slave#2

1

SDA1

1

SDA

V_CC= 3.3V

FXMA2104

I2

V_CC= 1.8V

C Buffer

Master

Translator

SCL2

SDA 2

SCL2

SDA2

Slave #3

OE

SDA2

SDA 2

OE: High Enable

Low Disable

GPIO3

V_CCA

:

V_CCB:

1.65V – 5.5V V_CC

Domain

1.65V – 5.5V V_CC

Domain

Figure 6. Bus Isolation

FXMA2104 • Rev. 1.0.1

www.fairchildsemi.com

8

DC Electrical Characteristics

T_A= –40°C to +85°C.

Symbol

Parameter

Condition

V_CCA(V) V_CCB(V)

Min.

Max.

Unit

Data Inputs A_n

1.65–5.50 1.65–5.50 V_CCA– 0.4

1.65–5.50 1.65–5.50 0.7 x V_CCA

High Level Input

Voltage A

V_IHA

V

Control Input OE

High Level Input

Voltage B

V_IHB

V_ILA

V_ILB

Data Inputs B_n

1.65–5.50 1.65–5.50 V_CCB– 0.4

V

Data Inputs A_n

1.65–5.50 1.65–5.50

0.4

Low Level Input

Voltage A

Control Input OE

0.3 x V_CCA

Low Level Input

Voltage B

Data Inputs B_n

V_IL= 0.15V

1.65–5.50 1.65–5.50

0.4

Low Level Output

Voltage

V_OL

V

I_OL= 6mA

Input Leakage

Current

Control Input OE,

I_L

±1

±2

5

µA

V_IN= V_CCAor GND

V

5.5V

_INor V_O= 0V to

A_n

0

5.50

0

Power-Off Leakage

Current

I_OFF

µA

V_INor V_O= 0V to

5.5V

B_n

5.50

0

A_n, V_O= 0V to 5.5V,

B_nOE = V_IL

5.50

0

3-State Output

Leakage⁽⁶⁾

V_O= 0V to 5.5V,

A_n

I_OZ

OE = Don’t Care

V_O= 0V to 5.5V,

B_n

5.50

OE = Don’t Care

Quiescent Supply

Current^(7,8)

V_IN= V_CCIor GND,

I_O= 0

I_{CCA B}

/

1.65–5.50 1.65–5.50

µA

V_IN= V_CCIor GND,

Quiescent Supply

Current⁽⁷⁾

I_CCZ

I_O= 0,

OE = V_IL

5

V_IN= 5.5V or GND,

I_O= 0,

OE = Don’t Care,

B_nto A_n

0

1.65–5.50

-2

2

Quiescent Supply

Current⁽⁶⁾

I_CCA

µA

1.65–5.50

0

V_IN= 5.5V or GND,

I_O= 0,

OE = Don’t Care,

A_nto B_n

-2

2

Quiescent Supply

Current⁽⁶⁾

I_CCB

1.65–5.50

Notes:

5. This table contains the output voltage for static conditions. Dynamic drive specifications are given in Dynamic

Output Electrical Characteristics.

6. “Don’t Care” indicates any valid logic level.

7.

V_CCIis the V_CCassociated with the input side.

8. Reflects current per supply, V_CCAor V_CCB

.

FXMA2104 • Rev. 1.0.1

www.fairchildsemi.com

9

Dynamic Output Electrical Characteristics

Output Rise / Fall Time

Output load: C_L= 50pF, R_PU= 2.2kΩ, push / pull driver, and T_A= -40°C to +85°C.

(10)

V_CCO

4.5 to 5.5V 3.0 to 3.6V 2.3 to 2.7V 1.65 to 1.95V

Symbol

Parameter

Unit

Typical

t_rise

t_fall

Output Rise Time; A Port, B Port⁽¹¹⁾

Output Fall Time; A Port, B Port⁽¹²⁾

3

4

8

5

6

7

4

ns

11

Notes:

9. Output rise and fall times guaranteed by design simulation and characterization; not production tested.

10. _CCOis the V_CCassociated with the output side.

V

11. See Figure 11.

12. See Figure 12.

)

Maximum Data Rate⁽¹³

Output load: C_L= 50pF, R_PU= 2.2kΩ, push-pull driver, and T_A= -40°C to +85°C.

V_CCB

V_CCA

Direction

4.5 to 5.5V

3.0 to 3.6V

2.3 to 2.7V

1.65 to 1.95V Unit

Minimum

A to B

B to A

A to B

B to A

A to B

B to A

A to B

B to A

26

20

16

9

4.5V to 5.5V

3.0V to 3.6V

2.3V to 2.7V

MHz

9

MHz

9

MHz

9

1.65V to 1.95V

MHz

9

Note:

13. F-toggle guaranteed by design simulation; not production tested.

www.fairchildsemi.com

FXMA2104 • Rev. 1.0.1

10

AC Characteristics⁽¹⁷⁾

Output Load: C_L= 50pF, R_PU= 2.2kΩ, and T_A= -40°C to +85°C.

V_CCB

3.0 to 3.6V 2.3 to 2.7V 1.65 to 1.95V Units

Typ. Max. Typ. Max. Typ. Max. Typ. Max.

Symbol

Parameter

4.5 to 5.5V

V_CCA= 4.5 to 5.5V

A to B

t_PLH

1

3

1

2

3

4

1

3

5

1

4

3

7

ns

B to A

A to B

t_PHL

2

4

3

5

4

6

7

B to A

2

4

2

5

2

6

5

7

OE to A

t_PZL

4

5

6

10

7

5

9

7

15

105

16

1.0

OE to B

3

5

4

5

8

10

65

9

OE to A

t_PLZ

65

5

100

9

65

6

105

10

1.0

65

7

105

12

1.0

ns

OE to B

t_skew

A Port, B Port⁽¹⁴⁾

0.5

1.5

0.5

V_CCA= 3.0 to 3.6V

A to B

t_PLH

2.0

1.5

2

5.0

3.0

4

1.5

2

3.0

4.0

4

1.5

2.0

2

3.0

6.0

5

1.5

3.0

6

3.0

9.0

7

ns

B to A

A to B

t_PHL

B to A

2

4

2

4

2

5

3

5

OE to A

t_PZL

4

8

5

9

6

11

115

10

1.0

7

15

14

115

15

1.0

OE to B

4

8

6

9

8

10

100

9

OE to A

t_PLZ

100

5

115

10

1.5

100

4

115

8

100

5

ns

OE to B

t_skew

A Port, B Port⁽¹⁴⁾

0.5

1.0

0.5

V_CCA= 2.3 to 2.7V

A to B

t_PLH

2.5

1.5

2

5.0

3.0

5

2.5

2.0

2

5.0

4.0

5

2.0

3.0

2

4.0

6.0

5

1.0

5.0

5

3.0

10.0

6

ns

B to A

A to B

t_PHL

B to A

2

5

2

5

2

5

3

6

OE to A

t_PZL

5

10

5

10

6

12

9.0

100

12

0.5

18.0

115

25

OE to B

4.0

100

65

0.5

8.0

115

110

1.5

4.5

100

65

0.5

9.0

115

110

1.0

5.0

100

65

0.5

10.0

115

1.0

OE to A

t_PLZ

ns

OE to B

t_skew

A Port, B Port⁽¹⁴⁾

1.0

V_CCA= 1.65 to 1.95V

A to B

t_PLH

4.0

1.0

5

7.0

2.0

8

40.

1.0

3

7.0

2.0

7

5.0

1.5

3

8.0

3.0

7

5.0

8

10.0

9

ns

B to A

A to B

t_PHL

B to A

4

8

3

7

3

7

3

7

OE to A

t_PZL

11

6

15

14

115

1.5

11

6

14

115

1.0

14

6

28

14

115

1.0

14

9

23

OE to B

19

OE to A

t_PLZ

75

0.5

75

0.5

75

0.5

75

0.5

115

1.0

ns

OE to B

t_skew

A Port, B Port⁽¹⁴⁾

Note:

14. Skew is the variation of propagation delay between output signals and applies only to output signals on the same

port (A_nor B_n) and switching with the same polarity (LOW-to-HIGH or HIGH-to-LOW) (see Figure 14). Skew is

guaranteed, but not tested.

15. AC Characteristic is guaranteed by Design and Characterization.

FXMA2104 • Rev. 1.0.1

www.fairchildsemi.com

11

Capacitance

T_A= +25°C.

Symbol

Parameter

Condition

Typical Unit

C_IN

C_I/O

C_pd

Input Capacitance Control Pin (OE) V_CCA= V_CCB= GND

2.2

pF

Input / Output Capacitance, A_n, B_n

Power Dissipation Capacitance

V_CCA= V_CCB= 5.0V, OE = GND

13.0

13.5

V_CCA= V_CCB= 5.0V, V_IN= 0V or V_CC, f = 400KHz

Figure 7. AC Test Circuit

Table 1. Propagation Delay Table⁽¹⁷⁾

Test

Input Signal

Output Enable Control

V_CCA

t_PLH, t_PHL

Data Pulses

t_PZL(OE to A_n, B_n)

t_PLZ(OE to A_n, B_n)

0V

LOW to HIGH Switch

HIGH to LOW Switch

Table 2. AC Load Table

V_CCO

C_L

R_L

1.8 ± 0.15V

2.5 ± 0.2V

3.3 ± 0.3V

5.0 ± 0.5V

50pF

2.2kΩ

FXMA2104 • Rev. 1.0.1

www.fairchildsemi.com

12

Timing Diagrams

V

CCI

DATA

IN

V

CCA

V

mi

OUTPUT

CONTROL

V

mi

GND

t

pxx

PZL

DATA

OUT

V

CCO

V

DATA

OUT

Y

V

OL

mo

Figure 8. Waveform for Inverting and Non-Inverting

Functions⁽¹⁶⁾

Figure 9. 3-STATE Output Low Enable Time⁽¹⁶⁾

V

CCA

Symbol

V_mi

V_CC

OUTPUT

V

mi

CONTROL

GND

V_CCI/ 2

t

PLZ

V_mo

V_CCO/ 2

0.5 x V_CCO

0.1 x V_CCO

DATA

OUT

V

V_X

x

V

OL

V_Y

Figure 10. 3-STATE Output High Enable Time⁽¹⁶⁾

Figure 11. Active Output Rise Time

Figure 12. Active Output Fall Time

V

CCO

DATA

OUTPUT

V

mo

GND

t

period

t

skew

V

CCI

DATA

IN

V

/ 2

V

/ 2

CCI

V

CCO

GND

DATA

OUTPUT

V

mo

F-toggle rate, f = 1 / t

period

GND

t

= (t

– t

)

(t

– t

)

skew

pHLmax pHLmin or pLHmax pLHmin

Figure 13. F-Toggle Rate

Figure 14. Output Skew Time

Notes:

16. Input t_R= t_F= 2.0ns, 10% to 90% at V_IN= 1.65V to 1.95V;

Input t_R= t_F= 2.0ns, 10% to 90% at V_IN= 2.3 to 2.7V;

Input t_R= t_F= 2.5ns, 10% to 90%, at V_IN= 3.0V to 3.6V only;

Input t_R= t_F= 2.5ns, 10% to 90%, at V_IN= 4.5V to 5.5 only.

17. V_CCI= V_CCAfor control pin OE or V_mi= (V_CCA/ 2).

www.fairchildsemi.com

FXMA2104 • Rev. 1.0.1

13

Physical Dimensions

(11X)

0.563

2.10

1.80

A

B

0.10

C

0.588

0.40

2X

1

1.80

2.10

PIN#1 IDENT

0.10 C

(12X)

0.20

TOP VIEW

2X

RECOMMENDED

LAND PATTERN

0.55 MAX.

0.152

0.10 C

0.08

0.45

0.35

C

0.10

0.05

0.00

SEATING

PLANE

C

0.10

SIDE VIEW

DETAIL A

SCALE : 2X

0.35

(11X)

NOTES:

0.45

3

6

A. PACKAGE DOES NOT FULLY CONFORM TO

JEDEC STANDARD.

0.40

B. DIMENSIONS ARE IN MILLIMETERS.

DETAIL A

C. DIMENSIONS AND TOLERANCES PER

ASME Y14.5M, 1994.

1

PIN#1 IDENT

D. LAND PATTERN RECOMMENDATION IS

BASED ON FSC DESIGN ONLY.

12

9

0.25

0.15

(12X)

BOTTOM VIEW

0.10

C A B

E. DRAWING FILENAME: MKT-UMLP12Arev4.

0.05

C

PACKAGE

EDGE

LEAD

OPTION 2

SCALE : 2X

OPTION 1

SCALE : 2X

Figure 15. 12-Lead Ultrathin MLP, 1.8mm x 1.8mm

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the

warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

FXMA2104 • Rev. 1.0.1

www.fairchildsemi.com

14

FXMA2104 • Rev. 1.0.1

www.fairchildsemi.com

15

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent

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1


型号：	FXMA2104UMX
厂家：	ONSEMI
描述：	双电源、4位电源转换器/缓冲器/中继器/隔离器，用于开路漏极应用中继器接口集成电路转换器
文件：	总17页 (文件大小：1619K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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