HUF76407D3ST [ONSEMI]
N 沟道，逻辑电平，UltraFET 功率 MOSFET，60V，11A，107mΩ;
| 型号： | HUF76407D3ST |
| 厂家： | 
ONSEMI |
| 描述： | N 沟道，逻辑电平，UltraFET 功率 MOSFET，60V，11A，107mΩ 开关 晶体管 |
| 文件： | 总12页 (文件大小：796K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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HUF76407D3S
Data Sheet
October 2013
N-Channel Logic Level UltraFET Power MOSFET
60 V, 11 A, 107 mΩ
Packaging
JEDEC TO-252AA
Features
DRAIN
• Ultra Low On-Resistance
(FLANGE)
- r
- r
= 0.092Ω, V = 10V
GS
DS(ON)
DS(ON)
= 0.107Ω, V = 5V
GS
GATE
• Simulation Models
SOURCE
- Temperature Compensated PSPICE® and SABER™
Electrical Models
- Spice and SABER Thermal Impedance Models
- www.fairchildsemi.com
Symbol
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
D
• Switching Time vs R
GS
Curves
G
Ordering Information
S
PART NUMBER
PACKAGE
TO-252AA
BRAND
76407D
HUF76407D3ST
o
Absolute Maximum Ratings
T
= 25 C, Unless Otherwise Specified
C
HUF76407D3ST
UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
60
60
16
V
V
V
DSS
Drain to Gate Voltage (R
= 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
DGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
Drain Current
o
Continuous (T = 25 C, V
C
= 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
= 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
11
12
6
6
A
A
A
A
GS
GS
D
D
D
o
Continuous (T = 25 C, V
C
o
o
Continuous (T = 135 C, V
= 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
= 4.5V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
C
GS
GS
Continuous (T = 135 C, V
C
D
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
Figure 4
DM
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .UIS
Figures 6, 14, 15
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
Derate Above 25 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
38
0.25
-55 to 175
W
D
o
o
W/ C
o
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T , T
C
J
STG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T
Package Body for 10s, See Techbrief TB334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
o
o
300
260
C
C
L
pkg
NOTE:
1. T = 25 C to 150 C.
o
o
J
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
For severe environments, see our Automotive HUFA series.
©2001 Fairchild Semiconductor Corporation
HUF76407D3S Rev. C0
HUF76407D3S
o
Electrical Specifications
T = 25 C, Unless Otherwise Specified
C
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
BV
I
I
= 250µA, V
= 250µA, V
= 0V (Figure 12)
o
60
55
-
-
-
-
-
-
-
-
V
DSS
D
GS
GS
GS
GS
= 0V , T = -40 C (Figure 12)
C
V
D
I
V
V
V
= 55V, V
= 50V, V
= 0V
= 0V, T = 150 C
1
µA
µA
nA
DSS
DS
DS
GS
o
-
250
100
C
Gate to Source Leakage Current
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
Drain to Source On Resistance
I
=
16V
-
GSS
V
V
= V , I = 250µA (Figure 11)
1
-
-
3
V
Ω
Ω
Ω
GS(TH)
GS
DS
D
r
I
I
I
= 13A, V
= 10V (Figures 9, 10)
0.077
0.095
0.107
0.092
0.107
0.117
DS(ON)
D
D
D
GS
= 8A, V
= 8A, V
= 5V (Figure 9)
-
GS
GS
= 4.5V (Figure 9)
-
THERMAL SPECIFICATIONS
o
Thermal Resistance Junction to Case
R
R
TO-252
-
-
-
-
3.94
100
C/W
θJC
o
Thermal Resistance Junction to
Ambient
C/W
θJA
SWITCHING SPECIFICATIONS (V
Turn-On Time
= 4.5V)
GS
t
V
V
= 30V, I = 8A
-
-
-
-
-
-
-
8
170
ns
ns
ns
ns
ns
ns
ON
DD
GS
D
= 4.5V, R
= 32Ω
GS
Turn-On Delay Time
Rise Time
t
-
-
d(ON)
(Figures 15, 21, 22)
t
105
22
39
-
r
Turn-Off Delay Time
Fall Time
t
-
d(OFF)
t
-
f
Turn-Off Time
t
92
OFF
SWITCHING SPECIFICATIONS (V
Turn-On Time
= 10V)
t
GS
V
V
R
= 30V, I = 13A
D
= 10V,
= 32Ω
-
-
-
-
-
-
-
56
ns
ns
ns
ns
ns
ns
ON
DD
GS
GS
Turn-On Delay Time
Rise Time
t
5
-
d(ON)
t
32
43
45
-
-
r
(Figures 16, 21, 22)
Turn-Off Delay Time
Fall Time
t
-
-
d(OFF)
t
f
Turn-Off Time
t
132
OFF
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Q
V
V
V
= 0V to 10V
= 0V to 5V
= 0V to 1V
V
= 30V,
-
-
-
-
-
9.4
5.2
11.3
6.2
0.43
-
nC
nC
nC
nC
nC
g(TOT)
GS
GS
GS
DD
= 8A,
I
I
D
Gate Charge at 5V
Q
g(5)
= 1.0mA
g(REF)
Threshold Gate Charge
Q
0.36
1.2
g(TH)
(Figures 14, 19, 20)
Gate to Source Gate Charge
Reverse Transfer Capacitance
CAPACITANCE SPECIFICATIONS
Input Capacitance
Q
gs
gd
Q
2.5
-
C
V
= 25V, V = 0V,
GS
-
-
-
350
105
23
-
-
-
pF
pF
pF
ISS
DS
f = 1MHz
(Figure 13)
Output Capacitance
C
OSS
RSS
Reverse Transfer Capacitance
C
Source to Drain Diode Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
1.25
1.0
UNITS
V
Source to Drain Diode Voltage
V
I
I
I
I
=8A
-
-
-
-
-
-
-
-
SD
SD
SD
SD
SD
= 3A
V
Reverse Recovery Time
t
= 8A, dI /dt = 100A/µs
SD
66
ns
rr
Reverse Recovered Charge
Q
= 8A, dI /dt = 100A/µs
SD
159
nC
RR
©2001 Fairchild Semiconductor Corporation
HUF76407D3S Rev. C0
HUF76407D3S
Typical Performance Curves
1.2
1.0
0.8
0.6
0.4
0.2
0
15
10
5
V
= 10V
GS
V
= 4.5V
GS
0
0
25
50
75
100
150
175
125
o
25
50
75
100
125
150
175
o
T
, CASE TEMPERATURE ( C)
T , CASE TEMPERATURE ( C)
C
C
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
2
DUTY CYCLE - DESCENDING ORDER
0.5
1
0.2
0.1
0.05
0.02
0.01
P
DM
0.1
t
1
t
2
NOTES:
DUTY FACTOR: D = t /t
1
2
SINGLE PULSE
PEAK T = P
x Z
x R + T
J
DM
θJC
θJC
C
0.01
-5
-4
10
-3
10
-2
10
-1
10
0
1
10
10
10
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
200
100
o
= 25 C
T
C
FOR TEMPERATURES
o
ABOVE 25 C DERATE PEAK
CURRENT AS FOLLOWS:
175 - T
150
C
I = I
25
V
= 5V
GS
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
1
10
10
t, PULSE WIDTH (s)
FIGURE 4. PEAK CURRENT CAPABILITY
©2001 Fairchild Semiconductor Corporation
HUF76407D3S Rev. C0
HUF76407D3S
Typical Performance Curves (Continued)
100
100
If R = 0
= (L)(I )/(1.3*RATED BV
t
- V )
DD
AV
If R ≠ 0
= (L/R)ln[(I *R)/(1.3*RATED BV
AS
DSS
t
AV
- V ) +1]
DD
AS DSS
100µs
10
o
STARTING T = 25 C
J
10
OPERATION IN THIS
AREA MAY BE
1ms
o
STARTING T = 150 C
J
1
LIMITED BY r
DS(ON)
10ms
SINGLE PULSE
= MAX RATED T = 25 C
o
T
J
C
0.1
1
0.001
1
10
, DRAIN TO SOURCE VOLTAGE (V)
100
200
0.01
0.1
1
10
t
,TIME IN AVALANCHE (ms)
V
AV
DS
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
15
15
V
= 10V
= 5V
PULSE DURATION = 80µs
GS
DUTY CYCLE = 0.5% MAX
V
V
= 15V
GS
DD
12
9
12
9
V
= 4V
GS
V
= 3.5V
GS
o
6
6
T
= 25 C
J
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
3
0
3
o
T
= 175 C
J
o
V
= 3V
T
= -55 C
o
GS
J
T
= 25 C
c
0
2
3
4
5
0
1
2
3
4
V
, GATE TO SOURCE VOLTAGE (V)
V
, DRAIN TO SOURCE VOLTAGE (V)
GS
DS
FIGURE 7. TRANSFER CHARACTERISTICS
FIGURE 8. SATURATION CHARACTERISTICS
150
120
90
2.5
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
C
PULSE DURATION = 80µs
I
= 12A
I
= 3A
D
D
DUTY CYCLE = 0.5% MAX
o
T
= 25 C
I
= 5A
D
2.0
1.5
1.0
0.5
V
= 10V, I = 12A
D
GS
60
-80
-40
0
40
80
120
160
200
2
4
6
8
10
o
V
, GATE TO SOURCE VOLTAGE (V)
GS
T , JUNCTION TEMPERATURE ( C)
J
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
FIGURE 10. NORMALIZED DRAINTO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
©2001 Fairchild Semiconductor Corporation
HUF76407D3S Rev. C0
HUF76407D3S
Typical Performance Curves (Continued)
1.2
1.1
1.0
0.9
1.2
I
= 250µA
D
V
= V , I = 250µA
DS
GS
D
1.0
0.8
0.6
-80
-40
0
40
80
120
160
200
-80
-40
0
40
80
120
160
200
o
o
T , JUNCTION TEMPERATURE ( C)
T , JUNCTION TEMPERATURE ( C)
J
J
FIGURE 11. NORMALIZED GATETHRESHOLDVOLTAGE vs
JUNCTION TEMPERATURE
FIGURE 12. NORMALIZED DRAINTO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
10
1000
V
= 30V
DD
C
= C
+ C
ISS
GS GD
8
6
4
2
0
C
≅ C
DS
+ C
GD
OSS
100
WAVEFORMS IN
DESCENDING ORDER:
I
I
I
= 12A
= 5A
= 3A
D
D
D
V
= 0V, f = 1MHz
1.0
GS
C
= C
GD
RSS
10
0
2
4
6
8
10
60
0.1
10
Q , GATE CHARGE (nC)
g
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 14. GATE CHARGEWAVEFORMS FOR CONSTANT
GATE CURRENT
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
150
80
V
= 4.5V, V
DD
= 30V, I = 6A
D
V
= 10V, V = 30V, I = 12A
DD D
GS
GS
t
r
60
40
100
50
0
t
t
f
t
f
t
r
t
d(OFF)
20
0
d(OFF)
t
d(ON)
t
d(ON)
0
10
20
30
40
50
0
10
R , GATE TO SOURCE RESISTANCE (Ω)
GS
20
30
40
50
R
, GATE TO SOURCE RESISTANCE (Ω)
GS
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
FIGURE 16. SWITCHING TIME vs GATE RESISTANCE
©2001 Fairchild Semiconductor Corporation
HUF76407D3S Rev. C0
HUF76407D3S
Test Circuits and Waveforms
V
DS
BV
DSS
L
t
P
V
DS
I
VARY t TO OBTAIN
P
AS
+
V
DD
R
REQUIRED PEAK I
AS
G
V
DD
-
V
GS
DUT
t
P
I
AS
0V
0
0.01Ω
t
AV
FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 18. UNCLAMPED ENERGY WAVEFORMS
V
DS
V
Q
DD
R
g(TOT)
L
V
DS
V
= 10V
GS
V
Q
GS
g(5)
+
-
V
DD
V
= 5V
V
GS
GS
DUT
V
= 1V
GS
I
0
g(REF)
Q
g(TH)
Q
Q
gd
gs
I
g(REF)
0
FIGURE 19. GATE CHARGE TEST CIRCUIT
FIGURE 20. GATE CHARGE WAVEFORMS
V
t
t
DS
ON
OFF
t
d(OFF)
t
d(ON)
t
t
f
R
L
r
V
DS
90%
90%
+
V
GS
V
DD
10%
10%
0
-
DUT
90%
50%
R
GS
V
GS
50%
PULSE WIDTH
10%
V
GS
0
FIGURE 21. SWITCHING TIME TEST CIRCUIT
FIGURE 22. SWITCHING TIME WAVEFORM
©2001 Fairchild Semiconductor Corporation
HUF76407D3S Rev. C0
HUF76407D3S
PSPICE Electrical Model
.SUBCKT HUF76407 2 1 3 ;
rev 28June 1999
CA 12 8 3.9e-9
CB 15 14 4.9e-9
CIN 6 8 3.25e-10
LDRAIN
DPLCAP
10
DRAIN
2
5
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
RLDRAIN
RSLC1
51
DBREAK
+
RSLC2
5
51
EBREAK 11 7 17 18 67.8
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
ESLC
11
-
50
+
-
17
18
-
DBODY
RDRAIN
6
ESG
8
EBREAK
EVTHRES
+
+
16
21
-
19
8
MWEAK
LGATE
EVTEMP
+
IT 8 17 1
RGATE
GATE
1
6
-
18
22
MMED
9
LDRAIN 2 5 1.0e-9
LGATE 1 9 5.42e-9
LSOURCE 3 7 2.57e-9
20
MSTRO
8
RLGATE
LSOURCE
CIN
SOURCE
3
7
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RSOURCE
RLSOURCE
S1A
S2A
RBREAK
12
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 3.7e-2
RGATE 9 20 3.37
RLDRAIN 2 5 10
RLGATE 1 9 54.2
RLSOURCE 3 7 25.7
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 2.50e-2
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
15
13
8
14
13
17
18
RVTEMP
19
-
S1B
S2B
13
CB
CA
IT
14
+
+
VBAT
6
8
5
8
EGS
EDS
+
-
-
8
22
RVTHRES
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*30),3))}
.MODEL DBODYMOD D (IS = 1.75e-13 RS = 1.75e-2 TRS1 = 1e-4 TRS2 = 5e-6 CJO = 5.9e-10 TT = 5.45e-8 N = 1.03 M = 0.6)
.MODEL DBREAKMOD D (RS = 6.50e-1 TRS1 = 1.25e-4 TRS2 = 1.34e-6)
.MODEL DPLCAPMOD D (CJO = 3.21e-10 IS = 1e-30 N = 10 M = 0.81)
.MODEL MMEDMOD NMOS (VTO = 2.02 KP = .83 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 3.37)
.MODEL MSTROMOD NMOS (VTO = 2.39 KP = 14 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.78 KP = 0.02 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 33.7 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 1.06e-3 TC2 = 0)
.MODEL RDRAINMOD RES (TC1 = 1.23e-2 TC2 = 2.58e-5)
.MODEL RSLCMOD RES (TC1 = 0 TC2 = 0)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 0)
.MODEL RVTHRESMOD RES (TC1 = -2.19e-3 TC2 = -4.97e-6)
.MODEL RVTEMPMOD RES (TC1 = -1.6e-3 TC2 = 1e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4 VOFF= -2.5)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.5 VOFF= -4)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.5 VOFF= 0)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0 VOFF= -0.5)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
©2001 Fairchild Semiconductor Corporation
HUF76407D3S Rev. C0
HUF76407D3S
SABER Electrical Model
REV 28 June 1999
template huf76407 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
d..model dbodymod = (is = 1.75e-13, cjo = 5.9e-10, tt = 5.45e-8, n=1.03, m = 0.6)
d..model dbreakmod = ()
d..model dplcapmod = (cjo = 3.21e-10, is = 1e-30, m = 0.81 )
m..model mmedmod = (type=_n, vto = 2.02, kp = .83, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 2.39, kp = 14, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 1.78, kp = 0.02, is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -4, voff = -2.5)
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -2.5, voff = -4)
LDRAIN
RLDRAIN
RDBODY
DPLCAP
DRAIN
2
5
10
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.5, voff = 0)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0, voff = -0.5)
RSLC1
51
RDBREAK
72
DBREAK
11
c.ca n12 n8 = 3.9e-10
c.cb n15 n14 = 4.9e-10
c.cin n6 n8 = 3.25e-10
RSLC2
ISCL
50
-
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod
71
RDRAIN
6
8
ESG
EVTHRES
+
+
16
21
-
19
8
MWEAK
i.it n8 n17 = 1
LGATE
EVTEMP
+
DBODY
RGATE
GATE
1
6
-
18
22
EBREAK
+
l.ldrain n2 n5 = 1.0e-9
l.lgate n1 n9 = 5.42e-9
l.lsource n3 n7 = 2.57e-9
MMED
9
20
MSTRO
8
17
18
-
RLGATE
LSOURCE
CIN
SOURCE
3
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
7
RSOURCE
RLSOURCE
S1A
S2A
res.rbreak n17 n18 = 1, tc1 = 1.06e-3, tc2 = 0
res.rdbody n71 n5 = 1.75e-2, tc1 = 1e-4, tc2 = 5e-6
res.rdbreak n72 n5 = 6.50e-1, tc1 = 1.25e-4, tc2 = 1.34e-6
res.rdrain n50 n16 = 3.7e-2, tc1 = 1.23e-2, tc2 = 2.58e-5
res.rgate n9 n20 = 3.37
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 54.2
res.rlsource n3 n7 = 25.7
res.rslc1 n5 n51 = 1e-6, tc1 = 0, tc2 =0
res.rslc2 n5 n50 = 1e3
RBREAK
12
15
13
14
13
17
18
8
RVTEMP
19
S1B
S2B
13
CB
CA
IT
14
-
+
+
VBAT
6
8
5
8
EGS
EDS
+
-
-
8
22
res.rsource n8 n7 = 2.50e-2, tc1 = 1e-3, tc2 =0
res.rvtemp n18 n19 = 1, tc1 = -1.6e-3, tc2 = 1.0e-7
res.rvthres n22 n8 = 1, tc1 = -2.19e-3, tc2 = -4.97e-6
RVTHRES
spe.ebreak n11 n7 n17 n18 = 67.8
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/30))** 3))
}
}
©2001 Fairchild Semiconductor Corporation
HUF76407D3S Rev. C0
HUF76407D3S
SPICE Thermal Model
JUNCTION
th
REV 28June 1999
HUF76407T
CTHERM1 th 6 4.5e-4
CTHERM2 6 5 2.5e-3
CTHERM3 5 4 1.9e-3
CTHERM4 4 3 2.6e-3
CTHERM5 3 2 5.5e-3
CTHERM6 2 tl 1.8e-2
RTHERM1
CTHERM1
6
RTHERM2
RTHERM3
RTHERM4
RTHERM5
RTHERM6
CTHERM2
CTHERM3
CTHERM4
CTHERM5
CTHERM6
RTHERM1 th 6 3.1e-2
RTHERM2 6 5 15.1e-2
RTHERM3 5 4 4.2e-1
RTHERM4 4 3 8.4e-1
RTHERM5 3 2 8.7e-1
RTHERM6 2 tl 1.5
5
SABER Thermal Model
SABER thermal model HUF76407T
4
3
2
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 4.5e-4
ctherm.ctherm2 6 5 = 2.5e-3
ctherm.ctherm3 5 4 = 1.9e-3
ctherm.ctherm4 4 3 = 2.6e-3
ctherm.ctherm5 3 2 = 5.5e-3
ctherm.ctherm6 2 tl = 1.8e-2
rtherm.rtherm1 th 6 = 3.1e-2
rtherm.rtherm2 6 5 = 15.1e-2
rtherm.rtherm3 5 4 = 4.2e-1
rtherm.rtherm4 4 3 = 8.4e-1
rtherm.rtherm5 3 2 = 8.7e-1
rtherm.rtherm6 2 tl = 1.5
}
tl
CASE
©2001 Fairchild Semiconductor Corporation
HUF76407D3S Rev. C0
HUF76407D3S
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Rev. I66
©2001 Fairchild Semiconductor Corporation
HUF76407D3S Rev. C0
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