HUFA76429D3 [ONSEMI]
N 沟道，逻辑电平，UltraFET Power MOSFET，60V，20A，27mΩ;
| 型号： | HUFA76429D3 |
| 厂家： | 
ONSEMI |
| 描述： | N 沟道，逻辑电平，UltraFET Power MOSFET，60V，20A，27mΩ PC 开关 晶体管 |
| 文件： | 总14页 (文件大小：181K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
www.onsemi.com
MOSFET – Power, N-Channel,
Logic Level, UltraFET
V
r
MAX
I MAX
D
DSS
DS(ON)
60 V
23 mꢀ @ 10 V
27 mꢀ @ 4.5 V
29 mꢀ @ 4.5 V
20 A
60 V, 20 A, 27 mW
HUFA76429D3
SOURCE
DRAIN
GATE
Features
• Ultra Low On−Resistance
♦ r
♦ r
= 0.023 ꢀ, V = 10 V
GS
DS(ON)
= 0.027 ꢀ, V = 5 V
DS(ON)
GS
DRAIN
• Simulation Models
(FLANGE)
®
♦ Temperature Compensated PSPICEt and Saber Electriecal
DPAK3 (IPAK)
JEDEC (TO−251AA)
CASE 369AR
Models
♦ Spice and SABER Thermal Impedance Models
♦ www.onsemi.com
• Peak Current vs. Pulse Width Curve
• UIS Rating Curve
MARKING DIAGRAM
• Switching Time vs. R Curves
GS
ABSOLUTE MAXIMUM RATINGS (T = 25°C unless otherwise noted)
$Y&Z&3&K
76429D
C
Rating
Symbol HUFA76429D3 Unit
Drain to Source Voltage (Note 1)
V
60
60
V
V
DSS
DGR
Drain to Gate Voltage (R = 20 kꢀ)
V
GS
(Note 1)
$Y
= Logo
= Assembly Plant Code
= 3−Digit Date Code
Gate to Source Voltage
V
16
20
V
A
GS
&Z
&3
&K
Drain
Current
Continuous (T = 25°C,
GS
I
C
D
D
D
D
V
= 5 V)
= 2−Digits Lot Run Traceability Code
76429D = Device Code
Continuous (T = 25°C,
I
I
I
20
20
A
A
A
C
V
GS
= 10 V) (Figure 2)
Continuous (T = 100°C,
C
V
GS
= 5 V)
D
Continuous (T = 100°C,
20
C
V
GS
= 4.5 V) (Figure 2)
G
Pulsed Drain Current
I
Figure 4
DM
Pulsed Avalanche Rating
UIS
Figures 6, 17,
18
S
N−Channel
Power
Dissipation
P
110
0.74
W
W/°C
°C
D
Derate Above 25°C
Operating and Storage Temperature
T , T
−55 to 175
300
J
STG
ORDERING INFORMATION
Maximum
Temperature from Case for 10 s
for Soldering
Leads at 0.063 in (1.6 mm)
T
°C
L
Part Number
Package
Marking Shipping
Package Body for 10 s,
See Techbrief TB334
T
pkg
260
°C
HUFA76429D3 DPAK3 (IPAK) 76429D 1800 Units
(TO−251AA)
/ Tube
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. T = 25°C to 150°C.
J
© Semiconductor Components Industries, LLC, 2012
1
Publication Order Number:
March, 2022 − Rev. 3
HUFA76429D3/D
HUFA76429D3
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
C
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
BV
60
55
−
−
−
−
V
V
I
I
= 250 ꢁ A, V = 0 V (Figure 12)
DSS
D
GS
= 250 ꢁ A, V = 0 V, T = −40°C
D
GS
C
(Figure 12)
Zero Gate Voltage Drain Current
I
V
V
V
= 55 V, V = 0 V
−
−
−
−
−
−
1
ꢁ A
ꢁ A
nA
DSS
DS
DS
GS
GS
= 50 V, V = 0 V, T = 150°C
250
100
GS
C
Gate to Source Leakage Current
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
Drain to Source On Resistance
I
= 16 V
GSS
V
r
V
I
= V , I = 250 ꢁ A (Figure 11)
1
−
−
−
−
3
V
ꢀ
ꢀ
ꢀ
GS(TH)
GS
DS
D
= 20 A, V = 10 V (Figures 9, 10)
0.0205
0.024
0.025
0.023
0.027
0.029
DS(ON)
D
GS
I
= 20 A, V = 5 V (Figure 9)
GS
D
D
I
= 20 A, V = 4.5 V (Figure 9)
GS
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
R
TO−251
−
−
−
−
1.36
100
°C/W
°C/W
ꢂ
ꢂ
JC
R
JA
SWITCHING SPECIFICATIONS (V = 4.5 V)
GS
Turn−On Time
t
V
V
= 30 V, I = 20 A
−
−
−
−
−
−
−
13
134
30
55
−
220
−
ns
ns
ns
ns
ns
ns
ON
DD
D
ꢃ
4
.
5
V
,
R
=
7
.
5
ꢀ
GS
GS
Turn−On Delay Time
Rise Time
t
d(ON)
(Figures 15, 21, 22)
t
r
−
Turn−Off Delay Time
Fall Time
t
−
d(OFF)
t
f
−
Turn−Off Time
t
130
OFF
SWITCHING SPECIFICATIONS (V = 10 V)
GS
Turn−On Time
Turn−On Delay Time
Rise Time
t
V
V
= 30 V, I = 20 A
−
−
−
−
−
−
−
7.7
36
60
56
−
65
−
ns
ns
ns
ns
ns
ns
ON
DD
D
ꢃ
1
0
V
,
R
=
8
.
2
ꢀ
GS
GS
t
d(ON)
(Figures 16, 21, 22)
t
r
−
Turn−Off Delay Time
Fall Time
t
−
d(OFF)
t
f
−
Turn−Off Time
t
175
OFF
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Q
V
V
V
= 0 V to 10 V
= 0 V to 5 V
= 0 V to 1 V
V
= 30 V, I = 20 A,
= 1.0 mA
−
−
−
−
−
38
21
46
25
1.6
−
nC
nC
nC
nC
nC
g(TOT)
GS
GS
GS
DD
D
I
g(REF)
Gate Charge at 5 V
Q
g(5)
(Figures 14, 19, 20)
Threshold Gate Charge
Gate to Source Gate Charge
Gate to Drain ”Miller” Charge
CAPACITANCE SPECIFICATIONS
Input Capacitance
Q
1.3
3.8
9.7
g(TH)
Q
gs
gd
Q
−
C
V
DS
= 25 V, V = 0 V, f = 1 MHz
−
−
−
1480
440
90
−
−
−
pF
pF
pF
ISS
GS
(Figure 13)
Output Capacitance
C
C
OSS
RSS
Reverse Transfer Capacitance
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
www.onsemi.com
2
HUFA76429D3
SOURCE TO DRAIN DIODE SPECIFICATIONS
Parameter
Symbol
Test Conditions
Min
−
Typ
−
Max
1.25
1.00
80
Unit
V
Source to Drain Diode Voltage
V
SD
I
I
I
I
= 20 A
= 10 A
SD
SD
SD
SD
−
−
V
Reverse Recovery Time
t
rr
= 20 A, dI /dt = 100 A/ꢁ s
−
−
ns
nC
SD
Reverse Recovered Charge
Q
= 20 A, dI /dt = 100 A/ꢁ s
−
−
230
RR
SD
www.onsemi.com
3
HUFA76429D3
TYPICAL PERFORMANCE CURVES
1.2
1.0
0.8
0.6
0.4
0.2
0
25
20
15
10
5
0
0
25
50
75
100
125
150
175
25
50
75
100
125
150
175
T , Case Temperature (°C)
C
T , Case Temperature (°C)
C
Figure 1. Normalized Power Dissipation vs.
Case Temperature
Figure 2. Maximum Continuous Drain Current
vs. Case Temperature
2
Duty Cycle − Descending Order
0.5
1
0.2
0.1
0.05
0.01
0.02
PDM
0.1
t1
t2
NOTES:
Duty Factor: D = t / t
1
2
Single Pulse
10−4
Peak T = P
x Z
x R
+ T
JC C
ꢂ
ꢂ
J
DM
JC
0.01
10−3
10−2
t, Rectangular Pulse Duration (s)
10−1
100
101
10−5
Figure 3. Normalized Maximum Transient Thermal Impedance
600
100
T
= 25°C
C
For Temperatures above
25°C Derate Peak Current
as follows:
V
GS
= 10 V
175 * TC
Ǹ
I + I25 ƪ ƫ
150
V
GS
= 5 V
Transconductance may
limit current in this region
10
10−5
10−4
10−3
10−2
10−1
100
101
t, Pulse Width (s)
Figure 4. Peak Current Capability
www.onsemi.com
4
HUFA76429D3
TYPICAL PERFORMANCE CURVES (Continued)
300
100
100
t
= (L) (IAS) / (1.3 x RATED BV
− V
)
AV
DSS
DD
If R = 0
If R 0 0
t
AV
= (L / R) ln [(IAS x R) / (1.3 * RATED BV
− V ) + 1]
DSS DD
100 ꢁ s
Starting TJ = 25°C
Operation in this
area may be limited
10
1
1 ms
by r
DS(ON)
Single Pulse
T = Max Rated
Starting TJ = 150°C
10 ms
J
T
C
= 25°C
10
0.01
1
10
100
0.1
1
10
V
DS
, Drain to Source Voltage (V)
t , Time in Avalanche (ms)
AV
NOTE: Refer to onsemi Application Notes AN9321 and AN9322.
Figure 5. Forward Bias Safe Operating Area
Figure 6. Unclamped Inductive Switching Capability
50
50
V
GS
= 10 V
V
GS
= 5 V
Pulse Duration = 80 ꢁ s
Duty Cycle = 0.5% Max
V
GS
= 4 V
40
30
20
10
0
40
30
20
10
0
V
DD
= 15 V
V
= 3.5 V
GS
V
= 3 V
TJ = 175°C
GS
TJ = −55°C
TJ = 25°C
Pulse Duration = 80 ꢁ s
Duty Cycle = 0.5% Max
T
C
= 25°C
1.5
2
2.5
3
3.5
4
0
1
2
3
4
V
GS
, Gate to Source Voltage (V)
V
DS
, Drain to Source Voltage (V)
Figure 7. Transfer Characteristics
Figure 8. Saturation Characteristics
40
30
2.5
2.0
1.5
Pulse Duration = 80 ꢁ s
Duty Cycle = 0.5% Max
Pulse Duration = 80 ꢁ s
Duty Cycle = 0.5% Max
V = 10 V, I = 20 A
GS D
I
D
= 20 A
T
C
= 25°C
I
D
= 10 A
20
10
1.0
0.5
−80
2
4
6
8
10
−40
0
40
80
120
160 200
V
GS
, Gate to Source Voltage (V)
T , Junction Temperature (°C)
J
Figure 9. Drain to Source On Resistance vs.
Gate Voltage and Drain Current
Figure 10. Normalized Drain to Source On
Resistance vs. Junction Temperature
www.onsemi.com
5
HUFA76429D3
TYPICAL PERFORMANCE CURVES (Continued)
1.2
1.0
0.8
1.2
V
= V , I = 250 ꢁ A
I = 250 ꢁ A
D
GS
DS
D
1.1
1.0
0.9
0.6
0.4
−80
−40
0
40
80
120
160 200
−80
−40
0
40
80
120
160 200
T , Junction Temperature (°C)
J
T , Junction Temperature (°C)
J
Figure 11. Normalized Gate Threshold Voltage vs.
Junction Temperature
Figure 12. Normalized Darin to Source Breakdown
Voltage vs. Junction Temperature
3000
10
V
GS
= 0 V, f = 1 MHz
V
DD
= 30 V
C
= C + C
ISS
GS
GD
8
6
4
2
0
1000
C
= C + C
GS GD
ISS
Waveforms in
descending order
100
30
C
+ C
I
D
I
D
= 20 A
= 10 A
RSS
GD
0.1
1.0
10
60
0
5
10
15
20
25
30
35
40
V
DS
, Drain to Source Voltage (V)
Q , Gate Charge (nC)
g
NOTE: Refer to onsemi Application Notes AN7254 and AN7260.
Figure 14. Gate Charge Waveforms for Constant
Gate Current
Figure 13. Capacitance vs. Drain to Source Voltage
300
400
V
GS
= 4.5 V, V = 30 V, I = 20 A
V
GS
= 10 V, V = 30 V, I = 20 A
DS
D
DS
D
250
200
150
100
50
300
200
100
t
r
t
d(OFF)
t
f
t
d(OFF)
t
f
t
r
t
d(ON)
t
d(ON)
0
0
0
10
20
30
40
50
0
10
20
30
40
50
R
, Gate to Source Resistance (ꢀ)
R
GS
, Gate to Source Resistance (ꢀ)
GS
Figure 15. Switching Time vs. Gate Resistance
Figure 16. Switching Time vs. Gate Resistance
www.onsemi.com
6
HUFA76429D3
TEST CIRCUITS AND WAVEFORMS
VDS
BVDSS
tP
L
VDS
IAS
VARY t to OBTAIN
P
+
VDD
VDD
REQUIRED PEAK I
RG
AS
−
VGS
DUT
0.01
tP
IAS
0 V
0
ꢀ
tAV
Figure 17. Unclamped Energy Test Circuit
Figure 18. Unclamped Energy Waveforms
VDS
Qg(TOT)
VDD
RL
VDS
Qg(5)
VGS = 10 V
VGS
+
VDD
−
VGS = 5 V
VGS
DUT
VGS = 1 V
0
Ig(REF)
Qg(TH)
Qgs
Qgd
Ig(REF)
0
Figure 19. Gate Charge Test Circuit
Figure 20. Gate Charge Waveforms
tON
td(ON)
tOFF
td(OFF)
VDS
tr
tf
RL
VDS
90%
90%
+
VGS
VDD
−
10%
10%
0
90%
50%
DUT
RGS
VGS
50%
10%
0
PULSE WIDTH
VGS
Figure 21. Switching Time Test Circuit
Figure 22. Switching Time Waveforms
www.onsemi.com
7
HUFA76429D3
PSPICE ELECTRICAL MODEL
.SUBCKT HUFA76429D3 2 1 3 ; rev 5 July 1999
CA 12 8 2.03e−9
CB 15 14 2.03e−9
CIN 6 8 1.39e−9
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 68.10
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
IT 8 17 1
LDRAIN 2 5 1e−9
LGATE 1 9 5.42e−9
LSOURCE 3 7 4.16e−9
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 9.1e−3
RGATE 9 20 2.80
RLDRAIN 2 5 10
RLGATE 1 9 54.2
RLSOURCE 3 7 41.6
RSLC1 5 51 RSLCMOD 1e−6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 6.5e−3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e−6*117),3))}
.MODEL DBODYMOD D (IS = 1.25e−12 IKF = 10 RS = 8.40e−3 TRS1 = 2.05e−3 TRS2 = 3.85e−6 CJO = 1.68e−9 TT =
4.90e−8 M = 0.48 XTI = 4.35)
.MODEL DBREAKMOD D (RS = 1.68e−1 TRS1 = 1e−3 TRS2 = −1e−6)
.MODEL DPLCAPMOD D (CJO = 1.28e−9 IS = 1e−30 N = 10 M = 0.8)
.MODEL MMEDMOD NMOS (VTO = 1.98 KP = 3.2 IS = 1e−30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.80)
.MODEL MSTROMOD NMOS (VTO = 2.30 KP = 52 IS = 1e−30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.72 KP = 0.08 IS = 1e−30 N = 10 TOX = 1 L = 1u W = 1u RG = 28.0 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 1.15e−3 TC2 = −5.40e−7)
www.onsemi.com
8
HUFA76429D3
.MODEL RDRAINMOD RES (TC1 = 7.85e−3 TC2 = 1.95e−5)
.MODEL RSLCMOD RES (TC1 = 4.97e−3 TC2 = 5.05e−6)
.MODEL RSOURCEMOD RES (TC1 = 1.5e−3 TC2 = 1e−6)
.MODEL RVTHRESMOD RES (TC1 = −1.85e−3 TC2 = −4.48e−6)
.MODEL RVTEMPMOD RES (TC1 = −1.92e−3 TC2 = 9.50e−7)
.MODEL S1AMOD VSWITCH (RON = 1e−5 ROFF = 0.1 VON = −6.2 VOFF= −2.4)
.MODEL S1BMOD VSWITCH (RON = 1e−5 ROFF = 0.1 VON = −2.4 VOFF= −6.2)
.MODEL S2AMOD VSWITCH (RON = 1e−5 ROFF = 0.1 VON = −1.1 VOFF= 0.5)
.MODEL S2BMOD VSWITCH (RON = 1e−5 ROFF = 0.1 VON = 0.5 VOFF= −1.1)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub−Circuit for the Power MOSFET
Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written
by William J. Hepp and C. Frank Wheatley.
LDRAIN
DPLCAP
DRAIN
2
5
10
RLDRAIN
RSLC1
DBREAK
51
+
RSLC2
5
ESLC
11
+
51
−
50
−
17
18
−
DBODY
RDRAIN
6
8
EBREAK
MWEAK
ESG
EVTHRES
+
+
16
21
−
19
8
LGATE
EVTEMP
+
RGATE
GATE
1
6
−
18
22
MMED
9
20
MSTRO
8
RLGATE
LSOURCE
CIN
SOURCE
3
7
RSOURCE
RLSOURCE
S1A
S1B
S2A
S2B
RBREAK
12
15
13
8
14
13
17
18
RVTEMP
19
−
13
CB
CA
IT
14
+
+
VBAT
6
8
5
8
EGS
EDS
+
−
−−
8
22
RVTHRES
Figure 23.
www.onsemi.com
9
HUFA76429D3
SABER ELECTRICAL MODEL
REV 5 July 1999
template HUFA76429d3 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
d..model dbodymod = (is = 1.25e−12, cjo = 1.68e−9, tt = 4.90e−8, xti = 4.35, m = 0.48)
d..model dbreakmod = ()
d..model dplcapmod = (cjo = 1.28e−9, is = 1e−30, n = 10, m = 0.8)
m..model mmedmod = (type=_n, vto = 1.98, kp = 3.2, is = 1e−30, tox = 1)
m..model mstrongmod = (type=_n, vto = 2.30, kp = 52, is = 1e−30, tox = 1)
m..model mweakmod = (type=_n, vto = 1.72, kp = 0.08, is = 1e−30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e−5, roff = 0.1, von = −6.2, voff = −2.4)
sw_vcsp..model s1bmod = (ron =1e−5, roff = 0.1, von = −2.4, voff = −6.2)
sw_vcsp..model s2amod = (ron = 1e−5, roff = 0.1, von = −1.1, voff = 0.5)
sw_vcsp..model s2bmod = (ron = 1e−5, roff = 0.1, von = 0.5, voff = −1.1)
c.ca n12 n8 = 2.03e−9
c.cb n15 n14 = 2.03e−9
c.cin n6 n8 = 1.39e−9
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod
i.it n8 n17 = 1
l.ldrain n2 n5 = 1e−9
l.lgate n1 n9 = 5.42e−9
l.lsource n3 n7 = 4.16e−9
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1 = 1.15e−3, tc2 = −5.40e−7
res.rdbody n71 n5 = 8.40e−3, tc1 = 2.05e−3, tc2 = 3.85e−6
res.rdbreak n72 n5 = 1.68e−1, tc1 = 1.00e−3, tc2 = −1.00e−6
res.rdrain n50 n16 = 9.10e−3, tc1 = 7.85e−3, tc2 = 1.95e−5
res.rgate n9 n20 = 2.80
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 54.2
res.rlsource n3 n7 = 41.6
res.rslc1 n5 n51 = 1e−6, tc1 = 4.97e−3, tc2 = 5.05e−6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 6.5e−3, tc1 = 1.5e−3, tc2 = 1e−6
res.rvtemp n18 n19 = 1, tc1 = −1.92e−3, tc2 = 9.50e−7
res.rvthres n22 n8 = 1, tc1 = −1.85e−3, tc2 = −4.48e−6
spe.ebreak n11 n7 n17 n18 = 68.10
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
www.onsemi.com
10
HUFA76429D3
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51−>n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e−9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/117))** 3))
}
}
LDRAIN
RLDRAIN
RDBODY
DPLCAP
5
DRAIN
2
10
RSLC1
RDBREAK
51
RSLC2
72
ISCL
DBREAK
50
−
71
RDRAIN
6
8
11
ESG
EVTHRES
+
+
16
21
−
19
8
MWEAK
EBREAK
LGATE
EVTEMP
+
DBODY
RGATE
GATE
1
6
−
18
22
MMED
+
9
20
MSTRO
8
17
18
−
RLGATE
LSOURCE
CIN
SOURCE
3
7
RSOURCE
RLSOURCE
S1A
S2A
RBREAK
12
15
13
8
14
13
17
18
RVTEMP
19
S1B
S2B
13
CB
CA
IT
14
−
+
+
VBAT
6
8
5
8
EGS
EDS
+
−
−−
8
22
RVTHRES
Figure 24.
www.onsemi.com
11
HUFA76429D3
JUNCTION
th
SPICE THERMAL MODEL
REV 26 July 1999
HUFA76429D3
RTHERM1
RTHERM2
RTHERM3
RTHERM4
RTHERM5
RTHERM6
CTHERM1
CTHERM1 th 6 2.45e−3
CTHERM2 6 5 8.15e−3
CTHERM3 5 4 7.40e−3
CTHERM4 4 3 7.45e−3
CTHERM5 3 2 1.01e−2
CTHERM6 2 tl 7.49e−2
6
CTHERM2
CTHERM3
CTHERM4
CTHERM5
CTHERM6
RTHERM1 th 6 9.00e−3
RTHERM2 6 5 1.80e−2
RTHERM3 5 4 9.15e−2
RTHERM4 4 3 2.43e−1
RTHERM5 3 2 3.50e−1
RTHERM6 2 tl 3.62e−1
5
4
3
2
SABER THERMAL MODEL
SABER thermal model HUFA76429D3
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 2.45e−3
ctherm.ctherm2 6 5 = 8.15e−3
ctherm.ctherm3 5 4 = 7.40e−3
ctherm.ctherm4 4 3 = 7.45e−3
ctherm.ctherm5 3 2 = 1.01e−2
ctherm.ctherm6 2 tl = 7.49e−2
rtherm.rtherm1 th 6 = 9.00e−3
rtherm.rtherm2 6 5 = 1.80e−2
rtherm.rtherm3 5 4 = 9.15e−2
rtherm.rtherm4 4 3 = 2.43e−1
rtherm.rtherm5 3 2 = 3.50e−1
rtherm.rtherm6 2 tl = 3.62e−1
}
tl
CASE
Figure 25.
PSPICE is a trademark of MicroSim Corporation.
Saber is a registered trademark of Sabremark Limited Partnership.
www.onsemi.com
12
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DPAK3 (IPAK)
CASE 369AR
ISSUE O
DATE 30 SEP 2016
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13815G
DPAK3 (IPAK)
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
ADDITIONAL INFORMATION
TECHNICAL PUBLICATIONS:
Technical Library: www.onsemi.com/design/resources/technical−documentation
onsemi Website: www.onsemi.com
ONLINE SUPPORT: www.onsemi.com/support
For additional information, please contact your local Sales Representative at
www.onsemi.com/support/sales
相关型号：
HUFA76429D3ST_F085
Power Field-Effect Transistor, 20A I(D), 60V, 0.029ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-252AA, ROHS COMPLIANT PACKAGE-3
FAIRCHILD
HUFA76429D3T
Power Field-Effect Transistor, 20A I(D), 60V, 0.029ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-251AA, TO-251AA, 3 PIN
FAIRCHILD
HUFA76429D3_NL
Power Field-Effect Transistor, 20A I(D), 60V, 0.029ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-251AA,
FAIRCHILD
©2020 ICPDF网 联系我们和版权申明