J112 [ONSEMI]
JFET Chopper Transistor; JFET晶体管斩波
| 型号： | J112 |
| 厂家： | 
ONSEMI |
| 描述： | JFET Chopper Transistor |
| 文件： | 总4页 (文件大小：114K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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by J112/D
SEMICONDUCTOR TECHNICAL DATA
N–Channel — Depletion
1 DRAIN
3
GATE
2 SOURCE
MAXIMUM RATINGS
Rating
Drain–Gate Voltage
Symbol
Value
Unit
Vdc
1
V
DG
–35
–35
50
2
3
Gate–Source Voltage
Gate Current
V
GS
Vdc
CASE 29–04, STYLE 5
TO–92 (TO–226AA)
I
G
mAdc
Total Device Dissipation @ T = 25°C
Derate above 25°C
P
D
350
2.8
mW
mW/°C
A
Lead Temperature
T
300
°C
°C
L
Operating and Storage Junction
Temperature Range
T , T
stg
–65 to +150
J
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
A
Characteristic
Symbol
Min
Max
Unit
OFF CHARACTERISTICS
Gate–Source Breakdown Voltage
(I = –1.0 µAdc)
G
V
35
—
—
Vdc
nAdc
Vdc
(BR)GSS
Gate Reverse Current
I
–1.0
–5.0
1.0
GSS
(V
GS
= –15 Vdc)
Gate Source Cutoff Voltage
(V = 5.0 Vdc, I = 1.0 µAdc)
V
–1.0
—
GS(off)
DS
Drain–Cutoff Current
(V = 5.0 Vdc, V
D
I
nAdc
D(off)
= –10 Vdc)
DS GS
ON CHARACTERISTICS
(1)
Zero–Gate–Voltage Drain Current
I
5.0
—
—
50
28
mAdc
Ω
DSS
(V
DS
= 15 Vdc)
Static Drain–Source On Resistance
(V = 0.1 Vdc)
r
DS(on)
DS
Drain Gate and Source Gate On–Capacitance
(V = V = 0, f = 1.0 MHz)
C
—
pF
dg(on)
+
DS
GS
C
sg(on)
Drain Gate Off–Capacitance
(V = –10 Vdc, f = 1.0 MHz)
C
—
—
5.0
5.0
pF
pF
dg(off)
GS
Source Gate Off–Capacitance
(V = –10 Vdc, f = 1.0 MHz)
C
sg(off)
GS
1. Pulse Width = 300 µs, Duty Cycle = 3.0%.
(Replaces J111/D)
Motorola, Inc. 1997
TYPICAL SWITCHING CHARACTERISTICS
1000
500
1000
T
= 25°C
T
= 25°C
J
J
500
V
= 7.0 V
V
= 7.0 V
GS(off)
GS(off)
200
100
50
200
100
50
R
= R ′
D
K
R
= R ′
D
K
20
10
20
10
5.0
5.0
R
K
= 0
R
= 0
K
2.0
1.0
2.0
1.0
0.5 0.7 1.0
2.0 3.0
5.0 7.0 10
20
30
50
0.5 0.7 1.0
2.0 3.0
5.0 7.0 10
20
30
50
I
, DRAIN CURRENT (mA)
I , DRAIN CURRENT (mA)
D
D
Figure 1. Turn–On Delay Time
Figure 2. Rise Time
1000
500
1000
500
T
= 25°C
T
= 25°C
J
J
V
= 7.0 V
V
= 7.0 V
GS(off)
GS(off)
200
100
50
200
100
50
R
= R
′
D
K
R
= R ′
D
K
R
K
= 0
20
10
20
10
R
= 0
K
5.0
5.0
2.0
1.0
2.0
1.0
0.5 0.7 1.0
2.0 3.0
5.0 7.0 10
20
30
50
0.5 0.7 1.0
2.0 3.0
5.0 7.0 10
20
30
50
I
, DRAIN CURRENT (mA)
I , DRAIN CURRENT (mA)
D
D
Figure 3. Turn–Off Delay Time
Figure 4. Fall Time
NOTE 1
The switching characteristics shown above were measured using a
test circuit similar to Figure 5. At the beginning of the switching
+V
DD
interval, the gate voltage is at Gate Supply Voltage (–V
). The
GG
Drain–Source Voltage (V ) is slightly lower than Drain Supply
DS
R
D
Voltage (V ) due to the voltage divider. Thus Reverse Transfer
DD
SET V
= 10 V
DS(off)
R
Capacitance (C ) or Gate–Drain Capacitance (C ) is charged to
rss gd
GG
During the turn–on interval, Gate–Source Capacitance (C
INPUT
V
+ V
.
DS
R
R
K
T
)
gs
R
50
OUTPUT
GEN
discharges through the series combination of R
and R . C
K
Gen
gd
Ω
GG
must discharge to V
through R and R in series with the
DS(on)
G
K
50
Ω
50 Ω
parallel combination of effective load impedance (R′ ) and
D
V
V
GEN
GG
Drain–SourceResistance (r ). During the turn–off, this charge flow
ds
is reversed.
Predicting turn–on time is somewhat difficult as the channel
resistance r is a function of the gate–source voltage. While C
ds
gs
gd
INPUT PULSE
R
R
GG
K
discharges, V
approaches zero and r decreases. Since C
ds
ds
t
≤
≤
0.25 ns
0.5 ns
µ
GS
r
f
R
(R
50)
50
discharges through r , turn–on time is non–linear. During turn–off,
the situation is reversed with r increasing as C charges.
t
T
D
R
D
PULSE WIDTH = 2.0
s
R
R
ds
gd
D
T
DUTY CYCLE 2.0%
≤
The above switching curves show two impedance conditions;
1) R is equal to R , which simulates the switching behavior of
K
D
Figure 5. Switching Time Test Circuit
cascaded stages where the driving source impedance is normally
the load impedance of the previous stage, and 2) R = 0 (low
K
impedance) the driving source impedance is that of the generator.
2
Motorola Small–Signal Transistors, FETs and Diodes Device Data
20
15
10
C
gs
10
7.0
5.0
7.0
5.0
C
gd
T
V
= 25°C
channel
= 15 V
DS
3.0
2.0
T
= 25°C
channel
(C IS NEGLIGIBLE)
ds
3.0
2.0
1.5
1.0
0.5 0.7 1.0
2.0 3.0
5.0 7.0 10
20
30
50
0.03 0.05 0.1
0.3 0.5
V , REVERSE VOLTAGE (VOLTS)
R
1.0
3.0 5.0
10
30
I
, DRAIN CURRENT (mA)
D
Figure 6. Typical Forward Transfer Admittance
Figure 7. Typical Capacitance
200
160
120
80
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
I
25
mA
50 mA 75 mA 100 mA
125 mA
DSS
I
V
= 1.0 mA
D
= 10
mA
= 0
GS
T
= 25
7.0
°C
40
channel
0
0
1.0
2.0
3.0
4.0
5.0
6.0
8.0
–70
–40
–10
20
50
80
110
C)
140
170
V
, GATE–SOURCE VOLTAGE (VOLTS)
T
, CHANNEL TEMPERATURE (
°
GS
channel
Figure 8. Effect of Gate–Source Voltage
On Drain–Source Resistance
Figure 9. Effect of Temperature On
Drain–Source On–State Resistance
100
90
10
T
= 25
= 0
°
C
channel
NOTE 2
9.0
8.0
7.0
The Zero–Gate–Voltage Drain Current (I
determinant of other J-FET characteristics. Figure 10 shows
the relationship of Gate–Source Off Voltage (V and
), is the principle
DSS
80
70
GS(off)
. Most of the
r
@ V
GS
DS(on)
Drain–Source On Resistance (r
) to I
ds(on)
DSS
60
50
40
30
20
10
0
6.0
5.0
4.0
3.0
2.0
devices will be within ±10% of the values shown in Figure 10.
This data will be useful in predicting the characteristic
variations for a given part number.
For example:
V
GS(off)
Unknown
r
and V
range for an J112
ds(on) GS
The electrical characteristics table indicates that an J112
has an I range of 25 to 75 mA. Figure 10, shows r
1.0
0
=
DSS
52 Ohms for I
ds(on)
= 75 mA.
= 25 mA and 30 Ohms for I
DSS
The corresponding V
DSS
values are 2.2 volts and 4.8 volts.
10 20 30 40 50 60
80
100
110 120 130 140 150
70
90
GS
I
, ZERO–GATE–VOLTAGE DRAIN CURRENT (mA)
DSS
Figure 10. Effect of I
On Drain–Source
DSS
Resistance and Gate–Source Voltage
Motorola Small–Signal Transistors, FETs and Diodes Device Data
3
PACKAGE DIMENSIONS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. CONTOUR OF PACKAGE BEYOND DIMENSION R
IS UNCONTROLLED.
A
B
4. DIMENSION F APPLIES BETWEEN P AND L.
DIMENSION D AND J APPLY BETWEEN L AND K
MINIMUM. LEAD DIMENSION IS UNCONTROLLED
IN P AND BEYOND DIMENSION K MINIMUM.
R
P
L
F
SEATING
PLANE
K
INCHES
MIN
MILLIMETERS
DIM
A
B
C
D
F
G
H
J
K
L
N
P
MAX
0.205
0.210
0.165
0.022
0.019
0.055
0.105
0.020
–––
MIN
4.45
4.32
3.18
0.41
0.41
1.15
2.42
0.39
12.70
6.35
2.04
–––
MAX
5.20
5.33
4.19
0.55
0.48
1.39
2.66
0.50
–––
0.175
0.170
0.125
0.016
0.016
0.045
0.095
0.015
0.500
0.250
0.080
–––
D
X X
G
J
H
V
C
–––
–––
SECTION X–X
0.105
0.100
–––
2.66
2.54
–––
1
N
R
V
0.115
0.135
2.93
3.43
N
–––
–––
STYLE 5:
PIN 1. DRAIN
2. SOURCE
3. GATE
CASE 029–04
(TO–226AA)
ISSUE AD
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
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