KAC-12040-CBA-JD-BA_技术文档

KAC-12040

4000 (H) x 3000 (V)

CMOS Image Sensor

Description

The KAC−12040 Image Sensor is a high-speed 12 megapixel

CMOS image sensor in a 4/3″ optical format based on a 4.7 mm 5T

CMOS platform. The image sensor features very fast frame rate,

excellent NIR sensitivity, and flexible readout modes with multiple

regions of interest (ROI). The readout architecture enables use of 8, 4,

or 2 LVDS output banks for full resolution readout of 70 frames per

second.

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Each LVDS output bank consists of up to 8 differential pairs

operating at 160 MHz DDR for a 320 Mbps data rate per pair.

The pixel architecture allows rolling shutter operation for motion

capture with optimized dynamic range or global shutter for precise

still image capture.

Table 1. GENERAL SPECIFICATIONS

Parameter

Architecture

Typical Value

5T Global Shutter CMOS

12 Megapixels

Figure 1. KAC−12040 CMOS Image Sensor

Features

Resolution

Aspect Ratio

4:3

Pixel Size

4.7 mm (H) × 4.7 mm (V)

4224 (H) × 3192 (V)

4016 (H) × 3016 (V)

4000 (H) × 3000 (V)

• Global Shutter and Rolling Shutter

• Very Fast Frame Rate

• High NIR Sensitivity

• Multiple Regions of Interest

• Interspersed Video Streams

Total Number of Pixels

Number of Effective Pixels

Number of Active Pixels

Active Image Size

18.8 mm (H) × 14.1 mm (V)

23.5 mm (Diagonal), 4/3″ Optical Format

Master Clock Input Speed

Maximum Pixel Clock Speed

Number of LVDS Outputs

Number of Output Banks

Frame Rate, 12 Mp

5 MHz to 50 MHZ

Applications

160 MHz DDR LVDS, 320 Mbps

64 Differential Pairs

8, 4, or 2

• Machine Vision

• Intelligent Transportation Systems

• Surveillance

1−70 fps 10 bits

1−75 fps 8 bits

Charge Capacity

16,000 electrons

ORDERING INFORMATION

See detailed ordering and shipping information on page 2 of

this data sheet.

Quantum Efficiency

KAC−12040−CBA

KAC−12040−ABA

40%, 47%, 45% (470, 540, 620 nm)

53%, 15%, 10% (500, 850, 900 nm)

−

Read Noise

(at Maximum LVDS Clock)

3.7 e rms, Rolling Shutter

−

25.5 e rms, Global Shutter

Dynamic Range

73 dB, Rolling Shutter

56 dB, Global Shutter

Blooming Suppression

Image Lag

> 10,000x

1.3 electron

Digital Core Supply

Analog Core Supply

Pixel Supply

2.0 V

1.8 V

2.8 V & 3.5 V

Power Consumption

Package

1.5 W for 12 Mp @ 70 fps 10 bits

267 Pin Ceramic Micro-PGA

AR Coated, 2-sides

Cover Glass

NOTE: All Parameters are specified at T = 40°C unless otherwise noted.

1

Publication Order Number:

March, 2016 − Rev. 5

KAC−12040/D

KAC−12040

The image sensor has a pre-configured QFHD (4 × 1080p,

clamping, overflow pixel for blooming reduction, black-sun

correction (anti-eclipse), column and row noise correction,

and integrated timing generation with SPI control, 4:1 and

9:1 averaging decimation modes.

16:9) video mode, fully programmable, multiple ROI for

windowing, programmable sub-sampling, and reverse

readout (flip and mirror). The two ADCs can be configured

for 8-bit, 10-bit, 12-bit or 14-bit conversion and output.

Additional features include interspersed video streams

(dual-video), on-chip responsivity calibration, black

ORDERING INFORMATION

Table 2. ORDERING INFORMATION − KAC−12040 IMAGE SENSOR

Part Number

Description

Marking Code

KAC−12040−ABA−JD−BA

Monochrome, Micro-PGA Package, Sealed Clear Cover Glass with AR

Coating (Both Sides), Standard Grade.

KAC−12040−ABA

Serial Number

KAC−12040−ABA−JD−AE

KAC−12040−CBA−JD−BA

KAC−12040−CBA−JD−AE

Monochrome, Micro-PGA Package, Sealed Clear Cover Glass with AR

Coating (Both Sides), Engineering Grade.

Bayer (RGB) Color Filter Pattern, Micro-PGA Package, Sealed Clear Cover

Glass with AR Coating (Both Sides), Standard Grade.

KAC−12040−CBA

Serial Number

Bayer (RGB) Color Filter Pattern, Micro-PGA Package, Sealed Clear Cover

Glass with AR Coating (Both Sides), Engineering Grade.

1. Engineering Grade samples might not meet final production testing limits, especially for cosmetic defects such as clusters, but also possibly

column and row artifacts. Overall performance is representative of final production parts.

Table 3. ORDERING INFORMATION − EVALUATION SUPPORT

Part Number

Description

KAC−12040−CB−A−GEVK

KAC−12040−AB−A−GEVK

LENS−MOUNT−KIT−C−GEVK

Evaluation Hardware for KAC−12040 Image Sensor (Color). Includes Image Sensor.

Evaluation Hardware for KAC−12040 Image Sensor (Monochrome). Includes Image Sensor.

Lens Mount Kit that Supports C, CS, and F Mount Lenses. Includes IR Cut-filter for Color Imaging.

See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention

used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at

www.onsemi.com.

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2

KAC−12040

DEVICE DESCRIPTION

Architecture

3.5 V

A

LVDS Bank 3

LVDS Bank 5

LVDS Bank 7

3.3 V

D

2.8 V

A

2.0 V

Odd Row ADC, Analog Gain, Black-Sun Correction

D

1.8 V

A

88

8

1D − 1D

Chip Clock (2 Pins)

TRIGGER

0

6

B

G

R

B

G

R

RESETN

4000 (H) y 3000 (V)

4.7 mm Pixel

Clk1

Serial

CSN

SCLK

MOSI

MISO

Peripheral

Interface

(SPI)

0D − 0D

0

6

B

G

R

B

G

R

ADC_Ref1

(0, 0)

8

88

Clk0

4.02 kW 1%

Even Row ADC, Analog Gain, Black-Sun Correction

ADC_Ref2

VSS 0 V

LVDS Bank 2

LVDS Bank 4

LVDS Bank 6

Figure 2. Block Diagram

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KAC−12040

Physical Orientation

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

A

B

C

D

E

LVDS Bank 3

LVDS Bank 5

LVDS Bank 7

LVDS Bank 2

LVDS Bank 4

LVDS Bank 6

AA

AB

AC

AD

AE

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

Notes:

1. The center of the pixel array is aligned to the physical package center.

2. The region under the sensor die is clear of pins enabling the use of a heat sink.

3. Non-symmetric mounting holes provide orientation and mounting precision.

4. Non-symmetric pins prevent incorrect placement in PCB.

5. Letter “F” indicator shows default readout direction relative to package pin 1.

Figure 3. Package Pin Orientation − Top X-Ray View

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KAC−12040

Table 4. PRIMARY PIN DESCRIPTION

Name

RESETN

CLK_In1

CLK_In2

TRIGGER

SCLK

Type

DI

Description

AB09

E07

Sensor Reset (0 V = Reset State)

Sensor Input Clk_In1 (45−50 MHz)

DI

D08

DI

Sensor Input Clk_In2 (Connect to Clk1)

Trigger Input (Optional)

AB08

AA05

AA08

AA07

AA06

AA14

AA15

AB07

AB06

E05

DI

SPI Master Clock

MOSI

DI

SPI Master Output, Slave Input

MISO

DO

DI

SPI Master Input, Slave Output

CSN

SPI Chip Select (0 V = Selected)

4.02 kW 1% Resistor between Ref1 & Ref2

Mechanical Shutter Output Sync (Optional)

Flash Output Sync (Optional)

ADC_Ref1

ADC_Ref2

MSO

AO

DO

FLO

FEN

Frame Enable Reference Output (Optional)

Line Enable Reference Output (Optional)

E06

LEN

1. DI = Digital Input, DO = Digital Output, AO = Analog Output.

2. Tie unused DI pins to Ground, NC unused DO pins.

3. By default Clk_In2 should equal Clk_In1 and should be the same source clock.

4. The RESETN pin has a 62 kW internal pull-up resistor, so if left floating the chip will not be in reset mode.

5. The TRIGGER pin has an internal 100 kW pull down resistor. If left floating (and at default polarity) then the sensor state will not be affected

by this pin (i.e. defaults to ‘not triggered’ mode if floated).

6. All of the DI and DO pins nominally operate at 0 V → 2.0 V and are associated with the VDD_DIG power supply.

Table 5. POWER PIN DESCRIPTION

Name

Voltage

Pins

Description

LVDS Output Supply

VDD_LVDS

3.3 V D

C04, C05, C23, C24, D04, D24, E04, E24, AA04, AA24,

AB04, AB24, AC04, AC05 AC23, AC24

VDD_DIG

AVDD_HV

2.0 V D

C18, C19, D18, D19, E18, AA18, AB18, AB19, AC18, AC19,

C20, C21, C22, D20, D21, D22, D23, E20, E21, E22, AA20,

AA21, AA22, AB20, AB21, AB22, AB23, AC20, AC21,

AC22, AB15, E08

Digital Core Supply

3.5 V A

C11, D11, E11, AA11, AB11, AC11, C10, D10, E10, AA10,

AB10, AC10

Pixel Supply 1

Vref_P

2.8 V A

1.8 V A

0 V

C13, D13, E13, AA13, AB13, AC13

C17, D16, D17, E17, AA17, AB16, AB17, AC17

E09

Pixel Supply 2

AVDD_LV

Vpixel_low

Analog Low Voltage Supply

Pixel Supply 3. Combine with VSS for

normal operation. Can be pulsed for

Extended Dynamic Range Operation.

VSS

0 V

NA

C12, C14, D12, D14, E12, AA12, AB12, AB14, AC12, AC14,

E15, D15, AA09, A02, A14, A26, B14, C03, C06, C25, D03,

D25, E03, E19, E23, E25, AA03, AA19, AA23, AA25, AB25,

AC03, AC06, AC25, AD14, AE02, AE14, AE26

Sensor Ground Reference

No Connect

A01, AC09, E14, E16, C09, D09, D05, D06, D07, AA16,

AB05

Unused and test-only pins. These

pins must be floated.

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KAC−12040

Table 6. LVDS PIN DESCRIPTION

E01

E02

D01

D02

C01

C02

B01

B02

A03

B03

A04

B04

A05

B05

A06

B06

Name

Description

C07

C08

A07

B07

A08

B08

A09

B09

A10

B10

A11

B11

A12

B12

A13

B13

Name

Description

C15

C16

A15

B15

A16

B16

A17

B17

A18

B18

A19

B19

A20

B20

A21

B21

Name

Description

A22

B22

A23

B23

A24

B24

A25

B25

B27

B26

C27

C26

D27

D26

E27

E26

Name

Description

1DCLK+

1DCLK−

1DATA0+

1DATA0−

1DATA1+

1DATA1−

1DATA2+

1DATA2−

1DATA3+

1DATA3−

1DATA4+

1DATA4−

1DATA5+

1DATA5−

1DATA6+

1DATA6−

3DCLK+

3DCLK−

3DATA0+

3DATA0−

3DATA1+

3DATA1−

3DATA2+

3DATA2−

3DATA3+

3DATA3−

3DATA4+

3DATA4−

3DATA5+

3DATA5−

3DATA6+

3DATA6−

5DCLK+

5DCLK−

5DATA0+

5DATA0−

5DATA1+

5DATA1−

5DATA2+

5DATA2−

5DATA3+

5DATA3−

5DATA4+

5DATA4−

5DATA5+

5DATA5−

5DATA6+

5DATA6−

7DCLK+

7DCLK−

7DATA0+

7DATA0−

7DATA1+

7DATA1−

7DATA2+

7DATA2−

7DATA3+

7DATA3−

7DATA4+

7DATA4−

7DATA5+

7DATA5−

7DATA6+

7DATA6−

Bank 1

Bank 3

Bank 5

Bank 7

LVDS Clock

Bank 1

Bank 3

Bank 5

Bank 7

LVDS Data

Name

Description

Name

Description

Name

Description

Name

Description

AA01

AA02

AB01

AB02

AC01

AC02

AD01

AD02

AE03

AD03

AE04

AD04

AE05

AD05

AE06

AD06

0DCLK+

0DCLK−

0DATA0+

0DATA0−

0DATA1+

0DATA1−

0DATA2+

0DATA2−

0DATA3+

0DATA3−

0DATA4+

0DATA4−

0DATA5+

0DATA5−

0DATA6+

0DATA6−

AC07

AC08

AE07

AD07

AE08

AD08

AE09

AD09

AE10

AD10

AE11

AD11

AE12

AD12

AE13

AD13

2DCLK+

2DCLK−

2DATA0+

2DATA0−

2DATA1+

2DATA1−

2DATA2+

2DATA2−

2DATA3+

2DATA3−

2DATA4+

2DATA4−

2DATA5+

2DATA5−

2DATA6+

2DATA6−

AC15

AC16

AE15

AD15

AE16

AD16

AE17

AD17

AE18

AD18

AE19

AD19

AE20

AD20

AE21

AD21

4DCLK+

4DCLK−

4DATA0+

4DATA0−

4DATA1+

4DATA1−

4DATA2+

4DATA2−

4DATA3+

4DATA3−

4DATA4+

4DATA4−

4DATA5+

4DATA5−

4DATA6+

4DATA6−

AE22

AD22

AE23

AD23

AE24

AD24

AE25

AD25

AD26

AD27

AC26

AC27

AB26

AB27

AA26

AA27

6DCLK+

6DCLK−

6DATA0+

6DATA0−

6DATA1+

6DATA1−

6DATA2+

6DATA2−

6DATA3+

6DATA3−

6DATA4+

6DATA4−

6DATA5+

6DATA5−

6DATA6+

6DATA6−

Bank 0

Bank 2

Bank 4

Bank 6

LVDS Clock

Bank 0

Bank 2

Bank 4

Bank 6

LVDS Data

1. All LVDS Data and Clock lines must be routed with 100 W differential transmission line traces.

2. All the traces for a single LVDS Bank should be the same physical length to minimize skew between the clock and data lines.

3. In 2 Bank mode, only LVDS banks 0 and 1 are active.

4. In 4 Bank mode, only LVDS bank 0, 1, 2, and 3 are active.

5. Float the pins of unused LVDS Banks to conserve power.

6. Unused pins in active banks (due to ADC bit depth < 14) are automatically tri-stated to save power, but these can also be floated.

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KAC−12040

IMAGING PERFORMANCE

Table 7. TYPICAL OPERATIONAL CONDITIONS

(Unless otherwise noted, the Imaging Performance Specifications are measured using the following conditions.)

Description

Light Source

Condition

Continuous Red, Green and Blue LED Illumination

Measured Die Temperature: 40°C and 27°C

16.6 ms (1400d LL, Register 0201h)

Notes

1

Temperature

Integration Time

Readout Mode

Clamps

Dual-Scan, Global Shutter, 320 MHz, PLL2

Column/Row Noise Corrections Active, Frame Black Level Clamp Active

10 bit

ADC Bit Depth

Analog Gain

Unity Gain or Referred Back to Unit Gain

1. For monochrome sensor, only green LED used.

Table 8. KAC−12040−ABA CONFIGURATION (MONOCHROME)

Temperature

Wavelength

(nm)

Sampling

Plan

Tested at

(5C)

27

Description

Symbol

QE

Min.

Nom.

Max.

Unit

Test

Peak Quantum Efficiency

%

Design

MAX

Green

NIR1

NIR2

550

850

900

−

53

15

10

−

ke^*

Lux @ s

Responsivity

−

84

−

Design

27

20

21

7.0

V

Lux @ s

Table 9. KAC−12040−CBA CONFIGURATION (BAYER RGB)

Temperature

Tested at

(5C)

Wavelength

(nm)

Sampling

Plan

Description

Symbol

QE

Min.

Nom.

Max.

Unit

Test

Peak Quantum Efficiency

470

540

620

850

900

−

40

47

45

15

10

−

%

Design

27

MAX

Green

NIR1

NIR2

ke^*

Lux @ s

Responsivity

Blue

Green

Red

−

17

35

38

−

Design

27

20

21

Blue

Green

Red

−

1.4

2.9

3.2

−

V

Lux @ s

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7

KAC−12040

Table 10. PERFORMANCE SPECIFICATIONS ALL CONFIGURATIONS

Temperature

Tested at

(5C)

Sampling

Plan

Description

Symbol

Min.

Nom.

Max.

Unit

Test

Notes

−

Photodiode Charge

Capacity

PNe

−

16

−

ke

Die

27, 40

16

−

Read Noise

ne T

−

3.7 RS

25.5 GS

−

e rms

27

8

1

−

Total Pixelized Noise

Dynamic Range

Column Noise

Row Noise

−

4.5 RS

28.3 GS

−

e rms

27

19

1

DR

−

73 RS

56 GS

−

dB

27

1, 4

1, 6

1, 7

1, 5

2

−

C

R

−

0.6 RS

3.0 GS

−

e rms

27

9

10

1

N

−

1.0 RS

5.0 GS

−

e rms

27

−

Dark Field Local

Non-Uniformity Floor

DSNU_flr

PRNU_1

−

3.0 RS

21 GS

−

e rms

27, 40

Bright Field Global

Photoresponse

Non-Uniformity

−

1.5

−

% rms

% pp

2

Bright Field Global Peak to

Peak Photoresponse

Non-Uniformity

PRNU_2

−

6.5

−

Die

27, 40

3

2

Maximum Photoresponse

Non-Linearity

NL

−

6.3

0.3

−

%

Die

27, 40

11

12

3

8

Maximum Gain Difference

between Outputs

DG

Photodiode Dark Current

Storage Node Dark Current

Image Lag

I

−

4.6

1,200

1.3

70

5,000

10

e/p/s

Die

40

13

14

15

7

9

5

PD

e/p/s

VD

−

Lag

Design

27, 40

27

2

Black-Sun Anti-Blooming

X

−

12

> 10,000

−

W/cm

14

10

AB

xllumSat

Parasitic Light Sensitivity

Dual-Video WDR

PLS

−

730

−

Design

27

6

−

140 RS

120 GS

−

dB

1, 11,

12

Pulsed Pixel WDR

(GS Only)

−

100

−

dB

Design

27

12, 13

1. RS = Rolling Shutter Operation Mode, GS = Global Shutter Operation Mode.

2. Measured per color, worst of all colors reported.

3. Value is over the range of 10% to 90% of photodiode saturation, Green response used.

−

4. Uses 20LOG (PNe / ne T).

5. Photodiode dark current made negligible.

6. Column Noise Correction active.

7. Row Noise Correction active.

8. Measured at ~70% illumination.

9. Storage node dark current made negligible.

10.GSE (Global Shutter Efficiency) = 1 − 1 / PLS.

11. Min vs Max integration time at 30 fps.

12.WDR measures expanded exposure latitude from linear mode DR.

13.Min/Max responsivity in a 30 fps image.

14.Saturation Illumination referenced to a 3 line time integration.

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KAC−12040

TYPICAL PERFORMANCE CURVES

Figure 4. Monochrome QE (with Microlens)

Figure 5. Bayer QE (with Microlens)

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KAC−12040

Angular Quantum Efficiency

For the curves marked “Horizontal”, the incident light angle is varied along the wider array dimension.

For the curves marked “Vertical”, the incident light angle is varied along the shorter array dimension.

Figure 6. Monochrome Relative Angular QE (with Microlens)

Figure 7. Bayer Relative Angular QE (with Microlens)

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KAC−12040

Dark Current vs. Temperature

NOTE: “Dbl” denotes an approximate doubling temperature for the dark current for the displayed temperature range.

Figure 8. Dark Current vs. Temperature

Power vs. Frame Rate

The most effective method to use the maximum PLL2

operations are suspended during Vertical Blanking

conserving significant power consumption and also

minimizing the image storage time on the storage node when

in Global Shutter Operation.

speed (313 → 320 MHz) and control frame rate with

minimum Power and maximum image quality is to adjust

Vertical Blanking. (register 01F1h). Unnecessary chip

NOTE: The LVDS clock is ½ the PLL2 clock speed.

Figure 9. Power vs. Frame Rate, 10 bit Mode

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KAC−12040

Power and Frame Rate vs. ADC Bit Depth

Increasing the ADC bit depth impacts the frame rate by

changing the ADC conversion time. The following figure

shows the power and Frame rate range for several typical

cases.

Figure 10. ADC Bit Depth Impact on Frame Rate and Power

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KAC−12040

DEFECT DEFINITIONS

Table 11. OPERATION CONDITIONS FOR DEFECT TESTING

Description

Condition

Notes

Operational Mode

10 bit ADC, 8 LVDS Outputs, Global Shutter and Rolling Shutter Modes,

Dual-Scan, Black Level Clamp ON, Column/Row Noise Corrections ON,

1× Analog Gain, 1× Digital Gain

Pixels per Line

Lines per Frame

Line Time

4,000

3,000

8.7 ms

Frame Time

13.9 ms

Photodiode Integration Time

Storage Readout Time

Temperature

33 ms

13.9 ms

40°C and 29°C

Light Source

Continuous Red, Green and Blue LED Illumination

Nominal Operating Voltages and Timing, PLL1 = 320 MHz, Wafer Test

1

Operation

1. For monochrome sensor, only the green LED is used.

Table 12. DEFECT DEFINITIONS FOR TESTING

Description

Definition

Limit

Test

Notes

Dark Field Defective Pixel

30°C

40°C

120

4

1, 4, 5

RS: Defect ≥ 20 dn

GS: Defect ≥ 180 dn

RS: Defect ≥ 30 dn

GS: Defect ≥ 240 dn

Bright Field Defective Pixel

Cluster Defect

Defect ≥ 12% from Local Mean

120

22

5

2, 5

3

A group of 2 to 10 contiguous defective pixels, but

no more than 3 adjacent defects horizontally.

Column/Row Major Defect

A group of more than 10 contiguous defective pixels

along a single column or row.

0

Dark Field Faint Column/Row Defect

Bright Field Faint Column/Row Defect

1. RS = Rolling Shutter, GS = Global Shutter.

RS: 3 dn Threshold

GS: 10 dn Threshold

17

18

1

RS: 12 dn Threshold

GS: 18 dn Threshold

2. For the color devices, all bright defects are defined within a single color plane, each color plane is tested.

3. Cluster defects are separated by no less than two good pixels in any direction.

4. Rolling Shutter Dark Field points are dominated by photodiode integration time, Global Shutter Dark Field defects are dominated by the

readout time.

5. The net sum of all bright and dark field pixel defects in rolling and global shutter are combined and then compared to the test limit.

Defect Map

The defect map supplied with each sensor is based upon

testing at an ambient (29°C) temperature. All defective

pixels are reference to pixel (0, 0) in the defect maps. See

Figure 11 for the location of pixel (0, 0).

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KAC−12040

TEST DEFINITIONS

Test Regions of Interest

Image Area ROI:

Active Area ROI:

Center ROI:

Pixel (0, 0) to Pixel (4015, 3015)

Pixel (8, 8) to Pixel (3999, 2999)

Pixel (1958, 1458) to Pixel (2057, 1557)

Only the Active Area ROI pixels are used for performance and defect tests.

88

8

B

G

R

B

G

R

4000 (H) y 3000 (V)

4.7 mm Pixel

8,8

0,0

B

G

R

8

88

Figure 11. Regions of Interest

Test Descriptions

The highest sub-ROI average (Maximum Signal) and the

lowest sub-ROI average (Minimum Signal) are then used in

the following formula to calculate PRNU_2.

1) Dark Field Local Non-Uniformity Floor (DSNU_flr)

This test is performed under dark field conditions.

A 4 frame average image is collected. This image is

partitioned into 300 sub-regions of interest, each of which is

200 by 200 pixels in size. For each sub-region the standard

deviation of all its pixels is calculated. The dark field local

non-uniformity is the largest standard deviation found from

Max. Signal * Min. Signal

_{PRNU_2 + 100 @}ǒ

Units : % pp

Ǔ

Active Area Signal

4) Dark Field Defect Test

−

This test is performed under dark field conditions.

The sensor is partitioned into 300 sub regions of interest,

each of which is 128 by 128 pixels in size. In each region of

interest, the median value of all pixels is found. For each

region of interest, a pixel is marked defective if it is greater

than or equal to the median value of that region of interest

plus the defect threshold specified in the Defect Definition

Table section.

all the sub regions of interest. Units: e rms (electrons rms).

2) Bright Field Global Photoresponse Non-Uniformity

(PRNU_1)

The sensor illuminated to 70% of saturation (~700 dn). In

this condition a 4 frame average image is collected. From

this 4 frame average image a 4 frame average dark image is

subtracted. The Active Area Standard Deviation is the

standard deviation of the resultant image and the Active

Area Signal is the average of the resultant image.

5) Bright Field Defect Test

This test is performed with the imager illuminated to

a level such that the output is at approximately 700 dn.

The average signal level of all active pixels is found.

The bright and dark thresholds are set as:

Active Area Standard Deviation

_{PRNU_1 + 100 @}ǒ

Ǔ

Active Area Signal

Units : % rms

Dark Defect Threshold = Active Area Signal ⋅ Threshold

Bright Defect Threshold = Active Area Signal ⋅ Threshold

3) Bright Field Global Peak to Peak Non-Uniformity

(PRNU_2)

This test is performed with the sensor uniformly

illuminated to 70% of saturation (~700 dn), a 4 frame

average image is collected and a 4 frame averaged dark

image is subtracted. The resultant image is partitioned into

300 sub regions of interest, each of which is 200 by

200 pixels in size. The average signal level of each sub

regions of interest (sub-ROI) is calculated.

The sensor is then partitioned into 300 sub regions of

interest, each of which is 128 by 128 pixels in size. In each

region of interest, the average value of all pixels is found.

For each region of interest, a pixel is marked defective if it

is greater than or equal to the median value of that region of

interest plus the bright threshold specified or if it is less than

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14

KAC−12040

or equal to the median value of that region of interest minus

7) Black-Sun Anti-Blooming

the dark threshold specified.

Example for bright field defective pixels:

• Average value of all active pixels is found to be 700 dn

• Lower defect threshold: 700 dn ⋅ 12% = 84 dn

• A specific 128 × 128 ROI is selected:

♦ Median of this region of interest is found to be

690 dn.

A typical CMOS image sensor has a light response profile

that goes from 0 dn to saturation (1023 dn for KAC−12040

in 10 bit ADC mode) and, with enough light, back to 0 dn.

The sensor reaching 0 dn at very bright illumination is often

called the “Black-sun” artifact and is undesirable. Black-sun

artifact is typically the dominant form of anti-blooming

image distortion. For the KAC−12040 the Black-sun artifact

threshold is measured at the onset of saturation distortion,

not at the point where the output goes to 0 dn. To first order

the onset of black-sun artifact for the KAC−12040 is not

proportional to the integration time or readout time.

The sensor is placed in the dark at unity gain and

illuminated with a 532 nm laser with the intensity of about

♦ Any pixel in this region of interest that is

≤ (690 − 84 dn) in intensity will be marked

defective.

♦ Any pixel in this region of interest that is

≥ (690 − 84 dn) in intensity will be marked

defective.

2

26 W/cm at the center of the sensor. The laser is strong

• All remaining 299 sub regions of interest are analyzed

enough to make the center of the laser spot below 1020 dn

without any ND filters. ND filters are added to adjust the

laser intensity until the signal in the region at the center of

the spot increases to > 1020 dn.

for defective pixels in the same manner.

6) Parasitic Light Sensitivity (PLS)

Parasitic Light Sensitivity is the ratio of the light

sensitivity of the photodiode to the light sensitivity of the

storage node in Global Shutter. There is no equivalent

distortion in Rolling Shutter. A low PLS value can provide

distortion of the image on the storage node by the scene

during readout.

This illumination intensity at this ND filter is recorded

2

(W/cm ) as the Black-Sun Anti-blooming.

The ‘xIlumSat’ unit is calculated using and integration

time of 100 msec.

Exposing the sensor to very strong illumination for

extended periods of time will permanently alter the sensor

performance in that localized region.

Photodiode Responsivity

PLS +

(UnitlessRatio)

Storage Node Responsivity

8) Read Noise

GSE (Global Shutter Efficiency) is a related unit.

This test is performed with no illumination and one line of

integration time. The read noise is defined as one standard

deviation of the frequency histogram containing the values

of all pixels after the excessively deviant pixels ( three

standard deviations) are removed.

1

PLS

_{GSE +}ǒ_{1 *}Ǔ_%

Detailed Method: Photodiode Responsivity:

The sensor is set in global shutter serial mode (integration

time not overlapping readout) and the FLO signal is used to

control a 550 nm normal incident (or large f# focused)

illumination source so that the sensor is illuminated only

during photodiode integration time (not illuminated during

readout time). The integration time is not critical but should

be large enough to create a measurable mean during this

time. A 16 frame-average illuminated photodiode image is

recorded. A 16 frame-average dark frame using the same

sensor settings is captured and is subtracted from the

illuminated image.

9) Column Noise

After all rows are averaged together. Shading (low

frequency change wrt column address) is removed.

A frequency histogram is constructed of the resulting

column values. The column noise is the standard deviation

of the frequency histogram of the column values.

10) Row Noise

All columns are averaged together. Shading (low

frequency change wrt row address) is removed. A frequency

histogram is constructed of the resulting row values.

The row noise is the standard deviation of the frequency

histogram of the row values.

Detailed Method: Storage Node Responsivity:

The sensor is set to a special characterization mode where

the PD signal is discarded and does not impact the storage

node. A long total frame time (storage node exposure time)

is used to increase the storage node signal. A 16

frame-average dark frame is captured. The sensor is

illuminated by the same 550 nm incident light source used

for the photodiode responsivity. A 16 frame-average

illuminated photodiode image is recorded; the dark frame

image is subtracted from this. The integration time is not

critical but should be set such that a significant response is

detected, typically several orders of magnitude greater than

the photodiode integration time.

11) Maximum Photoresponse Non-Linearity

The photoresponse non-linearity is defined as the

deviation from the best fit of the sensor response using 70%

of saturation and zero signal as the reference points.

The different signal levels are determined by varying the

integration time. The sensor saturation level is (1023-dark

offset). The dark offset is subtracted from the image for the

following M

and L

.

AVG

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15

KAC−12040

Analog gain is set to 8. With no illumination a 64 average

dark image is recorded (Dark_ref). The ‘el-per-DN’ is

measured using the photon transfer method.

• The integration time is varied until the integration time

required to reach the 70% saturation is determined.

M

AVG

= the active array mean at the 70% saturation

Illumination is adjusted blink every other frame such that

the mean image output is 70% of the Photodiode Charge

Capacity for even frames, and with no illumination for odd

frames. A 64 frame average of Odd Dark Frames is recorded

as Dark_Lag.

integration time.

• The integration is set to 1/14 (5% exposure point).

L

= meant at the 5% exposure point.

AVG

• PRNL (@ 5% saturation) = ((L

⋅ 100

/M

AVG AVG

) ⋅ (14/1) −1)

(

)

Lag + Dark_Lag * Dark_Ref @ el−per−DN

12) Maximum Gain Difference between Outputs

Units : Electrons rms

The sensor contains two ADC and four channels of analog

data in its highest frame rate configuration. The sensor is

factory calibrated to reduce the gain differences between the

channels. The gain variations are manifest as a row oriented

pattern where every other row uses a different ADC. Using

triple scan read out mode, an additional two analog channels

are introduced resulting in a four row pattern. With one

channel (‘Top Ping’) used as the reference, the residual gain

difference is defined as:

16) Photodiode Charge Capacity

The sensor analog gain is reduced to < 1 to prevent ADC

clipping at 1023 dn. The ‘el-per-DN’ is measured using the

photon transfer method. The sensor is illuminated at a light

level ~1.5x the illumination at which the pixel output no

longer linearly changes with illumination level.

The Photodiode Charge Capacity is equal to the average

signal (DN) ⋅ el-per-DN. Units: electrons rms.

Bottom Ping Row Average

17) Dark Field Faint Column/Row Defect

ǒ

_{* 1}Ǔ_{@ 100}

Top Ping Row Average

A 4 frame average, no illumination image is acquired at

one line time of integration. Major defective pixels are

removed (> 5 Sigma). All columns or rows are averaged

together. The average of the local ROI of 128 columns or

rows about the column/row being tested is determined. Any

columns/rows greater than the local average by more than

the threshold are identified.

Top Pong Row Average

Top Ping Row Average

ǒ

_{* 1}Ǔ_{@ 100}

Bottom Pong Row Average

Top Ping Row Average

ǒ

_{* 1}Ǔ_{@ 100}

13) Photodiode Dark Current

18) Bright Field Faint Column/Row Defect

The photodiode dark current is measured in rolling shutter

read out mode using 105 ms integration time and an analog

gain = 8. The value is converted to electrons/pix/sec using

the formula:

A 4 frame average, 70% illumination image is acquired at

one line time of integration. Major defective pixels are

removed (> 5 Sigma). All columns or rows are averaged

together. The average of the local ROI of 128 columns or

rows about the column/row being tested is determined. Any

columns/rows greater than the local average by more than

the threshold are identified.

el−per−DN (gain=8)

Photodiode Dark Current + Aver. Signal (DN) @

0.105 seconds

where ‘average signal (DN)’ is the average of all pixels in

the sensor array, and ‘el-per-DN (gain=8)’ is measured on

each sensor using the photon transfer method.

19) Total Pixelized Noise

This test is performed with no illumination and one line of

integration time. A single image is captured including both

Temporal and Fixed Pattern Noise (FPN). A spatial low pass

filter is applied to remove shading and deviant pixels

( three standard deviations) are removed. The Total

Pixelized Noise is defined as one standard deviation of the

frequency histogram.

14) Storage Node Dark Current

The storage node dark current is measured in global

shutter read out mode using a special timing mode to prevent

the photodiode dark current from being transferred to the

storage node. In global shutter mode, the integration time of

the storage node is the time it takes to read out a frame. The

sensor analog gain is set to 2:

−

20) Responsivity ke /lux-sec

el−per−DN (gain=2)

Storage Node Dark Current + Aver. Signal (DN) @

This number is calculated by integrating the

multiplication of the sensor QE by the human photopic

response assuming a 3200K light source with a QT100 IR

filter. This is a sharp 650 nm cutoff filter. If the IR filter is

removed a higher response value will result.

0.138 seconds

where ‘average signal (DN)’ is the average of all pixels in

the sensor array and ‘el-per-DN (gain=2)’ is measured on

each sensor using the photon transfer method.

15) Lag

21) Responsivity V/lux-sec

Lag is measured as the number of electrons left in the

photodiode after readout when the sensor is illuminated at

70% of Photodiode Charge Capacity.

Voltage levels are not output from the sensor. This metric

uses the pixel output in volts at the ADC input for 1x Analog

Gain.

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16

KAC−12040

OPERATION

This section is a brief discussion of the most common

features and functions assuming default conditions. See the

KAC−12040 User Guide for a full explanation of the sensor

operation modes, options, and registers.

All SPI reads are to an even address, all SPI writes are to an

odd address.

Sensor States

Figure 12 shows the sensor states, see the KAC−12040

User Guide for detailed explanation of the States.

Register Address

The last bit of any register address is a Read/Write bit.

Most references in this document refer to the Write address.

RESETN low or

RESET

reset Reg 4060h

<35µ s

STANDBY

<2µ s

150µ s

CONFIG

WAKE−UP

(50 ms)

<2µ s

Slave Integration Mode

<50µ s

TRIG_WAIT

TRIGGER Active Edge

IDLE

End of

acquisition

<2µ s

RUNNING mode OR

TRIGGER pin

<50µ s

End of acquisition AND

IDLE mode AND

No TRIGGER

EXT_INT

TRIGGER Inactive Edge

RUNNING

READOUT

Figure 12. Sensor State Diagram

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17

KAC−12040

Encoded Syncs

the following Figure 13. This is performed for each of the

8 LVDS output banks providing frame, line, and output

synchronization. See the KAC−12040 User Guide for

additional detail on LVDS and Encoded Sync output.

To facilitate system acquisition synchronization the

KAC−12040 places synchronization words (SW) at the

beginning and at the end of each output row as indicated in

V Blanking Period

SOF

SOL

Data

EOL

EOF

V Blanking Period

Line Length (LL)

Figure 13. Encoded Frame Syncs

Line Time

This Datasheet presumes the recommended startup script

that is defined in the KAC−12040 User Guide has been

applied. The KAC−12040 defaults to Dual-Scan mode. In

this mode the LVDS data readout overlaps the pixel readout

and ADC conversion time. The Pixel and ADC conversion

time are fixed (for 10 bit operation) and total ~8.66 ms.

The LVDS time will be dependent on the PLL2 frequency

selected. If the PLL2 < 313 MHz, then the LVDS data

readout will dominate the row time. For PLL2 > 313 MHz,

the Pixel + ADC will set the minimum Line Time. The Line

Time is not impacted by the selection of Rolling Shutter or

Global Shutter mode.

The KAC−12040 architecture always outputs two rows at

once, one row from the top ADC, and one from the bottom

ADC. Each ADC then divides up the pixel into 1 → 4

parallel pixel output LVDS Banks. The default is 4 output

banks per ADC for a total of 8 parallel pixel outputs to

minimize the LVDS data output time. Since the sensor

always outputs 2 rows at a time the timing and registers are

based on a Line Time (LT) or Line Length (LL) where one

LT = the time to readout 2 rows in parallel (one even row and

one odd row).

Line

10 bit ADC n+1

Wait

Pixel n+1

4.30 ms

4.36 ms

8 Bank LVDS Output n

LVDS Clock = 160 MHz

8.44 ms

Line n Time = Line Length Register (0201h) = 1400

8.75 ms

Figure 14. Default Line Time (Dual-Scan) with PLL2 = 320 MHz

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18

KAC−12040

Frame Time

By default the Integration Phase overlaps the Readout and

Frame Wait Phases. If the Integration Phase is larger than the

Readout + Frame Wait time, then the Integration Phase will

determine the video frame rate. Otherwise the frame rate

will be set by the Readout + Frame Wait time. In other words,

if the programmed integration time is larger than the

minimum readout time (and vertical blanking) then extra

vertical blanking will be added and the frame rate will slow

to accommodate the requested integration time.

The frame time is defined in units of Line Time. 1 Line

Time unit = 2 output rows. To first-order the frame rate is not

directly impacted by selection of Global Shutter, Rolling

Shutter, Dual-Scan, or Tri-Scan.

The Frame Time is made up of three phases:

1. Integration Phase

2. Readout Phase

3. Frame Wait Phase (Vertical Blanking, V

)

BLANK

8.34 ms by Default (952 Line Times)

Integration Phase Frame m

Integration Phase Frame m+1

Integration Phase Frame m+2

Frame

Readout Phase Frame m

Wait

Frame

Wait

Readout Phase Frame m+1

13.79 ms by Default

(1576 Line Times)

Single Frame of Video Overhead

13.80 ms by Default

~0.01 ms

(1 Line Time)

Video Frame Time = Readout + Wait

Figure 15. Default Frame Time Configuration (Frame A)

If the Integration Phase is less than the Readout Phase then

the start of integration is automatically delayed to minimize

the storage time and dark current.

Integration Phase Frame m

Integration Phase Frame m+1

Integration Phase Frame m+2

Frame

Wait

Frame

Wait

Readout Phase Frame m

Readout Phase Frame m+1

Video Frame Time = Integration Time

Figure 16. Frame Time with Extended Integration Time

If the Readout Phase (+ V

) is less than the

See the KAC−12040 User Guide for detailed calculation

of the Integration Phase, Readout Phase, and Frame Wait.

To first-order the Readout Phase is equal to the number of

rows ⋅ row_time.

BLANKING

Integration Phase, then the readout occurs as soon the

integration is complete to minimize the storage time and

dark current.

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19

KAC−12040

Global Shutter Readout

Global Shutter readout provides the maximum precision

for freezing scene motion. Any motion artifacts will be

100% defined by an ideal integration time edge. Every pixel

in the array starts and stops integration at the same time.

Figure 17 illustrates a Global Shutter Frame readout

assuming the recommended Start-up Script defined in the

KAC−12040 User Guide (8 LVDS banks, Dual-Scan,

8.75 ms line time). The Frame Wait Phase is not shown due

to its small default size (1 LL) and for clarity.

Global Shutter readout mode is selected using Bits [1:0]

of Register 01D1h.

Images can be initiated by setting and holding the

TRIGGER input pin or by placing the sensor into

RUNNING mode by writing 03d to register 4019h. If the

TRIGGER input pin is true when at the start of the

integration time for the next frame then the sensor will

complete an additional frame integration and readout. In the

case shown in Figure 17 two frames will be output.

Integration of Next Frame Overlaps

Readout of Previous Frame

Integration Time = 8.33 ms

Frame Readout = 13.80 ms

Time/Col Address Axis

Effective Frame Time (Video) = Readout Time

Trigger Pin: True = 2.0 V

Figure 17. Illustration of Frame Time for Global Shutter Readout

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20

KAC−12040

Rolling Shutter Readout

The KAC−12040 high speed Rolling Shutter readout

provides the maximum dynamic range while still providing

excellent motion capture. In Rolling Shutter the readout

more closely matches a film camera shutter. Each row of the

image receives the same integration time, but each row starts

and ends at a different time as the shutter travels from the top

of the array to the bottom. In the Figure 18 frame time

illustration this ‘moving shutter’ displays as a sloped edge

for the blue pixel array region, just as the readout edge is

sloped.

The Figure 18 illustration shows a 2 frame output

sequence using the external TRIGGER pin.

Integration of Next Frame Overlaps

Readout of Previous Frame

Integration Time = 8.33 ms

Frame Readout = 13.80 ms

Time/Col Address Axis

Effective Frame Time (Video) = Readout Time

Trigger Pin: True = 2.0 V

Figure 18. Illustration of Frame Time for Rolling Shutter Readout

Rolling Readout mode can be selected using Bits [1:0] of

Register 01D1h.

Images can be initiated by setting and holding the

TRIGGER input pin or by placing the sensor into

RUNNING mode by writing 03d to register 4019h. If the

TRIGGER input pin is True when at the start of the

integration time for the next frame then the sensor will

complete an additional frame integration and readout.

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21

KAC−12040

8 BANK LVDS DATA READOUT

LVDS Banks

The KAC−12040 provides 8 parallel pixel banks, each

consisting of 8 LVDS differential pairs (7 data pairs + 1clock

pair). This allows the output of 8 pixels per LVDS clock

period. All 7 data pairs, of each bank, are used only in 14 bit

operation mode. By default only 5 data pairs are used for

10 bit mode (D4 → D0). The unused pairs are held in

low-power high impedance mode.

Bank 3

Bank 5

Bank 7

Bank 3

Bank 5

Bank 7

Bank 3

Bank 5

Bank 7

Pixel Array

2 Bank Mode

4 Bank Mode

8 Bank Mode

Bank 2

Bank 4

Bank 6

Bank 2

Bank 4

Bank 6

Bank 2

Bank 4

Bank 6

Figure 19. LVDS Bank Labeling

The number of output banks used is independent of the

ADC bit depth chosen. By default the KAC−12040 uses all

8 output banks for maximum frame rate. If technical

restrictions prevent the use of 8 LVDS banks, the sensor can

be programmed to use 4 or 2 banks, however this can result

in reduced frame rate and reduction of image quality. It is

recommended that 8 banks be used when possible. Only the

8 bank option is discussed in detail in this specification, see

the KAC−12040 User Guide for additional detail on 4 and 2

bank mode.

In order to minimize the LVDS clock rate (and power) for

a given data rate the pixels are output in DDR (Double Data

Rate) where the MSB is always sent first (on rising edge) and

the LSB second (falling edge) This is not programmable.

Ports per LVDS Bank

The MSB comes out first on the falling edge, followed by

the LSB on the net rising edge.

Table 13. NUMBER OF LVDS PAIRS (PORTS) USED VS. BIT DEPTH

Bit Depth

Edge of DATA CLK

Falling (MSB Nibble)

Rising (LSB Nibble)

Falling (MSB Nibble)

Rising (LSB Nibble)

Falling (MSB Nibble)

Rising (LSB Nibble)

Falling (MSB Nibble)

Rising (LSB Nibble)

Data0

D7

Data1

D8

Data2

D9

Data3

D10

D3

Data4

D11

D4

Data5

D12

D5

Data6

D13

D6

14 bits

D0

D1

D2

12 bits

10 bits

8 bits

D6

D7

D8

D9

D10

D4

D11

D5

HiZ

D0

D1

D2

D3

D5

D6

D7

D8

D9

HiZ

D0

D1

D2

D3

D4

D5

D6

D7

HiZ

D0

D1

D2

D3

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22

KAC−12040

8 Bank Pixel Order

The KAC−12040 always processes two rows at a time.

Even row decodes are sent to the bottom ADC and LVDS

output banks (0, 2, 4, 6). Odd rows are sent to the top ADC

and LVDS banks (1, 3, 5, 7). The ROI must be (and is

internally forced to) an even size and always starting on an

even row decode.

The rows are read out progressively left to right (small

column address to large). Eight pixels are sent out of the chip

at once, one pixel per LVDS bank per LVDS clock cycle.

Pixel Readout order:

4. Each LVDS Bank outputs one pixel per clock

cycle, so 4 pixels of each row are output each full

LVDS clock cycle, two rows in parallel for

8 pixels per clock cycle total.

5. The pixels are sent out from left to right

(low column number to high column number).

So the first 4 pixels are sent out on clock cycle 1,

and the next 4 pixels to the right are sent out on

clock cycle 2.

6. To conserve the number of wires per port,

the 10 bits per pixel are sent out DDR (Dual Data

Rate) over 5 ports. On the falling edge the upper

5 MSB bits are sent out, and on the rising edge the

lower 5 bits LSB are sent out. Completing one full

LVDS clock cycle and one set of eight pixels.

1. Two rows are selected, the even row is sent to

the bottom ADC and the odd row to the top ADC.

2. Each ADC converts its row of pixel data at once

and stores the result in a line buffer.

3. At default settings there are 4 output LVDS banks

for each ADC.

Bank 3

Bank 5

Bank 7

0

1

2

3

4

5

6

7

Row 2n +1

Row 2n

5

Bank 2

Bank 4

Bank 6

First CLK−DATA

Pulse

Second CLK−DATA

Pulse

Figure 20. Pixel Readout Order Diagram

Table 14. PIXEL READOUT ORDER TABLE

LVDS Bank

Bank 0

Bank 2

Bank 4

Bank 6

Bank 1

Bank 3

Bank 5

Bank 7

Row

Pixel Number

2n (Even)

2n+1 (Odd)

0

1

2

3

0

1

2

3

1

4

5

6

7

4

5

6

7

2

8

9

12

13

14

15

12

13

14

15

4

16

17

18

19

16

17

18

19

5

10

11

8

9

10

11

3

LVDS Clock Cycle

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23

KAC−12040

De-Serializer Settings

Figure 21 shows the data stream of one LVDS bank for

10 bit resolution.

Data serialization is fixed at 2 cycle DDR for all bit depths.

Data output order is MSB first on the falling edge, and LSB

following on the rising edge.

The SOL/SOF synchronization words are sent out of each

LVDS bank before the first valid pixel data from that bank.

Each bank outputs all 4 syncs of the SOF or SOL.

And each of the active LVDS banks each output all 4 sync

codes for the EOL/EOF.

Four pixel values per synchronization word are embedded

into the video stream per LVDS bank.

Dclk0

Data0 D5 D0 D5 D0 D5 D0 D5 D0 D5 D0 D5 D0 D5 D0 D5 D0

Data1 D6 D1 D6 D1 D6 D1 D6 D1 D6 D1 D6 D1 D6 D1 D6 D1

Data2 D7 D2 D7 D2 D7 D2 D7 D2 D7 D2 D7 D2 D7 D2 D7 D2

Data3 D8 D3 D8 D3 D8 D3 D8 D3 D8 D3 D8 D3 D8 D3 D8 D3

Data4 D9 D4 D9 D4 D9 D4 D9 D4 D9 D4 D9 D4 D9 D4 D9 D4

MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB

D5 D0 D5 D0 D5 D0 D5 D0 D5 D0 D5 D0

D6 D1 D6 D1 D6 D1 D6 D1 D6 D1 D6 D1

D7 D2 D7 D2 D7 D2 D7 D2 D7 D2 D7 D2

D8 D3 D8 D3 D8 D3 D8 D3 D8 D3 D8 D3

D9 D4 D9 D4 D9 D4 D9 D4 D9 D4 D9 D4

MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB

SW1

SW2

SW3

SW4

P0

P1

P2

P3

PN−1

PN

SW1

SW2

SW3

SW4

t

Synchronized Word on 10 bits

Data on 10 bits

Synchronized Word on 10 bits

Figure 21. Data Stream of One LVDS Bank for 10 bits ADC Resolution

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24

KAC−12040

REGISTER DEFINITION

Table 15. REGISTER DEFINITION

16 bit

Default Value

Write Address (Hex)

Hex/Dec

420d

2176d

80d

3856d

0d

SPI State

Group

Register Name

Frame A ROI y1

0001

0009

0011

0019

0021

0029

0031

0039

0041

0049

0051

0059

0061

0069

0071

0079

0081

0089

0091

0099

00A1

00A9

00E9

00F1

00F9

0101

0109

0111

0119

0121

0129

0131

0139

0141

0149

0151

0159

0161

0169

0171

0179

0181

0189

0191

Any

Frame A Definition

Frame B Definition

Frame A ROI h1

Frame A ROI x1

Frame A ROI w1

Frame A sub-ROI y2

Frame A sub-ROI h2

Frame A sub-ROI x2

Frame A sub-ROI w2

Frame A sub-ROI y3

Frame A sub-ROI h3

Frame A sub-ROI x3

Frame A sub-ROI w3

Frame A sub-ROI y4

Frame A sub-ROI h4

Frame A sub-ROI x4

Frame A sub-ROI w4

Frame A Decimation

Frame A Video Blanking

Frame A Integration Lines

Frame A Integration Clocks

Frame A Black Level

Frame A Gain

0d

0033d

0d

800d

0d

10d

001Fh

0d

Frame B ROI y1

3016d

0d

Frame B ROI h1

Frame B ROI x1

4016d

0d

Frame B ROI w1

Frame B sub-ROI y2

Frame B sub-ROI h2

Frame B sub-ROI x2

Frame B sub-ROI w2

Frame B sub-ROI y3

Frame B sub-ROI h3

Frame B sub-ROI x3

Frame B sub-ROI w3

Frame B sub-ROI y4

Frame B sub-ROI h4

Frame B sub-ROI x4

Frame B sub-ROI w4

Frame B Decimation

Frame B Video Blanking

Frame B Integration Lines

Frame B Integration Clocks

Frame B Black Level

Frame B Gain

0d

033h

0d

800d

0d

10d

001Fh

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25

KAC−12040

Table 15. REGISTER DEFINITION (continued)

16 bit

Write Address (Hex)

Default Value

Hex/Dec

SPI State

CONFIG Only

CONFIG or IDLE

Any

Description

Config1

01D1

01D9

01E1

01E9

01F1

01F9

0201

0209

0211

0219

0709

0711

0719

2059

2099

20A1

2449

2479

2481

2499

24A1

24B9

24C1

24C9

24D1

24D9

24E1

24E9

24F1

24F9

2501

2559

2561

25C1

25C9

2619

2D89

4001

4009

4011

4019

4021

CC11h

0000h

000Ah

0000h

0d

Config2

Analog/Digital Power Mode

Dual-Video Repetition

Vertical Blanking

Fixed Frame Period

Line Length (LL)

ADC Bit Depth

1938d

1376d

0028h

0000h

0300h

2877h

0861h

0432h

10ABh

20C7h

0011h

0220h

202d

FLO Edge

MSO Edge

CFA Feedback

Any

Temperature Sensor FB

General Feedback

Output Bank Select 1

PLL1 Setting

Any

CONFIG Only

Any

PLL2 Setting

Sub-LVDS Enable

Column Clamp Threshold A

Column Clamp Threshold B

Test Pattern Control 1

Test Pattern Control 2

Slope 1 Length

Any

CONFIG or IDLE

CONFIG Only

Any

101d

Slope 2 Length

101d

Slope 3 Length

101d

Slope 4 Length

101d

Slope 5 Length

420d

Slope 6 Length

0083g

038Fh

0FBFh

1F9Fh

4804h

0006h

0003h

000Ah

000Bh

0000h

4100h

0011h

0080h

0000h

Slope 1/2 Gain

Slope 3/4 Gain

Slope 5/6 Gain

Slope 7 Gain

Defect Avoidance Threshold

Defect Avoidance Enable

Encoded Sync Config

LVDS Power-Down

Output Bank Select 2

FLO/MSO Polarity

Chip Revision Code

Chip ID Code MSB

Chip ID Code LSB

Set Sensor State

OTP Address

Any

CONFIG or IDLE

CONFIG Only

Any

CONFIG or IDLE

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26

KAC−12040

Table 15. REGISTER DEFINITION (continued)

16 bit

Write Address (Hex)

Default Value

Hex/Dec

SPI State

Description

OTP Write Data

Command_Done_FB

OTP Read Data

Soft Reset

4029

4031

4041

4061

0000h

CONFIG or IDLE

NOTES: SPI State (the Sensor State from which the register can be set):

1. “Any”: Can be written from any state (including RUNNING).

2. “CONFIG or IDLE”: These registers can be changed in IDLE or CONFIG states.

3. “CONFIG Only”: Sensor must be in CONFIG state to set these registers.

4. Only Register 4018h and 4060h may be set when the sensor is in STANDBY state.

NOTES: Decimal, hexadecimal, binary values:

1. “b” denotes a binary number, a series of bits: MSB is on the left, LSB is on the right.

2. “h” or “hex” denotes a hexadecimal number (Base 16, 1−9, A−F). The letters in a hex number are always capitalized.

3. “d” denotes a decimal number.

4. Note that “0” and “1” are the same value in all number base systems and sometimes the base notation is omitted.

The KAC−12040 features an embedded microprocessor by Cortus.

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27

KAC−12040

ABSOLUTE MAXIMUM RATINGS

For Supplies and Inputs the maximum rating is defined as

a level or condition that should not be exceeded at any time.

If the level or the condition is exceeded, the device will be

degraded and may be damaged. Operation at these values

will reduce Mean Time to Failure (MTTF).

Table 16. SUPPLIES

Description

Value

−0.25 V; 2.3 V

AVDD_LV, VDD_DIG

AVDD_HV, Vref_P, VDD_LVDS

DC Input Voltage at Any Input Pin

−0.25 V; 4 V

−0.25 V; VDD_DIG + 0.25 V

Table 17. CMOS INPUTS

Parameter

Input Voltage Low Level

Input Voltage High Level

Symbol

Minimum

−0.3

Typical

Maximum

Unit

V

IL

−

0.35 VDD_DIG

VDD_DIG + 0.3

V

IH

0.65 VDD_DIG

V

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28

KAC−12040

OPERATING RATINGS

Table 18. INPUT CLOCK CONDITIONS

Parameter

Minimum

Typical

Maximum

Unit

MHz

%

Frequency for Clk_In1 and Clk_In2

Duty Cycle for Clk_In1 and Clk_In2

RESETN

45

40

10

20

48

50

−

50

60

−

ns

TRIGGER Pin Minimum Pulse Width

−

ns

TRIGGER must be active at least 4 periods of PLL1 (~12.5 ns at 320 MHz) to start a capture cycle. The polarity of the active

level is configurable by SPI (Register 01D8h Bit 0), the default is active high (i.e. pin = VDD_DIG = trigger request).

Table 19. OPERATING TEMPERATURE

Description

Symbol

Minimum

Maximum

Unit

Operating Temperature (Note 1)

T

OP

−40

80

°C

1. Under conditions of no condensation on the sensor.

Table 20. CMOS IN/OUT CHARACTERISTICS

Parameter

Output Voltage Low Level

Symbol

Minimum

Typical

Maximum

Unit

V

OL

−

0.45

−

V

Output Voltage High Level

V

OH

VDD_DIG − 0.45

Input Hysteresis Voltage

V

R

−

62

100

−

0.25

−

TH

PU

PD

Pull-up Resistor Value for RESETN Pin

Pull-down Resistor Value for TRIGGER Pin

Current on ADC_REF Pin

−

kW

mA

−

I

100

−

ADC_REF

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29

KAC−12040

Table 21. SUPPLIES

Parameter

Symbol

VDD_LVDS

AVDD_HV

Vref_P

Minimum

3.15

3.40

2.71

1.71

1.90

−

Typical

3.30

3.50

2.80

1.80

2.00

0.5

Maximum

3.63

3.60

2.88

1.89

2.10

−

Unit

V

LVDS IO Supply

Pixel High Voltage Supply

Pixel Low Voltage Supply

Analog Power Supply

Digital Power Supply

AVDD_HV − Vref_P

V

AVDD_LV

VDD_DIG

V

Power in STANDBY State

−

10

−

mW

mA

Current in STANDBY State

VDD_LVDS

AVDD_HV

AVDD_LV

Vref_P

−

< 0.5

4

−

VDD_DIG

Power in CONFIG State

−

330

−

mW

mA

Current in CONFIG State

VDD_LVDS

AVDD_HV

AVDD_LV

Vref_P

−

< 0.5

145

−

VDD_DIG

Power in IDLE State

−

410

−

mW

mA

Current in IDLE State

VDD_LVDS

AVDD_HV

AVDD_LV

Vref_P

−

< 0.5

20

< 0.5

145

−

VDD_DIG

Power in RUNNING State

−

1.5

−

W

Current in RUNNING State

VDD_LVDS in Standard LVDS Mode

VDD_LVDS in Sub-LVDS Mode

AVDD_HV

AVDD_LV

Vref_P

mA

−

164

104

74

12

26

−

VDD_DIG

396

1. Voltages relative to VSS. Current measurements made in darkness.

2. PLL2 = 320 MHz, Max frame rate (i.e., no row or frame wait time). These average power values will decrease at lower frame rate either from

reduced PLL2 or low power state during Line and Frame blanking.

3. Sub-LVDS active.

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30

KAC−12040

SPI (SERIAL PERIPHERAL INTERFACE)

The SPI communication interface lets the application

system to control and configure the sensor. The sensor has

an embedded slave SPI interface. The application system is

the master of the SPI bus.

Table 22.

Sensor I/O

Direction

Name

Description

CSN

I

SPI Chip Select − Active low, this input activates the slave interface in the sensor.

SCK

SPI Clock − Toggled by the master.

MISO

MOSI

O

I

SPI Master Serial Data Input − Slave (sensor) serial data output.

SPI Master Serial Data Output − Slave (sensor) serial data input.

Table 23.

Parameter

Minimum

Typical

25

Maximum

Unit

MHz

%

SPI SCK

5

50

60

Duty Cycle on SPI SCK

40

50

Clock Polarity and Phase

CPOL (Clock POLarity) and CPHA (Clock PHAse) are

commonly defined in SPI protocol such as to define SCK

clock phase and polarity. The KAC−12040 defaults to

expecting the master to be configured with CPOL = 1

(the base value of the clock is VDD_DIG) and CPHA = 1

(data is valid on the clock rising edge).

CSN

SCK

…

MOSI

MISO

X

…

X

Figure 22. CPOL = 1 and CPHA = 1 Configuration

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31

KAC−12040

SPI Protocol

Byte 0

Byte 1

Byte 2

Byte 3

CSN

Sclk

8 Cycles 8 Cycles 8 Cycles 8 Cycles

16 Bit

Address Word

16 Bit

Data to Write

MOSI

MSB

LSB

MSB

LSB

Figure 23. SPI Write Byte Order

Byte 0

Byte 1

Byte 2

Byte 3

CSN

Sclk

8 Cycles 8 Cycles

8 Cycles

16 Bit

Address Word

MOSI

MISO

MSB

LSB

16 Bit

Data to Write

Wait Time

1.5 ms

MSB

LSB

Figure 24. SPI Read Byte Order

There is a delay during readback between presenting the

address to be read on the MOSI and being able to read the

register contents on the MISO. This delay is not the same for

all registers. Some are available immediately, some require

a longer fetch time. The 1.5 ms shown in Figure 15 is the

maximum time to fetch a register’s value when in CONFIG

state (the recommended state for changing registers). Some

registers can be adjusted during RUNNING state (see the

Register Summary on page 25). If performing a readback

during RUNNING state, the delay could be as long as 4.5 ms

depending on when in the row the request was sent and the

sensor’s microcontroller activity at that moment.

new register writes are placed in a shadow memory until

they can be updated into the active memory. This active

memory update occurs at the start of the next frame or upon

entering the state listed in the Register Summary table on

page 25. Register reads access this shadow memory not the

active memory. For instance if the sensor is in RUNNING

mode and you adjust the LL in register 200h. You can read

back and confirm that your register change was received by

the sensor; however, the LL will not change since register

200h can only be changed in CONFIG state. If you change

the sensor state to CONFIG and then back to RUNNING,

then the new LL will take effect.

Note that readback does not provide the actual register

value being used, but reflects the next value to be used. All

www.onsemi.com

32

KAC−12040

SPI Interface

…

CS

T

CS_HOLD

T

CYCLE

CS_SETUP

…

SCK

T

HOLD

SETUP

X

MSB

MOSI

T

OUT_DELAY

OUT_DELAY_CSN

MISO

MSB

MSB−1

Figure 25. SPI Timing Chronogram

Table 24. SPI TIMING SPECIFICATION

Symbol

Minimum Value

Maximum Value

Unit

ns

T

20

−

200

2.9

−

CYCLE

ns

SETUP

T

0.8

−

ns

HOLD

CS_SETUP

T

2.5

−

ns

T

0.1

3.1

4.9

ns

CS_HOLD

OUT_DELAY_CSN

T

4.7

8.7

ns

T

ns

OUT_DELAY

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33

KAC−12040

LVDS INTERFACE

The data output can be configured to follow standard

TIA/EIA−644−A LVDS specification or a low power mode

compatible with common Sub-LVDS definition used in

FPGA industry. (Please refer to the KAC−12040 User Guide

for more information).

Unless otherwise noted, min/max characteristics are for

T = −40°C to +85°C, output termination resistance

RL = 100 W 1%, Typical values are at VDD_LVDS =

3.3 V.

Use register 2449h to select standard or Sub-LVDS. This

document assumes that Sub-LVDS is active for all power

measurements. Standard LVDS can increase the average

power consumption as much as 200 mW in the case of

minimum horizontal and vertical blanking.

Table 25. STANDARD LVDS CHARACTERISTICS

Parameter

Symbol

VOD

Minimum

250

Typical

Maximum

Unit

mV

V

Differential Output Voltage

355

450

20

VOD Variation between Complementary Output States

Common Mode Output Voltage

DVOD

VOCM

DVOCM

IOZD

−20

−

1.259

−

1.235

−25

1.275

25

VOCM Variation between Complementary Output States

High Impedance Leakage Current

mV

mA

−1

−

1

Output Short Circuit Current:

When D+ or D− Connected to Ground

When D+ or D− Connected to 3.3 V

IOSD

mA

2.9

12.25

−

4.3

30.47

Output Capacitance

CDO

−

1.3

−

pF

Maximum Transmission Capacitance Load Expected

(for 260 MHz LVDS Clock)

10

Table 26. SUB-LVDS CHARACTERISTICS

Parameter

Symbol

Minimum

140

Typical

Maximum

Unit

mV

V

Differential Output Voltage

V

OD

180

−

220

5

VOD Variation between Complementary Output States

Common Mode Output Voltage

DV

−5

OD

V

OCM

0.88

−10

0.90

−

0.92

10

1

VOCM Variation between Complementary Output States

High Impedance Leakage Current

DV

mV

mA

OCM

I

−1

−

OZD

Output Short Circuit Current:

When D+ or D− Connected to Ground

When D+ or D− Connected to 3.3 V

I

mA

OSD

1.4

10.21

−

2.2

30.47

Output Capacitance

C

−

1.3

−

pF

DO

Maximum Transmission Capacitance Load Expected

(for 260 MHz LVDS Clock)

10

Table 27.

Parameter

Minimum

Typical

160

Maximum

Unit

MHz

%

LVDS_CLK

50

−

160

−

Duty Cycle on LVDS_CLK

50

www.onsemi.com

34

KAC−12040

In-Block LVDS Timing Specification

The tables below give LVDS timing specifications for no

data de-skew applied and with data de-skewing applied.

Ideal Sample Times = Center of Data

Data

A

C

A

Clock

B

Figure 26. LVDS Timing Chronogram

Table 28. IN-BLOCK LVDS TIMING SPECIFICATION (Data Transition Uncertainty − No De-Skew Applied)

Parameter

Value

360 ps

Description

A

B

C

Max Data Transition Uncertainty (Skew + Jitter)

1/4 LVDS Clock Period = 1/2 PLL2 Period

Minimum Receiver Setup/Hold Time Sample Window

LVDS Clock Period/4

C = B − A

KAC−12040 Example at Maximum PLL2 Speed

(320 MHz):

If the sampling window is too small the PLL2 can be

reduced to increase the window (parameter C).

Alternatively, the majority of the transition uncertainty is

potential skew between the 7 data lines. Using de-skewing

can remove 350 ps from the uncertainty window.

LVDS Clock Frequency = PLL2/2 = 160 MHz

LVDS Clock Period = 6250 ps

B = LVDS Clock Period/4 = 1563 ps

C = B – A = 1563 – 360 = 1203 ps

Table 29. IN-BLOCK LVDS TIMING SPECIFICATION (Data Transition Uncertainty − Data De-Skewing Applied)

Parameter

Value

10 ps

Description

A

B

C

Max Data Transition Uncertainty (Jitter)

1/4 LVDS Clock Period = 1/2 PLL2 Period

Minimum Receiver Setup/Hold Time Sample Window

LVDS Clock Period/4

C = B − A

KAC−12040 Example at Maximum PLL2 Speed

(320 MHz):

LVDS Clock Frequency = PLL2/2 = 160 MHz

LVDS Clock Period = 6250 ps

B = LVDS Clock Period/4 = 1563 ps

C = B – A = 1563 – 10 = 1553 ps

Table 30. INTER-BLOCK LVDS TIMING SPECIFICATION

Parameter

Minimum

Typical

Maximum

Unit

Inter-Block Skew

−

6

12

LVDS Clock Period

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35

KAC−12040

STORAGE AND HANDLING

Table 31. STORAGE CONDITIONS

Description

Storage Temperature

Humidity

Symbol

Minimum

Maximum

Unit

°C

Notes

T

ST

−40

5

80

90

1

2

RH

%

1. Long-term storage toward the maximum temperature will accelerate color filter degradation.

2. T = 25°C. Excessive humidity will degrade MTTF.

For information on ESD and cover glass care and

cleanliness, please download the Image Sensor Handling

and Best Practices Application Note (AN52561/D) from

www.onsemi.com.

For quality and reliability information, please download

the Quality & Reliability Handbook (HBD851/D) from

www.onsemi.com.

For information on device numbering and ordering codes,

please download the Device Nomenclature technical note

(TND310/D) from www.onsemi.com.

For information on soldering recommendations, please

download the Soldering and Mounting Techniques

Reference

www.onsemi.com.

Manual

(SOLDERRM/D)

from

For information on Standard terms and Conditions of

Sale, please download Terms and Conditions from

www.onsemi.com.

www.onsemi.com

36

KAC−12040

MECHANICAL INFORMATION

Completed Assembly

Notes:

1. See Ordering Information for marking code.

2. No materials to interfere with clearance through package holes.

3. Imaging Array is centered at the package center.

4. Length dimensions in mm units.

Figure 27. Completed Assembly (1 of 5)

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37

KAC−12040

Figure 28. Completed Assembly (2 of 5)

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38

KAC−12040

Figure 29. Completed Assembly (3 of 5)

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39

KAC−12040

Figure 30. Completed Assembly (4 of 5)

Figure 31. Completed Assembly (5 of 5)

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40

KAC−12040

MAR (Multi-Layer Anti-Reflective Coating) Cover Glass

Notes:

1. Units: IN [MM]

2. A-Zone Dust/Scratch Spec: 10 mm Maximum

3. Index of Refraction: 1.5231

Figure 32. MAR Cover Glass Specification

ON Semiconductor and the

are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.

SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed

at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation

or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and

specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets

and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each

customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,

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the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or

unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and

expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim

alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable

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For additional information, please contact your local

Sales Representative

KAC−12040/D

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41


型号：	KAC-12040-CBA-JD-BA
厂家：	ONSEMI
描述：	CMOS Image Sensor 时钟传感器换能器
文件：	总41页 (文件大小：820K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

KAC-12040-CBA-JD-BA [ONSEMI]

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