KAE-04472-ABA-SD-EE_技术文档

KAE-04472

2096 (H) x 2096 (V) Interline

Transfer EMCCD Image Sensor

The KAE−04472 Image Sensor is a 4.4 Mp, 4/3″ format, Interline

Transfer EMCCD image sensor that provides exceptional imaging

performance in extreme low light applications and enhanced near IR

sensitivity. Each of the sensor’s four outputs incorporates both a

conventional horizontal CCD register and a high gain EMCCD

register. This image sensor is drop−in compatible with the

KAE−04471 Image Sensor and provides enhanced NIR sensitivity.

An intra-scene switchable gain feature samples each charge packet

on a pixel-by-pixel basis. This enables the camera system to determine

whether the charge will be routed through the normal gain output or

the EMCCD output based on a user selectable threshold. This feature

enables imaging in extreme low light, even when bright objects are

within a dark scene, allowing a single camera to capture quality

images from sunlight to starlight. The device is available in a PGA

package with integrated thermoelectric cooler (TEC).

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Figure 1. KAE−04472 Interline

Transfer EMCCD Image Sensor

Table 1. GENERAL SPECIFICATIONS

Parameter

Typical Value

Interline CCD; with EMCCD

4.4 Megapixels

Architecture

Resolution

Features

• Intra-Scene Switchable Gain

• Wide Dynamic Range

Total Number of Pixels

Number of Effective Pixels

Number of Active Pixels

Pixel Size

2168 (H) × 2144 (V)

2120 (H) × 2120 (V)

2096 (H) × 2096 (V)

7.4Ămm (H) × 7.4Ămm (V)

15.51 mm (H) × 15.51 mm (V)

21.93 mm (Diagonal)

4/3″ Optical Format

1:1

• Charge Domain Binning

• Low Noise Architecture

• Exceptional Low Light Imaging

• Global Shutter

Active Image Size

• Excellent Image Uniformity and MTF

• Bayer Color Pattern and Monochrome

Aspect Ratio

Number of Outputs

Charge Capacity

1, 2, or 4

40,000 electrons

Applications

Output Sensitivity

Normal Gain, Intra-scene

−

• Scientific Imaging

• Medical Imaging

• Defense Imaging

• Surveillance

33, 45ĂmV/e

Quantum Efficiency

Mono (500, 850, 920 nm) / R,G,B

(50%, 16%, 8%) / 48%, 43%, 43%

Read Noise (20 MHz)

Normal Mode (1× Gain)

Intra-scene Mode (20× Gain)

Dark Current (−10°C)

Photodiode, VCCD

< 10 electrons rms

< 1 electron rms

• Intelligent Transportation Systems

< 0.1, 6 electrons/s

ORDERING INFORMATION

Dynamic Range

Normal Mode (1× Gain)

Intra-scene Mode (20× Gain)

See detailed ordering and shipping information on page 2 of

this data sheet.

72 dB

92 dB

Charge Transfer Efficiency

Blooming Suppression

Smear

0.999999

> 300 X

−110 dB

Image Lag

< 1 electron

Maximum Data Rate

40 MHz (HCCD, +20°C),

20 MHz (EMCCD)

Maximum Frame Rate

24 fps (40 MHz HCCD),

13.8 fps (20 MHz HCCD)

Power Consumption (Intra-scene,

15 fps)

1300 mW

NOTE: All Parameters are specified at T = −10°C unless otherwise noted.

1

Publication Order Number:

February, 2019 − Rev. 1

KAE−04472/D

KAE−04472

ORDERING INFORMATION

US export controls apply to all shipments of this product

designated for destinations outside of the US and Canada,

requiring ON Semiconductor to obtain an export license

from the US Department of Commerce before image sensors

or evaluation kits can be exported.

Table 2. ORDERING INFORMATION − KAE−04472 IMAGE SENSOR

Part Number

Description

Marking Code

KAE−04472−ABA−SD−FA

Monochrome, Microlens, PGA Package with Integrated TEC,

Sealed MAR Cover Glass (No Coatings), Standard Grade

KAE−04472−ABA

Serial Number

KAE−04472−ABA−SD−EE

KAE−04472−FBA−SD−FA

KAE−04472−FBA−SD−EE

Monochrome, Microlens, PGA Package with Integrated TEC,

Sealed MAR Cover Glass (No Coatings), Engineering Grade

Color (Bayer RGB), Microlens, PGA Package with Integrated TEC,

Sealed MAR Cover Glass (No Coatings), Standard Grade

KAE−04472−FBA

Serial Number

Color (Bayer RGB), Microlens, PGA Package with Integrated TEC,

Sealed MAR Cover Glass (No Coatings), Engineering Grade

See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention

used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at

www.onsemi.com.

Warning

The KAE−04472−ABA−SD and KAE−04472−FBA−SD

packages have an integrated thermoelectric cooler (TEC)

and have epoxy sealed cover glass. The seal formed is

non−hermetic, and may allow moisture ingress over time,

depending on the storage environment.

As a result, care must be taken to avoid cooling the device

below the dew point inside the package cavity, since this

may result in condensation on the sensor.

For all KAE−04472 configurations, no warranty,

expressed or implied, covers condensation.

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2

KAE−04472

DEVICE DESCRIPTION

Architecture

3

1079

450

24

1079

450

24

286

1

3

28

8

1060

8

28

1

3

12

2

1

2

24 12

2096 x 2096

12 24

2

12

3

1

28

8

24

450

1079

1060

286

1060

286

24

450

1079

8

28 1

3

Figure 2. Block Diagram

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3

KAE−04472

3

1079

450

24

1079

450

24

286

1

3

28

8

1060

8

28

1

3

12

2

1

2

24 12

2096 x 2096

12 24

2

1

2

12

3

1

3

1

28

8

24

450

1079

1060

286

1060

286

24

450

1079

8

28

3

Figure 3. Block Diagram Showing Bayer Pattern

Dark Reference Pixels

Image Acquisition

There are 12 dark reference rows at the top and bottom of

the image sensor, as well as 24 dark reference columns on the

left and right sides. However, the rows and columns at the

perimeter edges should not be included in acquiring a dark

reference signal, since they may be subject to some light

leakage.

An electronic representation of an image is formed when

incident photons falling on the sensor plane create

electron-hole pairs within the individual silicon

photodiodes. These photoelectrons are collected locally by

the formation of potential wells at each photo-site. Below

photodiode saturation, the number of photoelectrons

collected at each pixel is linearly dependent upon light level

and exposure time and non-linearly dependent on

wavelength. When the photodiodes charge capacity is

reached, excess electrons are discharged into the substrate to

prevent blooming.

Active Buffer Pixels

12 unshielded pixels adjacent to any leading or trailing

dark reference regions are classified as active buffer pixels.

These pixels are light sensitive but are not tested for defects

and non-uniformities.

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4

KAE−04472

Physical Description

Pin Grid Array Configuration

Output “D”

Output “C”

F

E

D

C

B

A

25 23 21 19

17 15 13 11

9

7

5

3

1

26 24 22 20 18 16 14 12 10

8

6

4

2

Output “B”

Output “A”

Figure 4. PGA Package Pin Designations (Bottom View)

Table 3. PIN DESCRIPTION

Pin Number

A2

Label

+9 V

Description

+9 V Supply

A3

VDD15ac

VDD1a

VOUT1a

VDD2a

VOUT2a

H2La

+15 V Supply

A4

Amplifier 1 Supply, Quadrant a

Video Output 1, Quadrant a

Amplifier 2 Supply, Quadrant a

Video Output 2, Quadrant a

A5

A6

A7

A8

HCCD Last Gate, Outputs 1, 2 and 3, Quadrant a

Amplifier 3 Supply, Quadrant a

Video Output 3, Quadrant a

HCCD Phase 1, Quadrant a

HCCD Phase 2, Quadrant a

Ground

A9

VDD3a

VOUT3a

H1a

A10

A11

A12

A13

A14

H2a

GND

H2b

HCCD Phase 2, Quadrant b

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5

KAE−04472

Table 3. PIN DESCRIPTION

Pin Number

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

B1

Label

H1b

Description

HCCD Phase 1, Quadrant b

Video Output 3, Quadrant b

Amplifier 3 Supply, Quadrant b

VOUT3b

VDD3b

H2Lb

HCCD Last Gate, Outputs 1, 2 and 3, Quadrant b

Video Output 2, Quadrant b

Amplifier 2 Supply, Quadrant b

Amplifier 1 Output, Quadrant b

Amplifier 1 Supply, Quadrant b

+15 V Supply, Quadrants b and d

+9 V Supply

VOUT2b

VDD2b

VOUT1b

VDD1b

VDD15bd

+9 V

GND

Ground

TEC−

GND

Thermoelectric Cooler Negative Bias

Ground

B2

ESD

B3

V4B

VCCD Bottom Phase 4

B4

GND

Ground

B5

VSS1a

RG1a

RG23a

GND

Amplifier 1 Return, Quadrant a

Amplifier 1 Reset, Quadrant a

Amplifier 2 and 3 Reset, Quadrant a

Ground

B6

B7

B8

B9

H2BEMa

H1BEMa

H1Sa

EMCCD Barrier Phase 2, Quadrant a

EMCCD Barrier Phase 1, Quadrant a

HCCD Storage Phase 1, Quadrant a

HCCD Storage Phase 2, Quadrant a

Ground

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

C1

H2Sa

GND

H2Sb

HCCD Storage Phase 2, Quadrant b

HCCD Storage Phase 1, Quadrant b

EMCCD Barrier Phase 1, Quadrant b

EMCCD Barrier Phase 2, Quadrant b

Ground

H1Sb

H1BEMb

H2BEMb

GND

RG23b

RG1b

VSS1b

GND

Amplifier 2 and 3 Reset, Quadrant b

Amplifier 1 Reset, Quadrant b

Amplifier 1 Return, Quadrant b

Ground

V4B

VCCD Bottom Phase 4

ESD

GND

Ground

TEC−

GND

Thermoelectric Cooler Negative Bias

Ground

C2

ID

Device ID

C3

V3B

VCCD Bottom Phase 3

C4

V2B

VCCD Bottom Phase 2

C5

V1B

VCCD Bottom Phase 1

C6

H2Xa

Floating Gate Exit HCCD Gate, Quadrant a

HCCD Output 2 Selector, Quadrant a

HCCD Output 3 Selector, Quadrant a

EMCCD Storage Multiplier Phase 2, Quadrant a

EMCCD Storage Multiplier Phase 1, Quadrant a

C7

H2SW2a

H2SW3a

H2SEMa

H1SEMa

C8

C9

C10

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KAE−04472

Table 3. PIN DESCRIPTION

Pin Number

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

C24

C25

C26

D1

Label

H1Ba

H2Ba

SUB

Description

HCCD Barrier Phase 1, Quadrant a

HCCD Barrier Phase 2, Quadrant a

Substrate

H2Bb

H1Bb

H1SEMb

H2SEMb

H2SW3b

H2SW2b

H2Xb

V1B

HCCD Barrier Phase 2, Quadrant b

HCCD Barrier Phase 1, Quadrant b

EMCCD Storage Multiplier Phase 1, Quadrant b

EMCCD Storage Multiplier Phase 2, Quadrant b

HCCD Output 3 Selector, Quadrant b

HCCD Output 2 Selector, Quadrant b

Floating Gate Exit HCCD Gate, Quadrant b

VCCD Bottom Phase 1

V2B

VCCD Bottom Phase 2

V3B

VCCD Bottom Phase 3

N/C

No connect

GND

Ground

TEC−

N/C

Thermoelectric Cooler Negative Bias

No connect

D2

N/C

No connect

D3

V3T

VCCD Top Phase 3

D4

V2T

VCCD Top Phase 2

D5

V1T

VCCD Top Phase 1

D6

H2Xc

Floating Gate Exit HCCD Gate, Quadrant c

HCCD Output 2 Selector, Quadrant c

HCCD Output 3 Selector, Quadrant c

EMCCD Storage Phase 2, Quadrant c

EMCCD Storage Phase 1, Quadrant c

HCCD Barrier Phase 1, Quadrant c

HCCD Barrier Phase 2, Quadrant c

Substrate

D7

H2SW2c

H2SW3c

H2SEMc

H1SEMc

H1Bc

D8

D9

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

E1

H2Bc

SUB

H2Bd

H1Bd

H1SEMd

H2SEMd

H2SW3d

H2SW2d

H2Xd

V1T

HCCD Barrier Phase 2, Quadrant d

HCCD Barrier Phase 1, Quadrant d

EMCCD Storage Multiplier Phase 1, Quadrant d

EMCCD Storage Multiplier Phase 2, Quadrant d

HCCD Output 3 Selector, Quadrant d

HCCD Output 2 Selector, Quadrant d

Floating Gate Exit HCCD Gate, Quadrant d

VCCD Top Phase 1

V2T

VCCD Top Phase 2

V3T

VCCD Top Phase 3

VSUBREF

GND

Substrate Voltage Reference

Ground

TEC+

N/C

Thermoelectric Cooler Positive Bias

No connect

E2

GND

Ground

E3

V4T

VCCD Top Phase 4

E4

GND

Ground

E5

VSS1c

RG1c

Amplifier 1 Return, Quadrant c

Amplifier 1 Reset, Quadrant c

E6

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7

KAE−04472

Table 3. PIN DESCRIPTION

Pin Number

E7

Label

RG23c

GND

Description

Amplifier 2 and 3 Reset, Quadrant c

Ground

E8

E9

H2BEMc

H1BEMc

H1Sc

EMCCD Barrier Phase 2, Quadrant c

EMCCD Barrier Phase 1, Quadrant c

HCCD Storage Phase 1, Quadrant c

HCCD Storage Phase 2, Quadrant c

Ground

E10

E11

E12

E13

E14

E15

E16

E17

E18

E19

E20

E21

E22

E23

E24

E25

E26

F1

H2Sc

GND

H2Sd

HCCD Storage Phase 2, Quadrant d

HCCD Storage Phase 1, Quadrant d

EMCCD Barrier Phase 1, Quadrant d

EMCCD Barrier Phase 2, Quadrant d

Ground

H1Sd

H1BEMd

H2BEMd

GND

RG23d

RG1d

VSS1d

GND

Amplifier 2 and 3 Reset, Quadrant d

Amplifier 1 Reset, Quadrant d

Amplifier 1 Return, Quadrant d

Ground

V4T

VCCD Top Phase 4

GND

Ground

GND

Ground

TEC+

N/C

Thermoelectric Cooler Positive Bias

No connect

F2

V2B

VCCD Bottom Phase 2

F3

ESD

F4

VDD1c

VOUT1c

VDD2c

VOUT2c

H2Lc

Amplifier 1 Supply, Quadrant c

Video Output 1, Quadrant c

Amplifier 2 Supply, Quadrant c

Video Output 2, Quadrant c

HCCD Last Gate, Outputs 1, 2 and 3, Quadrant c

Amplifier 3 Supply, Quadrant c

Video Output 3, Quadrant c

HCCD Phase 1, Quadrant c

HCCD Phase 2, Quadrant c

Ground

F5

F6

F7

F8

F9

VDD3c

VOUT3c

H1c

F10

F11

F12

F13

F14

F15

F16

F17

F18

F19

F20

F21

F22

F23

F24

F25

F26

H2c

GND

H2d

HCCD Phase 2, Quadrant d

HCCD Phase 1, Quadrant d

Video Output 3, Quadrant b

Amplifier 3 Supply, Quadrant d

HCCD Last Gate, Outputs 1, 2 and 3, Quadrant d

Video Output 2, Quadrant d

Amplifier 2 Supply, Quadrant d

Amplifier 1 Output, Quadrant d

Amplifier 1 Supply, Quadrant d

ESD

H1d

VOUT3d

VDD3d

H2Ld

VOUT2d

VDD2d

VOUT1d

VDD1d

ESD

V2B

VCCD Bottom Phase 2

GND

Ground

TEC+

Thermoelectric Cooler Positive Bias

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8

KAE−04472

Imaging Performance

Table 4. TYPICAL OPERATION CONDITIONS

(Unless otherwise noted, the Imaging Performance Specifications are measured using the following conditions.)

Description

Light Source (Note 1)

Operation

Condition

Continuous Red, Green, Blue and IR LED Illumination

Nominal Operating Voltages and Timing

1. For monochrome sensor, only green LED light source is used.

Table 5. PERFORMANCE PARAMETERS

Test

Temperature

(5C)

Sampling

Plan

Description

Symbol

Min.

Nom.

Max.

Unit

Maximum Photoresponse Nonlinearity

(EMCCD gain = 1) (Note 2)

NL

−

2

−

%

Design

Maximum Gain Difference Between

Outputs (EMCCD gain = 1) (Note 6)

DG

−

10

1

−

%

Maximum Signal Error due to Nonlin-

earity Differences

DNL

(EMCCD gain = 1) (Note 2)

−

Horizontal CCD Charge Capacity

Vertical CCD Charge Capacity

Photodiode Dark Current (Average)

Vertical CCD Dark Current

Image Lag

H

V

−

50

−

ke

Design

Ne

−

ke

Ne

I

−

0.1

0.4

−

3

e/p/s

e−

−10

PD

−

Lag

−

10

−

Antiblooming Factor

X

AB

300

−

1000

−110

9

Vertical Smear (Blue Light)

Smr

−

dB

Read Noise (EMCCD Gain = 1)

(Note 3)

n

e−T

−

e−rms

Read Noise (EMCCD Gain = 20)

−

< 1

1.4

−

e−rms

dB

EMCCD Excess Noise Factor

(Gain = 20x)

Design

0

Dynamic Range (Gain = 1)

(Notes 3, 4)

DR

−

72

−

Dynamic Range (High Gain)

−

60

92

−

dB

Dynamic Range (Intra-scene)

Output Amplifier Bandwidth (Note 5)

f

250

45

MHz

mV/e−

Design

−3db

Output Amplifier Sensitivity

(EMCCD Output)

DV/DN

Output Amplifier Sensitivity

(Floating Gate Amplifier)

DV/DN

(FG)

−

7.8

−

mV/e−

Design

Quantum Efficiency (Monochrome,

Peak)

QE

%

max

Green (500 nm)

NIR (850 nm)

NIR (920 nm)

−

50%

16%

8%

−

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9

KAE−04472

Table 5. PERFORMANCE PARAMETERS (continued)

Test

Temperature

(5C)

Sampling

Plan

Description

Symbol

QE

Min.

Nom.

Max.

Unit

Quantum Efficiency (Color, Peak)

Red (620 nm)

Green (540 nm)

%

Design

max

−

48%

43%

−

Blue (470 nm)

Power

W

Design

4-output Mode

(20MHz)

(40MHz)

−

0.7

0.8

−

2-output Mode

(20MHz)

(40MHz)

−

0.5

−

1-output Mode

(20MHz)

(40MHz)

−

0.4

−

2. Value is over the range of 10% to 90% of photodiode saturation.

3. At 20 MHz.

4. Uses 20 LOG (P /n

)

Ne e−T

5. Calculated from f

= 1 / 2p * R

* C

where C

= 5 pF.

−3db

OUT

LOAD

6. The output-to-output gain differences may be adjusted by independently adjusting the EMCCD amplitude for each output.

Table 6. PERFORMANCE SPECIFICATIONS

Test

Temperature

(5C)

Sampling

Plan

Description

Symbol

Min.

−

Nom.

−

Max.

2.0

Unit

mVpp

%rms

Dark Field Global Non-Uniformity

DSNU

Die

−10

Bright Field Global Non-Uniformity

(Note 7)

−

2.0

5.0

−10

Bright Field Global Peak to Peak

Non-Uniformity (Note 7)

PRNU

−

5.0

1.0

15.0

2.0

%pp

Die

−10

Bright Field Center Non-Uniformity

(Note 7)

%rms

−

Photodiode Charge Capacity (Note 8)

P

−

40

−

ke

Die

−10

Ne

Horizontal CCD Charge Transfer

Efficiency

HCTE

0.999995

0.999999

Vertical CCD Charge Transfer

Efficiency

VCTE

0.999995

8.0

0.999999

10

−

Die

−10

Output Amplifier DC Offset

(VOUT2, VOUT3)

V

12.0

V

ODC

Output Amplifier DC Offset (VOUT1)

Output Amplifier Impedance

7. Per color

−0.5

−

1.0

2.5

−

V

Die

−10

ODC

R

140

W

OUT

8. The operating value of the substrate reference voltage, to reach the desired charge capacity, V , can be read from V

.

AB

SUBREF

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10

KAE−04472

TYPICAL PERFORMANCE CURVES

Quantum Efficiency

Monochrome and Color with Microlens

0.6

0.55

0.5

0.45

0.4

0.35

0.3

0.25

0.2

0.15

0.1

0.05

0

Wavelength (nm)

Figure 5. Monochrome Quantum Efficiency

120

100

80

Green

Blue

Red

IR

60

40

20

0

−30

−20

−10

0

10

20

30

Horizontal Angle

Figure 6. Angled Response for Monochrome Device

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11

KAE−04472

0.6

0.55

0.5

0.45

0.4

0.35

0.3

Red

Green

Blue

0.25

0.2

0.15

0.1

0.05

0

Wavelength (nm)

Figure 7. Color Device Quantum Efficiency

120

100

80

Red

Green

Blue

60

40

20

0

−30

−20

−10

0

10

20

30

Angle (degrees)

Figure 8. Horizontal Angled Response for Color Device

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12

KAE−04472

Figure 9. Frame Rates vs. Clock Frequency

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13

KAE−04472

DEFECT DEFINITIONS

Table 7. DEFECT DEFINITIONS

Description

Definition

Maximum Number Allowed

Major Dark Field Defective Bright Pixel

Defect ≥ 30 mV deviation from the mean, for all pixels

40

in the active image area.

Major Bright Field Defective Dark Pixel

Minor Dark Field Defective Bright Pixel

≥ 12%

Defect ≥ 15 mV deviation from the mean, for all pixels

400

8

in the active image area.

Cluster Defect

Column Defect

A group of 2 to 10 contiguous major defective pixels,

with no more than 2 adjacent defects horizontally.

A group of more than 10 contiguous major dark

defective pixels along a single column or 10 contiguous

bright defective pixels along a single column.

0

9. Low exposure dark column defects are not counted at temperatures above −10°C

10.For the color device, a bright field defective pixel deviates by 12% with respect to pixels of the same color.

11. Column and cluster defects are separated by no less than 2 good pixels in any direction (excluding single pixel defects).

Absolute Maximum Ratings

Absolute maximum rating is defined as a level or

condition that should not be exceeded at any time per the

description. If the level or the condition is exceeded, the

device will be degraded and may be damaged. Operation at

these values will reduce MTTF.

Table 8. ABSOLUTE MAXIMUM RATINGS

Description

Symbol

Minimum

Maximum

Unit

°C

Operating Temperature Range (Note 12)

T

OP

−50

−10

−

+60

0

Parameter Specification Temperature Range (Note 13)

Output Bias Current, Total for Each Output (Note 14)

12.Device degradation is not evaluated outside of this temperature range.

T

%

PSR

OUT

I

−8

mA

13.The device will operate effectively within the specified temperature range, but the performance may not meet those given in the tables

“PERFORMANCE PARAMETERS” and “PERFORMANCE SPECIFICATIONS”. In particular, noise performance may be higher at

temperatures above the range given here, and charge transfer efficiency may be lower for temperatures below the range given here.

14.Shorting the output pins to ground or any low impedance source should be avoided during operation This action will result in irreparable

damage to the device, and is not covered by the device warranty.

Table 9. ABSOLUTE MAXIMUM VOLTAGE RATINGS BETWEEN PINS AND GROUND

Description

Minimum

−0.4

Maximum

17.5

Unit

V

VDD2(a,b,c,d), VDD3(a,b,c,d)

VDD1(a,b,c,d), VOUT1(a,b,c,d)

V1B, V1T

−0.4

7.0

V

ESD – 0.4

–0.4

ESD + 22.0

ESD + 14.0

+10

V

V2B, V2T, V3B, V3T, V4B, V4T

V

H1(a,b,c,d), H2(a,b,c,d)

H1S(a,b,c,d), H2S(a,b,c,d)

H1B(a,b,c,d), H2B(a,b,c,d)

H1BEM(a,b,c,d), H2BEM(a,b,c,d)

H2SW2(a,b,c,d), H2SW3(a,b,c,d)

H2L(a,b,c,d)

V

H2X(a,b,c,d)

RG1(a,b,c,d), RG23(a,b,c,d)

H1SEM(a,b,c,d), H2SEM(a,b,c,d)

ESD

−0.4

−9.0

6.5

+20

0.0

40

V

SUB (Notes 15 and 16)

15.Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions.

16.The measured value for VSUBREF is a diode drop higher than the recommended minimum VSUB bias.

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14

KAE−04472

GUIDELINES FOR OPERATION

Power Up and Power Down Sequence

GND at all times. The SUBREF pin will not become valid

until VDD15ac and VDD15bd have been powered.

The SUB pin should be at least 4 V before powering up

VDD2(a,b,c,d) and VDD3(a,b,c,d).

SUB and ESD power up first, then power up all other

biases in any order. No pin may have a voltage less than ESD

at any time. All HCCD pins must be greater than or equal to

V+

VDD

SUB

VDD1 and HCCD high

time

VCCD Low

ESD

V−

Figure 10. Power Up and Power Down Sequence

Table 10. DC BIAS OPERATING CONDITIONS

Maximum

DC Current

Description

Pins

Symbol

Min.

Nom.

Max.

Unit

Output Amplifier Return

Output Amplifier Supply

VSS1(a,b,c,d)

VDD1(a,b,c,d)

VSS1

VDD1

VDD

−8.3

4.5

−8.0

5.0

−7.7

6.0

V

4 mA

15 mA

VDD2(a,b,c,d),

VDD3(a,b,c,d)

+14.7

+15.0

+15.3

18.0 mA

Supply Voltage

(Note 17)

VDD15ac,

VDD15bd

VDD15

+14.7

+15.0

+15.3

V

9 mA

Ground

GND

SUB

GND

0.0

6.0

0.0

V

17.0 mA

Substrate

(Notes 18 and 19)

VSUB

VSUBREF

− 0.5

VSUBREF

+ 28

Up to 1 mA

(Determined by

Photocurrent)

ESD Protection Disable

Output Bias Current

ESD

−8.3

2.0

−8.0

2.5

−7.7

5.0

V

2 mA

VOUT1(a,b,c,d),

VOUT2(a,b,c,d),

VOUT3(a,b,c,d)

I

mA

OUT

17.VDD15ac and VDDD15bd bias pins must be maintained at 15 V during operation.

18.For each image sensor, the voltage output on the VSUBREF pin is programmed to be one diode drop, 0.5 V, above the nominal VSUB voltage.

So, the applied VSUB should be one diode drop (0.5 V) lower than the VSUBREF value measured on the device, when VDD2(a,b,c,d) and

VDD3(a,b,c,d) are at the specified voltage. This value corresponds to the VAB printed on the label for each sensor and applies to operation

at 0_C. (For other temperatures, there is a temperature dependence of approximately 0.01 V/degree.) It is noted that VSUBREF is unique

to each image sensor and may vary from 6.5 to 10.0 V. In addition, the output impedance of VSUBREF is approximately 100 k.

19.Caution: The EMCCD register must NOT be clocked while the electronic shutter pulse is high.

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15

KAE−04472

AC Operating Conditions

Clock Levels

Table 11. CLOCK LEVELS

HCCD and RG

Low Level

Nominal

Amplitude

Nominal

Low

High

Low

High

Function

H2B(a,b,c,d)

H1B(a,b,c,d)

H2S(a,b,c,d)

H1S(a,b,c,d)

Reversible HCCD Barrier 2

Reversible HCCD Barrier 1

Reversible HCCD Storage 2

Reversible HCCD Storage 1

HCCD Switch 2 and 3

−0.2

0.0

+0.2

3.1

3.3

3.6

H2SW2(a,b,c,d),

H2SW3(a,b,c,d)

H2L(a,b,c,d)

HCCD Last Gate

−0.2

0.0

Cap

0.0

+0.2

3.1

6.2

3.1

4.6

8.0

3.3

6.6

3.3

5.0

−

3.6

7.0

H2X(a,b,c,d)

Floating Gate Exit

Floating Gate Reset

Floating Diffusion Reset

Multiplier Barrier 1

Multiplier Barrier 2

Multiplier Storage 1

Multiplier Storage 2

RG1(a,b,c,d)

3.6

RG23(a,b,c,d)

H1BEM(a,b,c,d)

H2BEM(a,b,c,d)

H1SEM(a,b,c,d)

H2SEM(a,b,c,d)

3.6

−0.2

−0.3

+0.2

+0.3

5.4

18.0

−

20.HCCD Operating Voltages. There can be no overshoot on any horizontal clock below −0.4 V: the specified absolute minimum. The H1SEM

and H2SEM clock amplitudes need to be software programmable independently for each quadrant to adjust the charge multiplier gain.

21.Reset Clock Operation: The RG1, RG23 signals must be capacitive coupled into the image sensor with a 0.01 mF to 0.1 mF capacitor.

The reset clock overshoot can be no greater than 0.3 V, as shown in Figure 11, below.

3.1 V Minimum

0.3 V Maximum

Figure 11. RG Clock Overshoot

Clock Capacitances

H1SEMa

H2SEMa

H1BEMa

H2BEMa

H1a

pF

45

65

75

H1SEMb

H2SEMb

H1BEMb

H2BEMb

H1b

pF

45

65

75

H1SEMc

H2SEMc

H1BEMc

H2BEMc

H1c

pF

45

65

75

H1SEMd

H2SEMd

H1BEMd

H2BEMd

H1d

pF

45

65

75

H2a

H1Sa

H2b

H1Sb

H2c

H1Sc

H2d

H1Sd

H2Sa

H1Ba

H2Ba

H2Sb

H1Bb

H2Bb

H2Sc

H1Bc

H2Bc

H2Sd

H1Bd

H2Bd

NOTE: The capacitances of all other HCCD pins is 15 pF or less.

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16

KAE−04472

H1SEMa

H2SEMa

high

low

+18 V

H1SEMb

H2SEMb

high

low

4 Output

DAC

A

B

C

D

H1SEMc

H2SEMc

high

low

H1SEMd

H2SEMd

high

low

Figure 12. EMCCD Clock Adjustable Levels

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17

KAE−04472

For the EMCCD clocks, each quadrant must have

independently adjustable high levels. All quadrants have

a common low level of GND. The high level adjustments

must be software controlled to balance the gain of the four

outputs.

+3.3 V

0 to 75 W

RG1 Clock

Generator

RG1

0.01 to 0.1 mF

+3.3 V

RG2,3 Clock

Generator

RG23

0.01 to 0.1 mF

Figure 13. Reset Clock Drivers

The reset clock drivers must be coupled by capacitors to

the image sensor. The capacitors can be anywhere in the

range 0.01 to 0.1 mF. The damping resistor values would

vary between 0 and 75 W depending on the layout of the

circuit board.

Table 12. VCCD

Function

Low

−8.0

−0.2

8.5

Nominal

−8.0

High

−6.0

+0.2

12.5

V1T, V1B, V2T, V2B, V3T, V3B, V4T, V4B

V1T, V1B

Vertical CCD Clock, Low Level

Vertical CCD Clock, Mid Level

0.0

rd

Vertical CCD Clock, High (3 ) Level

9.0

22.The Vertical CCD operating voltages. The VCCD low level will be −8.0 V for operating temperatures of −10°C and above. Below −10°C the

VCCD low level should be increased for optimum noise performance.

Table 13. ELECTRONIC SHUTTER PULSE

Function

Low

High

SUB

Electronic Shutter

VSUBREF − 0.5

VSUBREF + 28

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18

KAE−04472

Device Identification

The device identification pin (DevID) may be used to

determine which ON Semiconductor 5.5 micron pixel

interline CCD sensor is being used.

Table 14. DEVICE IDENTIFICATION VALUES

Maximum

DC Current

Description

Pins

Symbol

Min.

Nom.

Max.

Unit

Device Identification (Notes 23, 24 and 25)

ID

63,000

70,000

84,000

W

0.3 mA

23.Nominal value subject to verification and/or change during release of preliminary specifications.

24.If the Device Identification is not used, it may be left disconnected.

25.After Device Identification resistance has been read during camera initialization, it is recommended that the circuit be disabled to prevent

localized heating of the sensor due to current flow through the R_DeviceID resistor.

Recommended Circuit

V1

V2

R_External

DevID

ADC

R_DeviceID

GND

KAE−04472

Figure 14. Device Identification Recommended Circuit

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19

KAE−04472

THEORY OF OPERATION

Image Acquisition

Photo

diode

Figure 15. An Illustration of Two Columns and Three Rows of Pixels

This image sensor is capable of detecting up to 40,000

The VCCD is shielded from light by metal to prevent

detection of more photons. For very bright spots of light,

some photons may leak through or around the metal light

shield and result in electrons being transferred into the

VCCD. This is called image smear.

electrons with a small signal noise floor of 1 electron all

within one image. Each 7.4 mm square pixel, as shown in

Figure 15 above, consists of a light sensitive photodiode and

a portion of the vertical CCD (VCCD). Not shown is

a microlens positioned above each photodiode to focus light

away from the VCCD and into the photodiode. Each photon

incident upon a pixel will generate an electron in the

photodiode with a probability equal to the quantum

efficiency.

The photodiode may be cleared of electrons (electronic

shutter) by pulsing the SUB pin of the image sensor up to

a voltage of 30 V to 40 V (VSUBREF + 22 to VSUBREF

+ 28 V) for a time of at least 2.5 ms. When the SUB pin is

above 30 V, the photodiode can hold no electrons, and the

electrons flow downward into the substrate. When the

voltage on SUB drops below 30 V, the integration of

electrons in the photodiode begins. The HCCD clocks

should be stopped when the electronic shutter is pulsed, to

avoid having the large voltage pulse on SUB coupling into

the video outputs and altering the EMCCD gain.

Image Readout

At the start of image readout, the voltage on the V1T and

V1B pins is pulsed from 0 V up to the high level for at least

1 ms and back to 0 V, which transfers the electrons from the

photodiodes into the VCCD. If the VCCD is not empty, then

the electrons will be added to what is already in the VCCD.

The VCCD is read out one row at a time. During a VCCD

row transfer, the HCCD clocks are stopped. All gates of type

H1 stop at the high level and all gates of type H2 stop at the

low level. After a VCCD row transfer, charge packets of

electrons are advanced one pixel at a time towards the output

amplifiers by each complimentary clock cycle of the H1 and

H2 gates.

The charge multiplier has a maximum charge handling

capacity (after gain) of 20,000 electrons. This is not the

average signal level. It is the maximum signal level.

Therefore, it is advisable to keep the average signal level at

15,000 electrons or less to accommodate a normal

distribution of signal levels. For a charge multiplier gain of

20x, no more than 15,000/20 = 750 electrons should be

allowed to enter the charge multiplier. Overfilling the charge

multiplier beyond 20,000 electrons will shorten its useful

operating lifetime.

It should be noted that there are certain conditions under

which the device will have no anti-blooming protection:

when the V1T and V1B pins are high, very intense

illumination generating electrons in the photodiode will

flood directly into the VCCD.

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20

KAE−04472

To prevent overfilling the charge multiplier,

a non-destructive floating gate output amplifier (VOUT1) is

provided on each quadrant of the image sensor as shown in

Figure 16 below.

To VOUT2

VOUT1

3 Clock Cycles

1 Clock Cycle

8 Clock Cycles

Empty Pixels

1 Clock

Cycle

28 Clock Cycles

Empty Pixels

24 Clock Cycles

From the Dark

VCCD Columns

From the Photo-active

VCCD Columns

SW

FG

Charge Transfer

2316 Clock Cycles

To the Charge

Multiplier and

VOUT3

Figure 16. The Charge Transfer Path of One Quadrant

The non-destructive floating gate output amplifier is able

to sense how much charge is present in a charge packet

without altering the number of electrons in that charge

packet. This type of amplifier has a low charge-to-voltage

The transfer sequence of a charge packet through the

floating gate amplifier is shown in Figure 17 below.

The time steps of this sequence are labeled A through D, and

are indicated in the timing diagram shown as Figure 18.

The RG1 gate is pulsed high during the time that the H2X

gate is pulsed high. This holds the floating gate at a constant

voltage so the H2X gate can pull the charge packet out of the

floating gate. The RG1 pulse should be at least as wide as the

H2X pulse, and the H2X pulse width should be at least 12 ns.

The rising edge of H2X relative to the falling edge of H1S

is critical, specifically, the H2X pulse cannot begin its rising

edge transition until the H1S edge is less than 0.4 V. If the

H2X rising edge comes too soon then there may be some

backward flow of charge for signals above 10,000 electrons.

−

conversion gain (about 7.8 mV/e ) and high noise (about

42 electrons), but it is being used only as a threshold

detector, and not an imaging detector. Even with

42 electrons of noise, it is adequate to determine whether

a charge packet is greater than or less than the recommended

threshold of 120 electrons.

After one row has been transferred from the VCCD into

the HCCD, the HCCD clock cycles should begin. After 8

clock cycles, the first dark VCCD column pixel will arrive

at VOUT1. After another 24 (34 total) clock cycles, the first

photo-active charge packet will arrive at VOUT1.

VDD1

Floating Gate Amp

VRef

VOUT1

RG1

H2

H1

H2X

OG1

H2L

H1S

A

B

C

D

Channel

Potential

NOTE: The differently shaded rectangles represent two separate charge packets. The direction of charge transfer is from right to left.

Gates after H2X are connected to H1 or H2. Gates before H2X are connected to H1S or H2S.

Figure 17. Charge Package Transfer Sequence through the Floating Gate Amplifier

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21

KAE−04472

A

B

C

D

H1S, H1

H2S, H2L, H2

H2X

RG1

VOUT1

Signal

Figure 18. Timing Signals that Control the Transfer of Charge through the Floating Gate Amplifier

The charge packet is transferred under the floating gate on

the falling edge of H2L. When this transfer takes place the

floating gate is not connected to any voltage source.

The presence of charge under the gate causes a change in

voltage on the floating gate according to V = Q/C, where Q

is the size of the charge packet and C is the capacitance of

and dynamically alter the timing on H2SW2 and H2SW3. To

route a charge packet to the charge multiplier (VOUT3),

H2SW2 is held at GND and H2SW3 is clocked with the

same timing as H2 for that one clock cycle. To route a charge

packet to the low gain output amplifier (VOUT2), H2SW3

is held at GND and H2SW2 is clocked with the same timing

as H2S for that one clock cycle.

−

the floating gate. With an output sensitivity of 7.8 mV/e ,

When operating the device at maximum (40 MHz) data

rate, all the charge must be routed through the low gain

amplifier (VOUT2). This is best accomplished with the

floating gate reset (RG1) held at its high level while clocking

the HCCD, and the H2X gate clocked with the same timing

as H2S and H2B. During the line timing patterns L1 or L2,

the RG1 gate should be clocked low. There is a diode on the

sensor that sets the DC offset of the RG1 gate when it is

clocked low. If the RG1 is not clocked low once per line then

the RG1 DC offset will drift. This timing scheme is

represented in the diagram shown below:

each electron on the floating gate would give a 7.8 mV

change in VOUT1 voltage. Therefore if the decision

threshold is to only allow charge packets of 126 electrons or

less into the charge multiplier, this would correspond to

120 × 7.8 = 936 mV. If the video output is less than 936 mV,

then the camera must set the timing of the H2SW2 and

H2SW3 pins to route the charge packet to the charge

multiplier. This action must take place 28 clock cycles after

the charge packet was under the floating gate amplifier.

The 28 clock cycle delay is to allow for pipeline delays of the

A/D converter inside the analog front end. The timing

generator must examine the output of the analog front end

40 MHz Floating Gate Bypass Timing

3.3 V

H1

0.0 V

3.3 V

0.0 V

3.3 V

0.0 V

H2S

H2SW2

H2S

H2SW2

6.0 V

H2X

0.0 V

3.3 V

RG1

0.0 V

Figure 19. 40 MHz Floating Gate Bypass Timing

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22

KAE−04472

EMCCD OPERATION

H1BEM H2SEM

H2BEM H1SEM H1BEM H2SEM H2BEM H1SEM

A

B

C

D

NOTE: Charge flows from right to left.

Figure 20. The Charge Multiplication Process

The charge multiplication process, shown in Figure 20

above, begins at time step A, when an electron is held under

the H1SEM gate. The H2BEM and H1BEM gates block the

electron from transferring to the next phase until the H2SEM

has reached its maximum voltage. When the H2BEM is

clocked from 0 to +5 V, the channel potential under H2BEM

increases until the electron can transfer from H1SEM to

H2SEM. When the H2SEM gate is above 10 V, the electric

field between the H2BEM and H2SEM gates gives the

electron enough energy to free a second electron which is

collected under H2SEM. Then the voltages on H2BEM and

H2SEM are both returned to 0 V at the same time that

H1SEM is ramped up to its maximum voltage. Now the

process can repeat again with charge transferring into the

H1SEM gate.

The alignment of clock edges is shown in Figure 21.

The rising edge of the H1BEM and H2BEM gates must be

delayed until the H1SEM or H2SEM gates have reached

their maximum voltage. The falling edge of H1BEM and

H2BEM must reach 0 V before the H1SEM or H2SEM

reach 0 V. There are a total of 1,800 charge multiplying

transfers through the EMCCD on each quadrant.

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23

KAE−04472

A

B

C

D

H2

100%

H2SEM

H2BEM

0%

100%

H1SEM

H1BEM

0%

Figure 21. The Timing Diagram for Charge Multiplication

The amount of gain through the EMCCD will depend on

temperature and H1SEM and H2SEM voltage as shown in

Figure 22. Gain also depends on substrate voltage, as shown

in Figure 23, and on the input signal, as shown in Figure 24.

1000

100

10

1

12.0

12.5

13.0

13.5

14.0

14.5

15.0

15.5

16.0

EMCCD Clock Amplitude (V)

NOTE: This figure represents data from only one example image sensor, other image sensors will vary.

Figure 22. The Variation of Gain vs. EMCCD High Voltage and Temperature

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24

KAE−04472

14.8

14.7

14.6

14.5

14.4

14.3

14.2

14.1

14.0

13.9

6

7

8

9

10

11

12

V

SUB

NOTE: EMCCD gain is not constant with substrate voltage.

Figure 23. The Requirement EMCCD Voltage for Gain of 20x vs. Substrate Voltage

22

21

20

19

18

17

0

50

100

150

200

250

300

−

Signal (e )

NOTE: The EMCCD voltage was set to provide 20x gain with an input of 180 electrons.

Figure 24. EMCCD Gain vs. Input Signal

If more than one output is used, then the EMCCD high

unpredictably from one image sensor to the next, as in

Figure 25. Because of this, the gain vs. voltage relationship

must be calibrated for each image sensor, although within

each quadrant, the H1SEM and H2SEM high level voltage

should be equal.

level voltage must be independently adjusted for each

quadrant. This is because each quadrant will require

a slightly different voltage to obtain the same gain. In

addition, the voltage required for a given gain differs

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25

KAE−04472

1000

100

10

1

12.0

12.5

13.0

13.5

14.0

14.5

15.0

15.5

16.0

EMCCD Clock Amplitude (V)

Figure 25. An Example Showing How Two Image Sensors Can Have Different Gain vs. Voltage Curves

The effective output noise of the image sensor is defined

as the noise of the output signal divided by the gain. This is

measured with zero input signal to the EMCCD. Figure 26

shows the EMCCD by itself has a very low noise that goes

as the noise at gain = 1 divided by the gain. The EMCCD has

very little clock-induced charge and does not require

elaborate sinusoidal waveform clock drivers. Simple square

wave clock drivers with a resistor between the driver and

sensor for a small RC time constant are all that is needed.

However, the pixel array may acquire spurious charge as

a function of VCCD clock driver characteristics.

10

1

0.1

1

10

100

1000

EMCCD Gain

NOTE: The data represented by this chart includes noise from dark current and spurious charge generation.

Figure 26. EMCCD Output Noise vs. EMCCD Gain in Single Output Mode from −305C to +105C

Because of these pixel array noise sources, it is

recommended that the maximum gain used be 100x, which

typically gives a noise floor between 0.4e and 0.6e at −10°C.

Using higher gains will provide limited benefit and will

degrade the signal to noise ratio due to the EMCCD excess

noise factor and spurious charge in the VCCD. Furthermore,

the image sensor is not limited by dark current noise sources

when the temperature is below −10°C. Therefore, cooling

below −10°C will not provide a significant improvement to

the noise floor, with the negative consequence that lower

temperatures increase the probability of poor charge

transfer.

CAUTION: The EMCCD should not be operated near

saturation for an extended period, as this

may result in gain aging and permanently

reduce the gain. It should be noted that

device degradation associated with gain

aging is not covered under the device

warranty.

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26

KAE−04472

Operating Temperature

Charge Switch Threshold

The reasons for lowering the operating temperature are to

reduce dark current noise and to reduce image defects.

The average dark signal from the VCCD and photodiodes

The floating gate output amplifier (VOUT1) is used to

select the routing of a pixel charge packet at the charge

switch. Pixels with large signals should be routed to the

normal floating diffusion amplifier at VOUT2. Pixels with

small signals should be routed to the EMCCD and VOUT3.

The routing of pixels is controlled by the timing on H2SW2

and H2SW3. The optimum signal threshold for that

transition between VOUT2 and VOUT3 is approximately

−

must be less than 1e in order to have a total system noise less

−

than 1e when using the EMCCD. The recommended

operating temperature is −10°C. This represents the best

compromise of low noise performance vs. complexity of

cooling the image sensor. Operation below −30°C is not

recommended, and temperatures below −30°C may result in

poor charge transfer in the HCCD. Operation above 0°C

may result in excessive dark current noise.

−

3 times the floating gate amplifier noise, or 126 e . Sending

−

signals larger than 126 e into the EMCCD will produce

images with lower signal to noise ratio than if they were read

out of the normal floating diffusion output of VOUT2.

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27

KAE−04472

TIMING DIAGRAMS

Pixel Timing

50 ns

H2S, H2L, H2

H1S, H1

H2X

RG1

RG23

H2SEM

H2BEM

H1SEM

H1BEM

NOTE: The minimum time for one pixel is 50 ns.

Figure 27. Pixel Timing Pattern P1

Black, Clamp, VOUT1, VOUT2, and VOUT3

Alignment at Line Start

The black level clamping operation of the analog front end

(AFE) should take place within the first 28 clock cycles of

every row. This applies to all modes of operation.

Charge Binning

The KAE−04471 sensor has an option to bin charge 2x2

or 4x4 at a horizontal clock rate of 20 MHz to give binned

pixel output rate of 10 MHz or 5 MHz.

VCCD Timing

Vertical Transfer Times and Pulse Widths

Table 15. TIMING DEFINITIONS

Symbol

Definition

VCCD Transfer Time A

Min

1.2

2.0

3.0

Nominal

1.2

Max

2.0

Unit

ms

T

VA

T

VB

VCCD Transfer Time B

1.2

4.0

ms

T

SUB

Electronic Shutter Pulse

2.5

10.0

5.0

ms

T

3

Photodiode to VCCD Transfer Time

3.0

ms

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28

KAE−04472

Clock Edge Alignments for V1, V2, V3, V4

V1B, V1T

V2B, V4T

V3B, V3T

V4B, V2T

T

VB

T

VB

T

VB

T

VB

T

VB

T

VA

T

VA

T

3

T

VA

T

VA

Figure 28. Timing Pattern F1. VCCD Frame Timing to Transfer Charge from Photodiodes to the VCCD

when Using the Bottom HCCD Outputs A or B

V1B

V2B, V3T

V3B, V4T

V4B

V1T

V2T

T

VB

T

VB

T

VB

T

VB

T

VB

T

VA

T

VA

T

3

T

VA

T

VA

Figure 29. Timing Pattern F2. VCCD Frame Timing to Transfer Charge from Photodiodes to the VCCD

when Using All Four Outputs in Quad Output Mode

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29

KAE−04472

V1B, V1T

V2B, V4T

V3B, V3T

V4B, V2T

T

VB

T

VB

T

VB

T

VB

T

VA

T

VA

T

VA

T

VA

Figure 30. Line Timing L1. VCCD Line Timing to Transfer One Line of Charge from VCCD to the HCCD

when Using the Bottom HCCD Outputs A or B in Single or Dual Output Modes

V1B, V2T

V2B, V3T

V3B, V4T

V4B, V1T

T

VB

T

VB

T

VB

T

VB

T

VA

T

VA

T

VA

T

VA

Figure 31. Line Timing L2. VCCD Line Timing to Transfer One Line of Charge from the VCCD to the HCCD

when Using All Four Outputs in Quad Output Mode

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30

KAE−04472

Electronic Shutter

V

AB

+ V

ES

V

SUB

V

AB

3.3 V

0 V

HCCD

VCCD

0 V

−8 V

T

VB

T

SUB

T

VB

Last HCCD

Clock Edge

First VCCD

Clock Edge

Figure 32. Electronic Shutter Timing Pattern S1

CAUTION: The EMCCD register must not be clocked

while the electronic shutter pulse is high.

HCCD and EMCCD Clocks for Electronics Shutter

The HCCD and EMCCD clocks must be static during the

frame, line, and electronic shutter timing sequences.

Table 16. HCCD AND EMCCD CLOCKS FOR ELECTRONICS SHUTTER

Clocks

State

High

Low

H1S, H1, H1SEM, H1BEM

H2S, H2, H2SW, H2L, H2X, H2SEM, H2BEM

HCCD Timing

To reverse the direction of charge transfer in a Horizontal

CCD, the timing patterns of the H1B and H2B inputs of that

HCCD are exchanged. If a HCCD is not used, all of its gates

are to be held at the high level.

Table 17. HCCD TIMING

Mode

HCCD a, b Timing

H1Ba = H2Bb = H1Sa = H1Sb

HCCD c, d Timing

Single

3.3 V

H2Ba = H1Bb = H2Sa = H2Sb

Dual

H1Ba = H1Bb = H1Sa = H1Sb

H2Ba = H2Bb = H2Sa = H2Sb

3.3 V

Quad

H1Ba = H1Bb = H1Sa = H1Sb

H2Ba = H2Bb = H2Sa = H2Sb

H1Bc = H1Bd = H1Sc = H1Sd

H2Bc = H2Bd = H2Sc = H2Sd

Table 18. FRAME RATES

Single

Dual (Left/Right)

6.9

Dual (Top/Bottom)

Quad

Unit

fps

3.7

7.4

13.8

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31

KAE−04472

Image Exposure and Readout

The flowchart for image exposure and readout is shown in

the figure below. The electronic shutter timing may be

omitted to obtain an exposure time equal to the image read

out time. NEXP is the number of lines exposure time and NV

is the number of VCCD clock cycles (row transfers).

Table 19. IMAGE READOUT TIMING

Mode

Single

NH

NV

Line Timing

Frame Timing

2316

1158

2316

1158

2144

1072

L1

L2

F1

F2

Dual (Left/Right)

Dual (Top/Bottom)

Quad

Frame Timing

Line Timing

Pixel Timing

Line Timing

Pixel Timing

Repeat NH Times

Repeat NV − NEXP

Times

Repeat NEXP Times

Electronic Shutter

Timing

Figure 33. The Image Readout Timing Flow Chart

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32

KAE−04472

Long Integrations and Readout

For extended integrations the output amplifiers need to be

powered down. When powered up, the output amplifiers

emit near infrared light that is sensed by the photodiodes. It

will begin to be visible in images of 30 second integrations

or longer.

Stop all VCCD clocks at

the V (−8 V) level.

LOW

Pulse the electronic shutter on V

empty all photodiodes.

to

SUB

Integration begins on the falling edge of

the electronic shutter pulse.

Set VDD = +5.0 V

Set VDD1 = 0.0 V

Set VSS1 = 0.0 V

Wait…

Set VDD = +15.0 V

Set VSS1 = −8.0 V

Set VDD1 = +5.0 V

Begin normal line timing

Repeat for at least 6000

lines in single or dual

output mode, 3000 lines

in quad output mode.

Read out the photodiodes

and one image.

Figure 34. Timing Flow Chart for Long Integration Time

To power down the output amplifiers set VDD1 and VSS1

powered. The HCCD and EMCCD may be continue to clock

during integration. If they are stopped during integration

then the EMCCD should be re-started at +7 V amplitude to

flush out any undesired signal before increasing the voltage

to charge multiplying levels.

to 0 V, and VDD2(a,b,c,d) and VDD3(a,b,c,d) to +5 V.

VDD must not be set to 0 V during the integration of an

image. During the time the VDD supply is reduced to +5 V

the VDD15 pin is to be kept at +15 V. The substrate voltage

reference output SUBV will be valid as long as VDD15 is

www.onsemi.com

33

KAE−04472

THERMOELECTRIC COOLER

Representative performance plots for the TEC are shown

below:

of a PWM controller) to maintain the cold side (sensor side)

temperature at 0°C, while the input signal to the EMCCD

registers was 20 mV, the EMCCD gains were set to 20X, and

the horizontal clock rate was 20 MHz. For these conditions,

the recommended maximum input current (Imax) is 1.1 A,

requiring an input voltage (Vmax) of 11.2 V. Lower cold side

temperatures may have different optimum operating

conditions.

Performance Plots of Integrated TECs

For the performance plots below, the thermoelectric

cooler (TEC) was in a dry package cavity, sealed under

nitrogen. The ambient temperature was 27°C. The TEC

controller was operated in DC mode (maximum pulse width

ΔT and Voltage vs. Current

70.0

60.0

50.0

40.0

30.0

20.0

10.0

0.0

Cooling System Thermal Resistance = 0.0 °C/W

(Maximum Performance)

Cooling System Thermal Resistance = 0.3 °C/W

Cooling System Thermal Resistance = 0.6 °C/W

Cooling System Thermal Resistance = 0.9 °C/W

0.00

0.20

0.40

0.60

0.80

1.00

1.20

1.40

1.60

16.0

14.0

12.0

10.0

8.0

6.0

4.0

2.0

0.0

0.00

0.20

0.40

0.60

0.80

1.00

1.20

1.40

1.60

Operating Current [A]

Figure 35. Performance Plots of Integrated TECs

The plot shown below separately shows the dependence

of cooling performance (DT) on the thermal resistance of the

cooling system.

www.onsemi.com

34

KAE−04472

70

60

50

40

30

20

10

0

y = -19.3x + 61.7

0.0

0.5

1.0

1.5

2.0

2.5

Cooling System Thermal Resistance [K/W] (Cooling source at 27C)

Figure 36. Maximum DT vs. Cooling System Thermal Resistance

The thermoelectric cooler has an on−board thermistor.

The current model has 3% tolerance and 10 kW (Ro) at

25°C (298°K, To). Its performance is shown in the plot

below and follows the equation, where T = temperature in

°K, over the range of 233°K to 398°K, and R = thermistor

T

resistance in ohms.

360

340

320

300

280

260

240

220

200

100

1,000

10,000

100,000

1,000,000

Resistance [W]

Figure 37. Thermistor Resistance vs. Temperature

1

T +

3

Ǌ

ǋ

(7.96E * 4) ) (2.67E * 4) * ln(R_T) ) (1.21E * 7) * (ln(R_T))

www.onsemi.com

35

KAE−04472

STORAGE AND HANDLING DETAILS

For information on charge binning please download the

KAE−04471 Charge Binning Application Note

(AND9597/D) from www.onsemi.com.

For quality and reliability information, please download

the Quality & Reliability Handbook (HBD851/D) from

www.onsemi.com.

For information on Storage, ESD prevention, cover glass

care, and cleanliness, please download the Image Sensor

Handling and Best Practices Application Note

(AN52561/D) from www.onsemi.com.

Please note that CCD products are not shipped or stored

in Moisture Barrier Bags (MBB), and Moisture Sensitivity

Level (MSL) ratings are not specified.

For information on device numbering and ordering codes,

please download the Device Nomenclature technical note

(TND310/D) from www.onsemi.com.

For information on Standard terms and Conditions of

Sale, please download Terms and Conditions from

www.onsemi.com.

For information on soldering recommendations, please

download the Soldering and Mounting Techniques

Reference

Manual

(SOLDERRM/D)

from

www.onsemi.com.

www.onsemi.com

36

KAE−04472

MECHANICAL INFORMATION

Figure 38. Completed Assembly (1 of 3)

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37

KAE−04472

Figure 39. Completed Assembly (2 of 3)

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38

KAE−04472

Figure 40. Completed Assembly (3 of 3)

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39

KAE−04472

Cover Glass

(20.30 SQ) SQ

A−ZONE

4X (C0.50)

4X (R0.30)

28.50 SQ

16X (C0.20)

0.95 0.05

NCO−150HB EPOXY

THICKNESS: 0.14 0.04

NOTES:

1. DUST, SCRATCH, INCLUSION DEFECT SPEC: 10m m MAX (A−ZONE).

2. GLASS MATERIAL: SCHOTT D263T eco.

3. ANTI−REFLECTION COATINGS ON BOTH SIDES OF SUBSTRATE TO MEET THE FOLLOWING

MINIMUM TRANSMISION SPECIFICATIONS:

365 nm

Tabs > 50%

Tabs > 97%

Tabs > 85%

Tave > 88%

400−900 nm

900−1100 nm

4. EPOXY IS B−STAGED FORM (REF. KSD−248−0109, SPEC KSD−241−0009)

5. ALL CONTAMINATION OUTSIDE THE A−ZONE MUST BE REMOVABLE WITH N2 AT 40 PSI.

0.50mm, Y[ 0.50mm, Z[

6. EDGE CHIPS: X[

0.48mm.

Figure 41. Cover Glass

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40

KAE−04472

Figure 42. Cover Glass Transmission

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent

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LITERATURE FULFILLMENT:

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◊

KAE−04472/D

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41


型号：	KAE-04472-ABA-SD-EE
厂家：	ONSEMI
描述：	2096 (H) x 2096 (V) Interline Transfer EMCCD Image Sensor CD
文件：	总41页 (文件大小：646K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

KAE-04472-ABA-SD-EE [ONSEMI]

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