KAF-09000 [ONSEMI]
Full Frame CCD Image Sensor;
| 型号： | KAF-09000 |
| 厂家： | 
ONSEMI |
| 描述： | Full Frame CCD Image Sensor CD |
| 文件： | 总21页 (文件大小：456K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
KAF-09000
3056 (H) x 3056 (V) Full
Frame CCD Image Sensor
Description
Combining high resolution with outstanding sensitivity, the
KAF−09000 image sensor has been specifically designed to meet the
needs of next−generation low cost digital radiography and scientific
imaging systems. The high sensitivity available from 12−micron
square pixels combines with a low noise architecture to allow system
designers to improve overall image quality, or to relax system
tolerances to achieve lower cost. The excellent uniformity of the
KAF−09000 image sensor improves overall image integrity by
simplifying image corrections, while integrated anti−blooming
protection prevents image bleed from over−exposure in bright areas of
the image. To simplify device integration, the KAF−09000 image
sensor uses the same pin−out and package as the KAF−16801 image
sensor.
www.onsemi.com
The sensor utilizes the TRUESENSE Transparent Gate Electrode to
improve sensitivity compared to the use of a standard front−side
illuminated polysilicon electrode.
Figure 1. KAF−09000 CCD Image Sensor
Table 1. GENERAL SPECIFICATIONS
Features
Parameter
Typical Value
• TRUESENSE Transparent Gate Electrode
for High Sensitivity
• Large Pixel Size
• Large Image Area
• High Quantum Efficiency
• Low Noise Architecture
• Broad Dynamic Range
Architecture
Full Frame CCD [Square Pixels]
3103 (H) x 3086 (V) = 9.6 Mp
3085 (H) x 3085 (V) = 9.5 Mp
3056 (H) x 3056 (V) = 9.3 Mp
12 mm (H) x 12 mm (V)
Total Number of Pixels
Number of Effective Pixels
Number of Active Pixels
Pixel Size
Active Image Size
36.7 mm (H) x 36.7 mm (V)
51.9 mm diagonal,
645 1.3x optical format
Applications
Aspect Ratio
Square
1
Horizontal Outputs
Saturation Signal
• Medical
• Scientific
−
110 ke
−
Output Sensitivity
24 mV/e
Quantum Efficiency (550 nm)
Responsivity (550 nm)
64%
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
2
2595 ke/mJ/cm
62.3 V/mJ/cm
2
−
Read Noise (f = 3 MHz)
7 e
Dark Signal (T = 25°C)
5 e/pix/sec
Dark Current Doubling Temperature
Linear Dynamic Range (f = 4 MHz)
7°C
84 dB
Blooming Protection
(4 ms exposure time)
> 100 X saturation exposure
Maximum Data Rate
Package
10 MHz
CERDIP, (sidebrazed pins, CuW)
AR coated 2 sides Taped Clear
Cover Glass
NOTE: Parameters above are specified at T = 25°C unless otherwise noted.
© Semiconductor Components Industries, LLC, 2015
1
Publication Order Number:
February, 2015 − Rev. 3
KAF−09000/D
KAF−09000
ORDERING INFORMATION
Table 2. ORDERING INFORMATION
Part Number
Description
Marking Code
KAF−09000−ABA−DP−BA
KAF−09000−ABA−DP−AE
KAF−09000−ABA−DD−BA
KAF−09000−ABA−DD−AE
Monochrome, Microlens, CERDIP Package, (sidebrazed, CuW),
Taped clear coverglass, Standard grade
KAF−09000−ABA
[Serial Number]
Monochrome, Microlens, CERDIP Package, (sidebrazed, CuW),
Taped clear coverglass, Engineering sample
Monochrome, Microlens, CERDIP Package, (sidebrazed, CuW),
AR coated 2 sides, Standard grade
Monochrome, Microlens, CERDIP Package, (sidebrazed, CuW),
AR coated 2 sides, Engineering sample
See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention
used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at
www.onsemi.com.
www.onsemi.com
2
KAF−09000
DEVICE DESCRIPTION
Architecture
1 Test Row
9
V1
V2
KAF−09000
4 1 3 20
9 1 8
3056 H x 3056 V
LOD
12 μm x 12 μm Pixels
OG
RD
RG
20 Dark
3056
VDD
VOUT
VSS
6 4 1 3 20
9 1 2
1
SUB
H1
H2
Figure 2. Block Diagram
Dark Reference Pixels
formation of potential wells at each pixel site. The number
of electrons collected is linearly dependent on light level and
exposure time and non−linearly dependent on wavelength.
When the pixel’s capacity is reached, excess electrons are
discharged into the lateral overflow drain to prevent
crosstalk or ‘blooming’. During the integration period, the
V1 and V2 register clocks are held at a constant (low) level.
The periphery of the device is surrounded with a border of
light shielded pixels creating a dark region. Within this dark
region, there are 20 leading dark pixels on every line as well
as 20 full dark lines at the start and 9 full dark lines at the end
of every frame. Under normal circumstances, these pixels do
not respond to light and may be used as a dark reference.
Dummy Pixels
Charge Transport
Within each horizontal shift register there are 14 leading
pixels and 3 trailing pixels. These are designated as dummy
pixels and should not be used to determine a dark reference
level.
The integrated charge from each pixel is transported to the
output using a two−step process. Each line (row) of charge
is first transported from the vertical CCDs to a horizontal
CCD register using the V1 and V2 register clocks. The
horizontal CCD is presented a new line on the falling edge
of V2 while H1 is held high. The horizontal CCDs then
transport each line, pixel by pixel, to the output structure by
alternately clocking the H1 and H2 pins in a complementary
fashion.
Image Acquisition
An electronic representation of an image is formed when
incident photons falling on the sensor plane create
electron−hole pairs within the device. These
photon−induced electrons are collected locally by the
www.onsemi.com
3
KAF−09000
HORIZONTAL REGISTER
Output Structure
H2
H1
HCCD
Charge
Transfer
VDD
OG
RG
RD
Floating
Diffusion
VOUT
VSS
Source
Follower
#1
Source
Follower
#2
Source
Follower
#3
Figure 3. Output Architecture (Left or Right)
The output consists of a floating diffusion capacitance
connected to a three−stage source follower. Charge
presented to the floating diffusion (FD) is converted into a
voltage and is current amplified in order to drive off−chip
loads. The resulting voltage change seen at the output is
linearly related to the amount of charge placed on the FD.
Once the signal has been sampled by the system electronics,
the reset gate (RG) is clocked to remove the signal and FD
is reset to the potential applied by reset drain (RD).
Increased signal at the floating diffusion reduces the voltage
seen at the output pin. To activate the output structure, an
off−chip current source must be added to the VOUT pin of
the device. See Figure 4.
www.onsemi.com
4
KAF−09000
Output Load
VDD = +15 V
Iout = 5 mA
0.1 μF
VOUT
2N3904
or Equiv.
Buffered
Video
Output
140 W
1 kW
Note: Component values may be revised based on operating conditions and other design considerations.
Figure 4. Recommended Output Structure Load Diagram
www.onsemi.com
5
KAF−09000
PHYSICAL DESCRIPTION
Pin Description and Device Orientation
SUB
V2
1
2
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
V2
V2
V1
(3056,3056)
V2
3
V1
4
V1
V1
5
SUB
N/C
N/C
N/C
N/C
SUB*
N/C
N/C
N/C
LOD
N/C
N/C
SUB*
SUB*
SUB
OG
6
7
8
9
10
11
12
13
VDD
VOUT 14
N/C
H2
VSS
RD
15
16
17
Pixel (1,1)
H1
RG
SUB
Notes: 1. Pins with the same name are to be tied together on the circuit board and have the same timing.
2. Unlike the KAF−16801, pins 9, 10, and, 25 are internally connected to SUB. They may be connected to SUB
on the printed circuit board or may be left floating.
Figure 5. Pinout Diagram
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
SUB
H1
Substrate
Table 3. PIN DESCRIPTION
Horizontal Phase 1
Horizontal Phase 2
No Connection
Pin
1
Name
SUB
V2
Description
H2
Substrate
N/C
N/C
N/C
N/C
SUB*
N/C
N/C
N/C
N/C
SUB
V1
2
Vertical CCD Clock − Phase 2
Vertical CCD Clock − Phase 2
Vertical CCD Clock − Phase 1
Vertical CCD Clock − Phase 1
Anti Blooming Drain
No Connection
No Connection
3
V2
No Connection
4
V1
No Connection
5
V1
No Connection
6
LOD
N/C
N/C
SUB*
SUB*
SUB
OG
No Connection
7
No Connection
8
No Connection
No Connection
9
No Connection
No Connection
10
11
12
13
14
15
16
17
No Connection
Substrate
Substrate
Vertical CCD Clock − Phase 1
Vertical CCD Clock − Phase 1
Vertical CCD Clock − Phase 2
Vertical CCD Clock − Phase 2
Output Gate
V1
VDD
VOUT
VSS
RD
Output Amplifier Supply
Video Output
V2
V2
Output Amplifier Return
Reset Drain
*Unlike the KAF−16801, pins 9, 10, and, 25 are internally connected
to SUB. They may be connected to SUB on the printed circuit board
or must be left floating.
RG
Reset Gate
www.onsemi.com
6
KAF−09000
IMAGING PERFORMANCE
Table 4. TYPICAL OPERATIONAL CONDITIONS
Description
Read out time treadout
Integration time (tint)
Horizontal clock frequency
Temperature
Condition − Unless otherwise noted
Notes
2533 ms
variable
4 MHz
25°C
Includes over clock pixels
Room temperature
Mode
integrate – readout cycle
Operation
Nominal operating voltages and timing with min. vertical
pulse width tVw = 20 ms
Table 5. SPECIFICATIONS
Description
Symbol
Min.
Nom.
110k
64
Max.
Units
Notes
Verification Plan
−
−
11
Saturation Signal
Ne
95k
e
die
sat
12
Quantum Efficiency (550 nm)
Photo Response Non−Linearity
Photo Response Non−Uniformity
Integration Dark Signal
QE
%
%
1
2
3
4
design
design
12
PRNL
PRNU
1
11
0.5
5
2.5
20
%
die
die
11
Vdark, int
e/pix/sec
2
0.6
80
2.8
320
20
pA/cm
11
11
Read out Dark Signal
Vdark, read
DSNU
ΔT
electrons
e/pix/sec
°C
5
6
die
Dark Signal Non−Uniformity
Dark Signal Doubling Temperature
Read Noise
die
12
7
7
design
design
design
design
design
−
12
12
12
12
NR
14
e rms
7
8
9
Linear Dynamic Range
Blooming Protection
DR
84
dB
x Vsat
mV/e
V
Xab
100
−
Output Amplifier Sensitivity
DC Offset, output amplifier
Output Amplifier Bandwidth
Output Impedance, Amplifier
Vout/Ne
24
Vrd−2.0
88
11
Vodc
Vrd−4
10
die
12
f
MHz
W
design
−3dB
11
ROUT
150
250
die
1. Increasing output load currents to improve bandwidth will decrease these values.
2. Worst case deviation from straight line fit, between 1% and 90% of Vsat.
3. One Sigma deviation of a 128 x 128 sample when CCD illuminated uniformly.
4. Average of all pixels with no illumination at 25°C.
5. Read out dark current depends on the read out time, primarily when the vertical CCD clocks are at their high levels. This is approximately
0.125 sec/image for nominal timing conditions, tVw = 20 ms. The read out dark current will increase as tVw is increased. The readout dark
current is also dependent on the operating temperature. The specification applies to 25°C.
6. Average integration dark signal of any of 32 x 32 blocks within the sensor. (each block is 128 x 128 pixels)
7. Output amplifier noise only. Operating at pixel frequency up to 4 MHz, bandwidth <20 MHz, tint = 0, and no dark current shot noise.
8. 20log (Vsat/VN)
9. Xab is the number of times above the Vsat illumination level that the sensor will bloom by spot size doubling. The spot size is 10% of the
imager height. Xab is measured at 4 ms.
10.Video level offset with respect to ground.
11. A parameter that is measured on every sensor during production testing.
12.A parameter that is quantified during the design verification activity.
www.onsemi.com
7
KAF−09000
TYPICAL PERFORMANCE CURVES (QE)
KAF−09000 Spectral Response
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
300
400
500
600
700
800
900
1000
1100
Wavelength (nm)
Figure 6. Typical Spectral Response
KAF−09000 Angle Response
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
Horizontal
Vertical
−40 −35 −30 −25 −20 −15 −10 −5
0
5
10 15 20 25 30 35 40
Degrees
Figure 7. Typical Angle Response
www.onsemi.com
8
KAF−09000
KAF−09000 Dark Current
100
10
1
Integration
Read out
−10
−5
0
5
10
15
20
25
30
0.1
Temperature (C)
Figure 8. Dark Current
KAF−09000 Noise Floor
System noise = 6.5 electrons (10MHz bandwidth)
20
15
10
5
0
−20
−10
0
10
20
30
40
Temperature (C)
Total Noise (Dark current, amplifier,
system)
CCD only (dark current, amplifier)
Figure 9. Noise Floor
www.onsemi.com
9
KAF−09000
KAF−09000 Linearity
1000000
100000
10000
1000
100
10
1
1
10
100
1000
10000
0.1
0.01
Integration time (Arbitrary)
measured
percent deviation from fit
fit
Figure 10. Linearity
www.onsemi.com
10
KAF−09000
DEFECT DEFINITIONS
Operating Conditions
All cosmetic tests performed at approximately 25°C.
Table 6. SPECIFICATIONS
Classification
Points
Clusters
Columns
Includes Dead Columns
Standard Grade
< 200
< 20
< 10
yes
Point Defects
Column Defect
A grouping of more than 10 point defects along a single
column
Dark: A pixel, which deviates by more than 6% from
neighboring pixels when illuminated to 70% of saturation
−or−
−or−
A column containing a pixel with dark current
> 15,000 e/pixel/sec (bright column)
−or−
Bright: A Pixel with dark current > 3,000 e/pixel/sec at 25°C
Cluster Defect
A column that does not meet the CTE specification for all
exposures less than the specified Max sat. signal level and
A grouping of not more than 10 adjacent point defects
Cluster defects are separated by no less than 4 good pixels
in any direction
−
greater than 2 ke
−
−
A pixel, which loses more than 250 e under 2 ke
illumination (trap defect)
Column defects are separated by no less than 4 good
columns. No multiple column defects (double or more) will
be permitted.
Column and cluster defects are separated by at least 4
good columns in the x direction.
www.onsemi.com
11
KAF−09000
OPERATION
Table 7. ABSOLUTE MAXIMUM RATINGS
Description
Diode Pin Voltages
Symbol
Minimum
Maximum
+20
Units
V
Notes
V
diode
V
gate1
–0.5
−18
1, 2
1, 3
4
Adjacent Gate Pin Voltages
Isolated Gate Pin Voltages
Output Bias Current
+18
V
V
−0.5
+20
V
1−2
out
I
−30
mA
V
5
LOD Diode Voltage
V
LOD
−0.5
−60
−13.0
60
6
Operating Temperature
T
OP
°C
7
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Referenced to pin SUB
2. Includes pins: RD, VDD, VSS, VOUT.
3. Includes pins: V1, V2, H1, H2, VOG.
4. Includes pins: RG.
5. Avoid shorting output pins to ground or any low impedance source during operation. Amplifier bandwidth increases at higher currents and
lower load capacitance at the expense of reduced gain (sensitivity). Operation at these values will reduce MTTF.
6. V1, H1, V2, H2, H1L, VOG, and RD are tied to 0 V.
7. Noise performance will degrade at higher temperatures due to the temperature dependence of the dark current.
8. Absolute maximum rating is defined as a level or condition that should not be exceeded at any time. If the level or condition is exceeded,
the device will be degraded and may be damaged.
Power−up Sequence
The sequence chosen to perform an initial power−up is not
critical for device reliability. A coordinated sequence may
minimize noise and the following sequence is
recommended:
1. Connect the ground pins (SUB).
2. Supply the appropriate biases and clocks to the
remaining pins.
Table 8. DC BIAS OPERATING CONDITIONS
Maximum DC
Current (mA)
Description
Reset Drain
Symbol
Minimum
12.8
Nominal
Maximum
13.2
Units
V
Notes
V
RD
13
2.0
15.0
0
I
= 0.01
= 3.0
RD
Output Amplifier Supply
Output Amplifier Return
Substrate
V
1.8
2.2
V
I
SS
SS
DD
V
14.8
17.0
V
I + I
OUT SS
V
V
V
0.01
0.01
0.01
SUB
Output Gate
V
0
1
2
V
OG
LOD
OUT
Lateral Overflow Drain
Video Output Current
7.8
−3
8.0
−5
9.0
−7
V
I
mA
1
1. An output load sink must be applied to VOUT to activate output amplifier – see Figure 4.
AC Operating Conditions
Table 9. CLOCK LEVELS
Description
V1 Low Level
Symbol
V1L
Level
Low
Minimum
−9.5
2.3
Nominal
−9.0
2.5
Maximum
−8.5
2.7
Units
Notes
V
V
V
V
V
V
1
1
1
1
1
1
V1 High Level
V2 Low Level
V2 High Level
H1 Low Level
H1 High Level
V1H
V2L
High
Low
−9.5
2.3
−9.0
2.5
−8.5
2.7
V2H
H1L
High
Low
−2.5
7.5
−2
−1.7
8.2
H1H
High
8
1. All pins draw less than 10 mA DC current. Capacitance values relative to SUB (substrate).
www.onsemi.com
12
KAF−09000
Table 9. CLOCK LEVELS
Description
Symbol
H2L
Level
Low
Minimum
Nominal
Maximum
−1.7
Units
Notes
H2 Low Level
−2.5
7.5
−2
8
V
V
V
V
1
1
1
1
H2 High Level
H2H
High
Low
8.2
RG Low Level
RGL
5.3
5.5
11
5.7
RG High Level
RGH
High
11.2
10.8
1. All pins draw less than 10 mA DC current. Capacitance values relative to SUB (substrate).
Capacitance Equivalent Circuit
LOD
CLOD_V2
CLOD
CLOD_V1
CV1_V2
V2
H1
V1
CV1
CV2
CVH
CH1_H2
H2
CH2
CH1
CH1_OG
RG
OG
CRG
COG
Figure 11. Equivalent Circuit Model
Table 10.
Description
Label
Value
Unit
nF
nF
nF
nF
nF
nF
pF
pF
pF
pF
pF
pF
LOD−Sub Capacitance
LOD−V1 Capacitance
LOD−V2 Capacitance
V1−V2 Capacitance
V1−Sub Capacitance
V2−Sub Capacitance
V2−H1 Capacitance
H1−H2 Capacitance
H1−Sub Capacitance
H2−Sub Capacitance
OG−Sub Capacitance
RG−Sub Capacitance
C
6.5
36
LOD
C
C
LOD_V1
LOD_V2
36
C
80
V1_V2
V1_SUB
V2_SUB
C
C
250
250
36
C
VH
C
75
H1_H2
H1_Sub
H2_Sub
OG_Sub
RG_Sub
C
C
500
300
5
C
C
13
www.onsemi.com
13
KAF−09000
TIMING
Table 11. REQUIREMENTS AND CHARACTERISTICS
Description
H1, H2 Clock Frequency
H1, H2 Rise, Fall Times
V1, V2 Rise, Fall Times
V1 − V2 Cross−over
H1 − H2 Cross−over
H1, H2 Setup Time
RG Clock Pulse Width
V1, V2 Clock Pulse Width
Pixel Period (1 Count)
Readout Time
Symbol
Minimum
Nominal
Maximum
Units
MHz
%
Notes
f
H
4
10
1
3
3
t
, t
5
5
H1r H1f
t , t
V1r V1f
%
V
VCR
V
HCR
−1
2
0
3
1
5
V
V
t
5
10
ms
HS
t
5
10
ns
4
RGw
t
20
20
ms
Vw
t
e
250
2,533
ns
2
7
5
6
t
ms
readout
Integration Time
t
int
Line Time
t
0.821
ms
line
1. 50% duty cycle values.
2. CTE will degrade above the maximum frequency.
3. Relative to the pulse width (based on 50% of high/low levels).
4. RG should be clocked continuously.
5. Integration time is user specified.
6. (3103 * t ) + t + (2 * t ) = 0.821 msec
e
= t
HS
Vw
7. t
* 3086 lines
readout
line
Edge Alignment
H1
VHCR
V1
V2
VVCR
V1,V2
Figure 12. Timing Edge Alignment
www.onsemi.com
14
KAF−09000
Frame Timing
1 Frame = 3086Lines
tint
treadout
V2
V1
Line
1
2
3
3085
3086
H2
H1
Figure 13. Frame Timing
Frame Timing Detail
90%
10%
V1
tVw
tV1f
tV1r
90%
V2
10%
tV2r
tV2f
Figure 14. Frame Timing Detail
Line Timing
Line Content
t line
3056 Active Pixels/Line
36 −3091
V2
tV
tHS
3092−3100
3101−3103
16−35
12−15
1 −11
V1
te
tV
H1 / H2 count values
H2
Internal Test Pixels
3103
Dummy Pixels
H1
Dark Reference Pixels*
Photoactive Pixels **
RG
Figure 15. Line Timing
www.onsemi.com
15
KAF−09000
Pixel Timing
Figure 16. Pixel Timing
Pixel Timing Detail
90 %
10 %
RGamp
tRG
R
RGlo
tRGf
t
RG
90 %
10 %
50 %
H1
,
H1,
ampamp
H1low
H2lo
te
2
t
H12
t
H12
Figure 17. Pixel Timing Detail
www.onsemi.com
16
KAF−09000
Example Waveforms
Figure 18. Horizontal Clocks
Figure 19. Video Waveform
NOTE: The upper waveform was taken at the CCD output and the lower waveform was taken at the analog to digital
converter, and is bandwidth limited.
www.onsemi.com
17
KAF−09000
Figure 20. Video Waveform and Clamp Clock
Figure 21. Video Waveform and Sample Clock
www.onsemi.com
18
KAF−09000
STORAGE AND HANDLING
Table 12. STORAGE CONDITIONS
Description
Symbol
Minimum
Maximum
Units
Notes
Storage Temperature
T
ST
−20
70
°C
1
1. Long term storage toward the maximum temperature will accelerate color filter degradation.
For information on ESD and cover glass care and
cleanliness, please download the Image Sensor Handling
and Best Practices Application Note (AN52561/D) from
www.onsemi.com.
For quality and reliability information, please download
the Quality & Reliability Handbook (HBD851/D) from
www.onsemi.com.
For information on device numbering and ordering codes,
please download the Device Nomenclature technical note
(TND310/D) from www.onsemi.com.
For information on soldering recommendations, please
download the Soldering and Mounting Techniques
Reference
www.onsemi.com.
Manual
(SOLDERRM/D)
from
For information on Standard terms and Conditions of
Sale, please download Terms and Conditions from
www.onsemi.com.
www.onsemi.com
19
KAF−09000
MECHANICAL INFORMATION
Completed Assembly
Figure 22. Completed Assembly (1 of 1)
www.onsemi.com
20
KAF−09000
Cover Glass Specification
MAR Glass for Sealed Cover
1. Scratch and dig: 10 micron max
2. Substrate material Schott D263T eco or equivalent
3. Multilayer anti−reflective coating
Table 13.
Wavelength
420 − 450
450 − 630
630 − 680
Total Reflectance
2%
1%
2%
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
KAF−09000/D
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明