KLI-8023-SAA-ED-AA_技术文档

KLI-8023

Linear CCD Image Sensor

Description

The KLI−8023 Image Sensor is a multispectral, linear solid state

image sensor for color scanning applications where ultra-high

resolution is required.

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The imager consists of three parallel linear photodiode arrays, each

with 8,000 active photosites for the output of red, green, and blue

(R, G, B) signals. This device offers high sensitivity, high data rates,

low noise and negligible lag. Individual electronic exposure control

for each color allows the KLI−8023 sensor to be used under a variety

of illumination conditions. The imager can be operated in an Extended

Dynamic Range mode for the most demanding applications.

Table 1. GENERAL SPECIFICATIONS

Parameter

Architecture

Typical Value

3 Channel, RGB Trilinear CCD

8002 × 3

Figure 1. KLI−8023 Linear CCD

Image Sensor

Pixel Count

Pixel Size

9 mm (H) × 9 mm (V)

9 mm

Features

Pixel Pitch

• 12 Line Spacing between Color Channels

• Single Shift Register per Channel

• High Off-Band Spectral Rejection

• Dark Reference Pixels Provided

• Anti-Reflective Glass

• Wide Dynamic Range, Low Noise

• Dual Dynamic Range Mode Operation

• No Image Lag

• Electronic Exposure Control

• High Charge Transfer Efficiency

• Two-Phase Register Clocking

• 74 ACT Logic Compatible Clocks

• 6 MHz Maximum Data Rate

Inter-Array Spacing

Imager Size

108 mm (12 Lines Effective)

72.0 mm (H) × 0.225 mm (V)

−

Saturation Signal

185 ke (Normal DR Mode)

400 ke (Extended DR Mode)

Dynamic Range

(2 MHz Data Rate)

84 dB (Normal DR Mode)

90 dB (Extended DR Mode)

Responsivity

R, G, B (−RAA)

R, G, B (−DAA)

Mono (−AAA, −SAA, −MAA)

2

32, 20, 20 V/mJ/cm

2

29, 19, 18 V/mJ/cm

2

33 V/mJ/cm

−

Output Sensitivity

Dark Current

14.4 mV/e

0.002 pA/Pixel

8°C

Dark Current Doubling Rate

Charge Transfer Efficiency

Photoresponse Non-Uniformity

Lag (First Field)

0.999998/Transfer

3% Peak-Peak

0.025%

Applications

• Digitization

• Medical Imaging

• Photography

Maximum Data Rate

Package

6 MHz/Channel

CERDIP (Sidebrazed, CuW)

AR Coated, 2 Sides

Cover Glass

ORDERING INFORMATION

See detailed ordering and shipping information on page 2 of

this data sheet.

NOTE: Parameters above are specified at T = 25°C (junction temperature)

and 1 MHz clock rates unless otherwise noted.

1

Publication Order Number:

March, 2017 − Rev. 3

KLI−8023/D

KLI−8023

ORDERING INFORMATION

Table 2. ORDERING INFORMATION − KLI−8023 IMAGE SENSOR

Part Number

Description

Marking Code

KLI−8023−AAA−ED−AA

Monochrome, No Microlens, CERDIP Package (Leadframe),

Clear Cover Glass with AR Coating (Both Sides), Standard Grade

KLI−8023 (Lot Code)

(Serial Number)

KLI−8023−AAA−ED−AE

KLI−8023−AAA−ER−AA

KLI−8023−AAA−ER−AE

KLI−8023−RAA−ED−AA

KLI−8023−RAA−ED−AE

KLI−8023−SAA−ED−AA

Monochrome, No Microlens, CERDIP Package (Leadframe),

Clear Cover Glass with AR Coating (Both Sides), Engineering Sample

Monochrome, No Microlens, CERDIP Package (Leadframe),

Clear Cover Glass with AR Coating (Both Sides), Standard Grade

KLI−8023 (Lot Code)

(Serial Number)

Monochrome, No Microlens, CERDIP Package (Leadframe),

Clear Cover Glass with AR Coating (Both Sides), Engineering Sample

Gen2 Color (RGB), No Microlens, CERDIP Package (Leadframe),

Clear Cover Glass with AR Coating (Both Sides), Standard Grade

KLI−8023 (Lot Code)

(Serial Number)

Gen2 Color (RGB), No Microlens, CERDIP Package (Leadframe),

Clear Cover Glass with AR Coating (Both Sides), Engineering Sample

Monochrome with RB Surround – Gen2, No Microlens, CERDIP Package

(Leadframe), Clear Cover Glass with AR Coating (Both Sides), Standard

Grade

KLI−8023 (Lot Code)

(Serial Number)

KLI−8023−SAA−ED−AE

KLI−8023−MAA−ED−AA*

KLI−8023−MAA−ED−AE*

Monochrome with RB Surround – Gen2, No Microlens, CERDIP Package

(Leadframe), Clear Cover Glass with AR Coating (Both Sides), Engineering

Sample

Monochrome with RB Surround – Gen1, No Microlens, CERDIP Package

(Leadframe), Clear Cover Glass with AR Coating (Both Sides), Standard

Grade

KLI−8023 (Lot Code)

(Serial Number)

Monochrome with RB Surround – Gen1, No Microlens, CERDIP Package

(Leadframe), Clear Cover Glass with AR Coating (Both Sides), Engineering

Sample

KLI−8023−DAA−ED−AA*

KLI−8023−DAA−ED−AE*

Gen1 Color (RGB), No Microlens, CERDIP Package (Leadframe),

Clear Cover Glass with AR Coating (Both Sides), Standard Grade

KLI−8023 (Lot Code)

(Serial Number)

Gen1 Color (RGB), No Microlens, CERDIP Package (Leadframe),

Clear Cover Glass with AR Coating (Both Sides), Engineering Sample

*Not recommended for new designs.

Table 3. ORDERING INFORMATION − EVALUATION SUPPORT

Part Number

Description

KLI−8023−12−5−A−EVK

Evaluation Board (Complete Kit)

See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention

used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at

www.onsemi.com.

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2

KLI−8023

DEVICE DESCRIPTION

LS

LOGn

Photodiode Array

14 Test

8002 Active Pixels

16 Dark

RD

VDD

TG1

TG2

IG

ID

f R

6 Blank

FD

CCD Cells

VIDn

OG

SUB

f2B

VSSn

Figure 2. Single Channel Schematic

−

Dark Reference Pixels

saturation exposure in this mode increases to 400,000 e

with a saturation voltage in excess of 5 volts.

Dark reference pixels are groups of photosensitive pixels

covered by a metal light shield. These pixels are used as

a black level reference for the image sensor output. Since the

incident light is blocked from entering these pixels,

the signal contained in these pixels is due only to dark

current. It is assumed that each photosensitive pixel (active

and dark reference) will have approximately the same dark

signal; thus, subtracting the average dark reference signal

from each active pixel signal will remove the background

dark signal level. Dark reference pixels are typically located

at one or both ends of the arrays, as shown earlier in this

document for a linear image sensor in the single channel

schematic.

Image Acquisition

During the integration period, an image is obtained by

gathering electrons generated by photons incident upon the

photodiodes. The charge collected in the photodiode array

is a linear function of the local exposure. The charge is stored

in the photodiode itself and is isolated from the CCD shift

registers during the integration period by the transfer gates

TG1 and TG2, which are held at barrier potentials. At the

end of the integration period, the CCD register clocking is

stopped with the f1 and f2 gates being held in a ‘high’ and

‘low’ state respectively. Next, the TG gates are turned ‘on’

causing the charge to drain from the photodiode into the TG1

storage region. As TG1 is turned back ‘off’ charge is

transferred through TG2 and into the f1 storage region.

The TG2 gate is then turned ‘off’, isolating the shift registers

from the accumulation region once again. Complementary

clocking of the f1 and f2 phases now resumes for readout

of the current line of data while the next line of data is

integrated.

Dynamic Range

Dynamic Range (DR) is the ratio of the maximum output

signal, or saturation level, of an image sensor to the dark

noise level of the imager. The dark noise level, or noise floor

of an imager is typically expressed as the root mean square

(rms) variation in dark signal voltage. The dark signal

includes components from dark current within the photosite

and CCD regions, reset transistor and output amplifier noise,

and input clocking noise. An input referred noise signal in

the charge domain can be calculated by dividing the dark

noise voltage by the imager charge-to-voltage conversion

factor. The dynamic range is typically expressed in units of

Charge Transport

Readout of the signal charge is accomplished by

two-phase, complementary clocking of the f1 and f2 gates.

The register architecture has been designed for high speed

clocking with minimal transport and output signal

degradation, while still maintaining low (6.25 Vp-p min)

clock swings for reduced power dissipation, lower clock

noise and simpler driver design. The data in all registers is

clocked simultaneously toward the output structures.

The signal is then transferred to the output structures in

a parallel format at the falling edge of the f2 clocks.

Re-settable floating diffusions are used for the

charge-to-voltage conversion while source followers

provide buffering to external connections. The potential

change on the floating diffusion is dependent on the amount

decibels as: DR = 20 ⋅ LOG (N

/ Noise).

SAT

High Dynamic Range Mode (DR)

Two modes of device operation can be realized,

the ‘normal mode’ and ‘high dynamic range mode’. In

‘the normal mode’ of operation, clocking of the output

structure reset gate (PHIR, pin 12) remains similar to all

other clocks at 6.25 Vp-p. The usable saturation exposure in

this mode is approximately 180,000 electrons, yielding

a saturation voltage of 2.5 volts. In the ‘high dynamic range’

mode, the reset gate clocking is increased to 12 Vp-pand the

reset drain bias (RD, pin 29) is increased to the upper

amplifier supply voltage (VDD, pin 26). The usable

of signal charge and is given by DV = DQ / C , where

FD

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KLI−8023

DV is the change in potential of the floating diffusion, DQ

is the amount of charge deposited on the floating diffusion,

value occurs at the slowest clocking frequency.

Additionally, dark current doubles for approximately every

8°C increase in temperature.

FD

and C is the floating diffusion capacitance. Prior to each

FD

pixel output, the floating diffusion is returned to the RD level

by the reset clock, fR.

Fixed Pattern Noise

If the output of an image sensor under no illumination is

viewed at high gain, a distinct non-uniform pattern or fixed

pattern noise can be seen. This fixed pattern can be removed

from the video by subtracting the dark value of each pixel

from the pixel values read out in all subsequent frames. Dark

fixed pattern noise is usually caused by variations in dark

current across an imager, but can also be caused by input

clocking signals abruptly starting or stopping, or by having

the CCD clocks not being close compliments of each other.

Mismatched CCD clocks can result in high instantaneous

substrate currents, which when combined with the fact that

the silicon substrate has some non-zero resistance, can result

in the substrate potential bouncing. The pattern noise can

also be seen when the imager is under uniform illumination.

An imager that exhibits a fixed pattern noise under uniform

illumination and shows no pattern in the dark is said to have

light pattern noise or photosensitivity pattern noise. In

addition to the reasons mentioned above, light pattern noise

can be caused by the imager entering saturation,

the nonuniform clipping effect of the anti-blooming circuit,

and by non-uniform photosensitive pixel areas often caused

by debris covering portions of some pixels.

Charge Transfer Efficiency

Charge Transfer Efficiency (CTE) is a measure of how

efficiently electronic charge can be transported by a Charge

Coupled Device (CCD). This parameter is especially

important in linear imager technology due to the fact that

CCDs are often required to transport charge packets over

long distances at very high speeds. The result of poor CTE

is to reduce the overall MTF of the line image in a nonlinear

fashion: the portion of the line image at the far end of the

CCD will be degraded more than the image at the output end

of the CCD, since it will undergo more CCD transfers. There

are many possible mechanisms that can negatively influence

the CTE. Amongst these mechanisms are included

excessive CCD clocking frequency, insufficient drive

potential on the CCD clocking gates, and incorrect voltage

bias on the output gate (OG signal). The effect of these

mechanisms is that some charge is “left behind” during

a CCD transfer clocking cycle. Depending on the limiting

mechanism, the lost charge could be added to the immediate

trailing cell or to a cell further back in time; thus, causing

a horizontal smearing of the line image.

The charge lost from a CCD cell, after being transferred

out of the CCD, is measured with respect to the original

charge level and is termed the charge transfer inefficiency

(CTI). CTI is defined as:

Exposure Control

Exposure control is implemented by selectively clocking

the LOG gates during portions of the scanning line time. By

applying a large enough positive bias to the LOG gate, the

channel potential is increased to a level beyond the ‘pinning

level’ of the photodiode. (The ‘pinning’ level is the

maximum channel potential that the photodiode can achieve

and is fixed by the doping levels of the structure.) With TG1

in an ‘off’ state and LOG strongly biased, all of the

photocurrent will be drawn off to the LS drain. Referring to

the timing diagrams in Figure 12 and Figure 13, one notes

that the exposure can be controlled by pulsing the LOG gate

to a ‘high’ level while TG1 is turning ‘off’ and then

returning the LOG gate to a ‘low’ bias level sometime during

Total Charge Lost

1

_{CTI +}ǒ

Ǔ_@ǒ

Ǔ

Initial Charge

Number of Transfers

The efficiency of the CCD transfer (CTE) is then defined

as simply:

CTE + 1 * CTI

Note that the total transfer efficiency for the entire line

(TTE) is equal to (CTE)N, where N is the total number of

transfers which is equal to the number of phases per cell,

times the number of cells (n).

the line scan. The effective exposure (t

) is the net time

EXP

TTE + CTE @ 2 @ 8022

between the falling edge of the LOG gate and the falling

edge of the TG1 gate (end of the line). Separate LOG

connections for each channel are provided, enabling on-chip

light source and image spectral color balancing. As

a cautionary note, the switching transients of the LOG gates

during line readout may inject an artifact at the sensor

output. Rising edge artifacts can be avoided by switching

LOG during the photodiode-to-CCD transfer period,

preferably during the TG1 falling edge. Depending on

clocking speeds, the falling edge of the LOG should be

synchronous with the f1/f2 shift register readout clocks.

For very fast applications, the falling edge of the LOG gate

may be limited by on-chip RC delays across the array. In this

case artifacts may extend across one or more pixels.

Dark Signal Evaluation

The dark signal evaluation measures the thermally

generated electronic current (i.e. background noise signal)

at a specific operating temperature. Dark current is

measured will all incident radiation removed (i.e. imager is

in the dark). The current measured by the picoammeter is the

dark current of the photodiode array plus the dark current of

the CCD array. Multiplying the dark current by the total

integration time yields the quantity of dark charge. And

dividing the dark current by the number of photodiodes

yields the dark current per photodiode (I

increases linearly with integration time, the worst-case

). Dark voltage

Dark

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KLI−8023

Correlated double sampling (CDS) processing of the output

and may be different from one photosite to the next.

An image sensor with excessive exposure control defects

would be rejected during quality assurance testing. The loss

of charge during the transportation of charge packets from

the photosite to the CCD, which is termed lag, tends to affect

the linearity only at very small signal levels. “Pinned”

photodiodes, or buried photodiodes, have extremely small

lag (< 0.5%), and can be considered to be lag free. The CCD

charge transfer inefficiency (CTI) will reduce the amplitude

of the charge packet as it is transported towards the output

amplifier, with the greatest effect realized at very small

signal levels. Modern CCD’s have CTE in excess of

0.999999 per CCD transfer; thus, the overall effect on

linearity is generally not a concern. If biased properly, the

output amplifier will yield a non-linearity of typically less

than 2%. Non linearity at signal levels beyond the saturation

level is expected and can often vary significantly from pixel

to pixel.

waveform can remove the first order magnitude of such

artifacts. In high dynamic range applications, it may be

advisable to limit the LOG fall times to minimize the current

transients in the device substrate and limit the magnitude of

the artifact to an acceptable level.

Lag

Lag, or decay lag is a measure of the amount of

photogenerated

charge

left

behind

during

a photodiode-to-CCD transfer cycle. Ideally, no charge is

left behind during such transfers and lag is equal to zero; that

is, 100% of the collected photogenerated charge is

transferred to the adjacent CCD. The use of “pinned”

photodiode technology enables the linear imagers to achieve

near perfect lag performance. Improper Transfer Gate (TG)

clocking levels can introduce a lag type response. Thus, care

must be taken to ensure that the clocking levels are not

limiting the lag performance.

Linearity Evaluation

Imager Responsivity

Ideally, the output video amplitude should vary linearly

with incident light intensity over the entire input range of

irradiance. There are many possible phenomena that can

cause non-linearity in the response curve; inadequate CTE

and improper biasing or clocking to name a few.

Electronic exposure control could be used to vary the

photodiode integration time; however, since electronic

exposure control can introduce non-linearity, it is not

recommended as a method of limiting the input signal.

The output signal versus relative irradiance is graphed and

a least squares, linear regression fit to the data is performed.

Responsivity is a measure of the imager output when

exposed to a given optical energy density. It is measured on

monochrome and color (if applicable) versions of an imager

over the entire wavelength range of operation. Imagers

having multiple photodiode arrays with differing color

filters and/or photodiode dimensions have responsivity

measured on each array. Responsivity is reported in units of:

V

mJńcm²

Linearity

The best fit data curve should pass through zero volts and

2

The non-linearity of an image sensor is typically defined

as the percent deviation from the ideal linear response,

which is defined by the line passing through V

remain linear (R > 0.99) up to the V

level.

SAT

Modulation Transfer Function (MTF)

and

SAT

MTF is the magnitude of the spatial frequency response of

a solid-state imager. The three main components of imager

MTF are termed the aperture MTF, diffusion MTF, and

charge transfer efficiency MTF. The aperture MTF results

from the discrete sampling nature of solid-state imagers,

with smaller pixel pitches yielding a better high frequency

MTF response. The diffusion of photogenerated charge

degrades the imager response and is responsible for the

second component. The third component is due to inefficient

charge transfer in the shift register. The maximum spatial

frequency an imager can detect without aliasing occurring

is defined as the Nyquist frequency and is equal to the

inverse of two times the pixel pitch. MTF is typically

reported at the Nyquist frequency, 1/2 Nyquist, and 1/4

Nyquist. The aperture MTF limits the maximum response at

Nyquist to 0.637. (Note that the maximum MTF response is

1.0). The diffusion component will further degrade this

value, especially at longer optical wavelengths.

V

. The percent linearity is then 100 minus the

DARK

non-linearity. The output linearity of a solid-state image

sensor is determined from the linearity of the photon

collection process, the electron exposure structure

non-linearities (if any exists), the efficiency of charge

transportation from the photosite to the output amplifier, and

the output amplifier linearity. The absorption of photons

within the silicon substrate can be considered an ideal linear

function of incident illumination level when averaged over

a given period of time. The existence of an electronic

exposure control circuit adjacent to the photosensitive sites

can introduce a non-linearity into the overall response by

allowing small quantities of charge to remain isolated in

unwanted potential wells. Whether or not any potential wells

exist depends on the design and manufacturing of the

particular image sensor. The existence of such potential

wells in the exposure circuitry, also called exposure control

defects, will degrade the linearity only at small signal levels

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KLI−8023

Noise

Noise is defined as any unwanted signal added to the

Care should be taken to ensure that all quantities are

represented in similar units before any calculations are

performed. Using the above formulas, the absolute quantum

efficiency can be expressed as:

imager output. Temporal noise sources present in a typical

imager include the dark current, photon shot noise, reset

transistor noise, CCD clocking noise, and the output

amplifier noise. Dark current is dependent on the imager

operating temperature and can be reduced by cooling the

imager. The reset transistor noise can be removed using

correlated double sampling signal processing. The photon

shot noise cannot be eliminated; however, by acquiring and

averaging several frames it, and all temporal noise sources,

can be reduced. Another source of noise is the variation in

dark current from pixel to pixel leads to a dark noise pattern

across an imager. The effects of this dark pattern noise can

also be minimized by averaging several frames and then

using the pixel-referenced, dark frame data as the zero

reference level for each pixel.

dV

h @ c

QE(l) + 100% @ R(l) B

B Area_Diode@

dN_e

l

Photoresponse Non-Uniformity (PRNU)

The PRNU measurement is taken in a flat field of

collimated white light. The intensity of the light is set to

a value approximately 10% to 20% below the saturated

signal level. One region (or “window”) of pixels is observed

for uniformity at a given time, and the average response is

calculated for each non-overlapping windowed section. In

the case of medium or low frequency PRNU measurements,

a medium filter of 3−7 pixels is applied to this region to

eliminate the effects of single point defects. The maximum

and minimum pixel is determined for each windowed

section. Again, for each section, the following formula is

applied:

Noise Evaluation

The noise evaluation measures the noise levels associated

with operating the imager at the specified clocking speeds

and temperatures. The test is performed with imager

temperature held stable and all incident light removed.

The noise contributions of the evaluation circuitry also need

to be removed from the calculation. Once this is done, the

total imager noise will be approximately equal to the sum of

squares of each of the CCD clocking noise, output amplifier

noise, and the dark current noise.

Max_Pixel_Value * Min_Pixel_Value

_{PRNU + 100% @}ǒ

Ǔ

Mean_Pixel_Value

Each section is then compared against the specification to

identify the region with the largest percent deviation from

the average response for the imager.

Resolution

The resolution of a solid-state image sensor is the spatial

resolving power of that sensor. The spatial resolution

of a sensor is descried in the spatial frequency domain by the

modulation transfer function (MTF). The discrete sampling

nature of solid-state image sensors gives rise to

a sampling frequency that will determine the upper limit of

the sensor’s frequency response. Resolution is

frequently described in terms of the number of dots or

photosites per inch (DPI) in the imager or object planes.

For example, a linear image sensor with a single array of

1,000 photosites of pitch 10 mm would have a resolution of

2,540 DPI (1,000 / (1,000 ⋅ 0.01 mm ⋅ 1″/25.4 mm)). If the

sensor were used in an optical system to image an 8″ wide

document, then the resolution in the document plane would

be 125 DPI (1,000 pixels / 8″). This example is slightly

misleading in that it does not consider the frequency

response of the sensor or the optics. In reality, the sensor will

have an MTF of between 0.2 and 0.7 at the Nyquist spatial

frequency and the optics are likely to have an

MTF of 0.6 to 0.9 at the Nyquist frequency. It is important

to note that even though a sensor may have a high

enough sampling frequency for a particular application, the

overall frequency response of the sensor and optics may not

be sufficient for that application!

Photodiode Quantum Efficiency

For a given area, absolute quantum efficiency is defined

as the ratio of the number of photogenerated electrons

captured during an integration period to the number of

impinging photons during that period. Higher values

indicate a more efficient photon conversion process and

hence are more desirable.

Absolute photodiode quantum efficiency is calculated

from the charge-to-voltage, imager responsivity, and

measured active photodiode area. It is calculated over the

entire wavelength range of operation and graphed on a curve

as percent Quantum Efficiency versus Wavelength.

Once the charge-to-voltage, responsivity, and active

photodiode dimensions have all been measured, the absolute

quantum efficiency can be calculated as:

Quantum Efficiency (l) + Responsivity (l) B

B Charge to Voltage B

B Active Photodiode Area

Energy per Photon (l)

where

h @ c

Energy per Photon (l) +

l

and

h @ c + 1.98647E * 25 [J * m]

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KLI−8023

Saturation Voltage

Smear

Smear, also referred to as Photodiode-to-CCD Crosstalk,

The saturated signal level is the output voltage

corresponding to the maximum charge packet the imager

can handle. Adding charge above the saturated level results

in the excess charge “spilling” over into neighboring

photosites or CCD structures. Either the photodiode

capacity or the CCD capacity, with the latter being the most

typical case, can limit the charge capacity. The saturated

signal level is measured by monitoring the dark-to-light

transition between the first-out dark reference pixels and the

first active pixels while the irradiance is slowly increased.

Note that improper settings on either the output gate (OG)

or the reset gate (fR) can have a clipping effect on the output

waveform.

occurs when photogenerated charge diffuses to an adjacent

CCD (such as a transfer register) and is collected, as opposed

to being collected in the photodiode where the photon

absorption occurred. The result of smear is to increase the

background signal within the dark reference pixels and CCD

buffer pixels. This increased background signal reduces the

achievable dynamic range; hence, a high smear value is

undesirable. The further the photodiode array and the CCD

are apart, the less the smear. Contributors to increased smear

are a short photodiode-to-CCD separation and improper

transfer gate clocking levels or timing. Smear is also highly

dependent on incident photon wavelength. In the

application, an IR cut-off filter (~710 nm) is recommended.

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KLI−8023

Physical Description

Pin Description and Device Orientation

SUB

1

2

3

40

39

38

SUB

f1A

SUB

f2A

SUB

4

37

36

35

34

33

32

31

N/C

IG

5

LOGG

LOGB

LS

6

ID

7

LOGR

SUB

TG1

SUB

8

TG2

9

SUB

10

SUB

11

12

30

29

SUB

RD

fR

VSSB

VIDB

13

14

28

27

OG

SUB

VIDG

VSSG

15

16

17

18

19

20

26

25

24

23

22

21

VDD

VIDR

VSSR

SUB

f1B

SUB

f2B

SUB

Figure 3. KLI−8023 Pinout

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KLI−8023

Table 4. PACKAGE PIN DESCRIPTION

1

Name

SUB

f2n

Description

Substrate/Ground

2

Phase 2 CCD Clock (n = A or B)

Substrate/Ground

3

SUB

LOGn

LS

4

Substrate/Ground

5

Substrate/Ground

6

Exposure Control for Channel (n = R, G, B)

Light Shield/Exposure Drain

Transfer Gate 2 Clock

Substrate/Ground

7

8

9

TG2

SUB

fR

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

Substrate/Ground

Reset Clock

VSSn

VIDn

SUB

VIDn

VSSn

SUB

f1n

Ground Reference (n = R, G, B)

Blue Output Video (n = R, G, B)

Substrate/Ground

Blue Output Video (n = R, G, B)

Ground Reference (n = R, G, B)

Substrate/Ground

Phase 1 CCD Clock (n = A or b)

Substrate/Ground

SUB

f2n

Substrate/Ground

Phase 2 CCD Clock (n = A or B)

Substrate/Ground

SUB

VSSn

VIDn

VDD

SUB

OG

Ground Reference (n = R, G, B)

Blue Output Video (n = R, G, B)

Amplifier Supply

Substrate/Ground

Output Gate

RD

Reset Drain

SUB

TG1

SUB

LOGn

ID

Substrate/Ground

Transfer Gate 1

Substrate/Ground

Exposure Control for Channel (n = R, G, B)

Test Input − Input Diode

Test Input − Input Gate

Substrate/Ground

IG

SUB

f1n

Substrate/Ground

Phase 1 CCD Clock (n = A or B)

Substrate/Ground

SUB

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9

KLI−8023

IMAGING PERFORMANCE

Typical Operational Conditions

f

= 1 MHz, AR coverglass, color filters, and an active

CLK

Specifications given under nominally specified operating

conditions for the given mode of operation at 25°C,

load as shown in Figure 4 unless otherwise specified. See

notes on next page for further descriptions.

Table 5. SPECIFICATIONS

Verification

Plan

Description

Symbol

Min.

Nom.

Max.

Units

Notes

HIGH DYNAMIC RANGE MODE (VRD = 15 V, fR (High) = 12 V)

17

Saturation Output Voltage

Output Sensitivity

V

5.2

5.5

14

−

Vp-p

1, 9

Die

SAT

−

18

DV /DN

−

mV/e

Design

O

e

−

18

Saturation Signal Charge

Dynamic Range

N

−

400

87

−

ke

e,SAT

DR

−

dB

V

3

5

Dark Signal Non-Uniformity

DC Gain, Amplifier

DSNU

−

0.006

0.775

0.003

−

0.02

0.825

0.005

−

A

0.725

DC

Dark Current

I

−

pA/pixel

DARK

17

Charge Transfer Efficiency

Lag

CTE, η

0.999995

die

18

L

−

8

−

0.003

11

0.06

13

%

Design

DC Output Offset

V

O,DC

V

9

17

Darkfield Defect, Brightpoint

Brightfield Defect, Dark or Bright

Exposure Control Defects

Dark Def

Bfld Def

Exp Def

−

0

Allowed

12

13

Die

−

0

−

32

11, 14,

15, 16

NORMAL MODE (VRD = 11 V, fR (High) = 6.5 V)

18

Saturation Output Voltage

Saturation Signal Charge

Dynamic Range

V

2.3

−

2.6

200

82

−

Vp-p

1, 9

Design

SAT

−

18

N

ke

DR

78

5.5

−

dB

V

3

9

DC Output Offset

V

ODC

7.75

10

KLI−8023−RAA CONFIGURATION GEN2 COLOR

2

18

Responsivity

Red

Green

R

V/mJ/cm

Design

MAX

−

29

19

18

−

Blue

18

Peak Responsivity Wavelength

lR

nm

Red

Green

Blue

−

650

540

460

−

17

Photoresponse Uniformity,

Low Frequency

PRNU.

Low

−

5

10

%p-p

Die

Photoresponse Uniformity,

Medium Frequency

PRNU.

Medium

−

5

10

Die

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10

KLI−8023

Table 5. SPECIFICATIONS (continued)

Verification

Plan

Description

Symbol

Min.

Nom.

Max.

Units

Notes

KLI−8023−DAA CONFIGURATION GEN1 COLOR (Note 19)

2

18

Responsivity

Red

Green

R

V/mJ/cm

Design

MAX

−

32

20

−

Blue

18

Responsivity Wavelength

lR

nm

Design

Red

Green

Blue

−

650

540

460

−

17

Photoresponse Uniformity,

Low Frequency

PRNU.

Low

−

4

7

%p-p

Die

17

Photoresponse Uniformity,

Medium Frequency

PRNU.

Medium

−

4

7

Die

KLI−8023−AAA, KLI−8023−SAA, AND KLI−8023−MAA CONFIGURATION MONOCHROME (Note 19)

2

18

Responsivity

Monochrome

R

V/mJ/cm

Design

MAX

−

33

−

18

Responsivity Wavelength

Monochrome

lR

nm

Design

−

675

4

−

7

17

Photoresponse Uniformity,

Low Frequency

PRNU.

Low

%p-p

Die

17

Photoresponse Uniformity,

Medium Frequency

PRNU.

Medium

−

4

7

Die

1. Defined as the maximum output level achievable before linearity or PRNU performance is degraded beyond specification.

2. With color filter. Values specified at filter peaks. 50% bandwidth = 30 nm. Color filter arrays become transparent after 710 nm. It is

recommended that a suitable IR cut filter be used to maintain spectral balance and optimal MTF. See Figure 5.

3. As measured at 2 MHz data rate. This device utilizes 2-phase clocking for cancellation of driver displacement currents. Symmetry between

f1 and f2 phases must be maintained to minimize clock noise.

4. Dark current doubles approximately every +8°C.

5. Measured per transfer. For the total line: (0.999995) ⋅ 16044 = 0.9229.

6. Low frequency response is measured across the entire array with a 1,000 pixel-moving window and a 5 pixel median filter evaluated under

a flat field illumination.

7. Medium frequency response is measured across the entire array with a 50 pixel-moving window and a 5 pixel median filter evaluated under

a flat field illumination.

8. High frequency response non-uniformity represents individual pixel defects evaluated under a flat field illumination. An individual pixel value

may deviate above or below the average response for the entire array. Zero individual defects allowed per this specification.

9. Increasing the current load (nominally 4 mA) to improve signal bandwidth will decrease these parameters.

10.If resistive loads are used to set current, the amplifier gain will be reduced, thereby reducing the output sensitivity and net responsivity.

(e.g. with 2.2 kW loads to ground, the sensitivity drops to 12.5 mV per electron).

11. Defective pixels will be separated by at least one non-defective pixel within and across channels.

12.Pixels whose response is greater than the average response by the specified threshold, (16 mV). See Figure 4.

13.Pixels whose response is greater or less than the average response by the specified threshold, ( 10%). See Figure 4.

14.Pixels whose response deviates from the average pixel response by the specified threshold, (4 mV), when operating in exposure control

mode. See Figure 4. If dark pattern correction is used with exposure control, the dark pattern acquisition should be completed with exposure

control actuated. Dark current tends to suppress the magnitude of these defects as observed in typical applications, hence line rate changes

may affect perceived defect magnitude. Note: Zero defects allowed for those pixels whose response deviates from the average pixel

response by a 20 mV threshold.

15.Defect coordinates are available upon request.

16.The quantity and type of defects acceptable for a specific application will be negotiated with each customer.

17.A parameter that is measured on every sensor during production testing.

18.A parameter that is quantified during the design verification activity.

19.Configuration KLI−8023−DAA and KLI−8023−MAA uses Gen1 color filter set and is not recommended for new designs.

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11

KLI−8023

TYPICAL PERFORMANCE CURVES

Defective Pixel Classification

Note 13: Bright

Field Bright Pixel

Note 14: Bright Field

Exposure Control

Bright Defect

Average

Pixel

Note 12: Dark

Field Bright

Pixel

Average

Pixel

Note 14: Bright

Field Exposure

Control Dark

Defect

Note 13: Bright

Field Dark Pixel

Exposure

Figure 4. Illustration of Defect Classifications

35

30

25

20

15

10

5

0

350

400

450

500

550

600

650

700

750

800

850

900

950

1000 1050 1100

Wavelength (nm)

Figure 5. KLI−8023 Typical Responsivity

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12

KLI−8023

KLI−8023 (9 mm) Typical Modulation Transfer Function (MTF)

Unified Aperture and Two-Layer Diffusion Calculation Model

100

95

90

85

80

75

70

65

60

55

50

45

40

35

30

25

20

15

10

5

450 nm

550 nm

650 nm

750 nm

850 nm

0

10

20

30

40

50

60

Spatial Frequency (Cyc/mm)

Figure 6. KLI−8023 Typical Modulation Transfer Function

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0.00

450

500

550

600

650

700

750

800

Wavelength (nm)

Figure 7. KLI−8023 Smear − LDR Operation/1 MHz/355C

fR

= 12 V

HIGH

5.5

5.0

4.5

4.0

3.5

3.0

12.0

12.5

13.0

13.5

VRD (V)

14.0

14.5

15.0

Figure 8. KLI−8023 Typical Saturation Voltage vs. VRD

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13

KLI−8023

70

60

50

40

30

20

10

0

50

100

150

200

Dark Voltage Level (mV)

Figure 9. KLI−8023 Typical Dark Voltage Level vs. Temperature

60

58

56

54

52

50

48

46

44

42

40

0

1

2

3

4

5

6

7

Pixel Frequency (MHz)

Figure 10. KLI−8023 Typical CCD Temperature vs. Operating Frequency

6

Sensor Output

5

Linear

4

3

2

1

0

0.5

1.0

1.5

2.0

2.5

Relative Light Level

Figure 11. KLI−8023 Typical Device Response Linearity

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14

KLI−8023

KLI−8023 Reference Design

The KLI−8023 Reference Design provides a baseline

reference for the design of a KLI−8023 image sensor into

your electronic imaging application. The circuit below uses

inexpensive off-the-shelf components to provide

voltage-translated clock signals and DC bias supplies

required to support the KLI−8023.

8

LS

ID

.1

35

26

.1

Ferrite Bead

VDD

+ 15 V

KLI−8023

IMAGE SENSOR

100 uF

.1

10 uF

.1 uF

29

28

RD

.1

18K

820

OG

10 K

24

VSSR

VSSG

VSSB

MASTER

OSCILLATOR

1N914

or

eqiv

.1

17

.1

+6.8 V

EL7202

13

100

.1

9

EL7202

TG2

TG1

100

32

+15 V

.1

+6.8 V

25

100

34

2N3904

VIDR

VIDG

VIDB

LOGR

LOGG

6

180

Vout

RED

750

74 ACT 11244

1/G

Rd

39

2

f1A

f2A

1A1 1Y1

1A2 1Y2

1A3 1Y3

1A4 1Y4

2/G

+ 15V

PLD

.1

Rd

2A1

2A2

2A3

2A4

2Y 1

2Y 2

2Y 3

2Y 4

16

2N3904

Vout

GREEN

750

+6.8 V

74 ACT 11244

1/G

Rd

19

22

1A1 1Y1

1A2 1Y2

1A3 1Y3

1A4 1Y4

2/G

f1B

f2B

+15 V

Rd

.1

2A1

2A2

2A3

2A4

2Y 1

2Y 2

2Y 3

2Y 4

14

2N3904

Vout

BLUE

+12.0V

750

12

.1

1N914A

fR

MPS 577

1

IG SUB

36

1,3,10 ,11 ,15 ,18 ,20 , 21

,23 ,27 ,30 ,31 ,33 ,38 , 40

33

1K

MPS 3646

1N914A

Figure 12. Reference Design

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15

KLI−8023

REFERENCE DESIGN CIRCUIT OVERVIEW

Programmable Logic

Bias Supplies

See the timing waveform requirements earlier in this

document before programming a logic device.

VDD, RD and OG

VDD and VRD are supplied directly from the 15 V input

power supply and OG is supplied by a voltage divider.

The input power should be sufficiently filtered to prevent

noise from coupling into the output stage of the KLI−8013

through the VDD node. Current spikes in the VRD and VDD

nodes, due to switching of the on-chip reset FET, are

suppressed by the addition of a 0.1 mF decoupling capacitor

to ground at each node. The decoupling capacitors should be

located as close as possible to the pins of the CCD and should

have a solid connection to ground. OG is also decoupled to

suppress voltage spikes the output gate of the device.

The OG node draws negligible current.

Clock Drivers

There are three types of clock drivers (voltage translating

buffers) used in this reference design. The most important

performance consideration is the ability of the clock driver

to drive the capacitive loads presented by the various gates

of the CCD.

Reset Driver

The RESET, (fR), gate presents a small capacitive load

of 100 pF, and requires fast rise and fall times.

The complimentary bipolar switching transistor circuit

shown in Figure 12 provides a low cost solution. The circuit

alternately drives the PNP and NPN transistors into

saturation, which switches the output between VCC and

ground. A 33-W series-damping resistor is used to suppress

ringing.

OG, VSSR, VSSG, VSSB

A forward-biased diode provides an inexpensive and

reliable voltage source for all three VSS nodes.

The switching action of the reset FET of the output stage can

cause voltage spikes to occur on the VSS nodes.

A decoupling capacitor located as close as practical to each

VSS pin, and connected to a solid system ground, will

minimize voltage spiking. In high dynamic range systems,

crosstalk between VSS channels might present a noise

problem. A separate supply for each of the three VSS nodes

will minimize channel crosstalk if it proves to be a problem.

Exposure Control and Transfer Gates

The exposure control gates; LOGR and LOGG, and the

transfer gates; TG1 and TG2 each present a moderate

capacitive load of 500 pF. The Elantec 7202 Dual-Channel

Power MOSFET driver delivers a peak output current of

2 amperes: more than enough to meet the rise and fall

requirements of the LOG and TG gates. Series damping

resistors are used to prevent ringing in the LOGR and LOGG

gates. The transfer gates are connected together and driven

by a single EL7202.

Output Buffers

An emitter follower circuit buffers each output channel.

The emitter follower provides a high impedance load to the

on-chip source follower output stage, and provides low

output impedance for driving the downstream analog signal

processing circuits. A 180-W resistor connected between the

base and emitter of the emitter follower uses the forward

biased base to emitter voltage drop to provide a constant

current load for the on-chip output stage.

CCD Shift Register Driver

The CCD clock phases (f1A, f2A, f1B and f2B) present

a significant load of 3,100 pF per phase. Two 74ACT11244

octal buffers provide an efficient solution. Each clock phase

is driven by four gates connected in parallel to increase

output drive current. The 6.5-volt swing required by the shift

register is obtained by setting VCC to 6.8 V. Series damping

resistors R are used to suppress ringing of the clock signals.

D

Values for R should be varied to eliminate ringing and

D

achieve 50% crossover between each pair of shift register

clocks.

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16

KLI−8023

DEFECT DEFINITIONS

Table 6. OPERATING CONDITION SPECIFICATIONS

(Test Conditions: T = 25°C, f

= 1 MHz, t

= 8.054 ms)

CLK

INT

Field

Dark

Defect Type

Bright

Threshold

Units

mV

%

Notes

20, 21

Number

16.0

10

0

Bright

Bright/Dark

Exposure Control

20, 22

4.0

mV

20, 23, 24

≤ 32

20.Defective pixels will be separated by at least one non-defective pixel within and across channels.

21.Pixels whose response is greater than the average response by the specified threshold. See Figure 13 below.

22.Pixels whose response is greater or less than the average response by the specified threshold. See Figure 13 below.

23.Pixels whose response deviates from the average pixel response by the specified threshold when operating in exposure control mode. See

Figure 13 below.

24.Defect coordinates are available upon request.

Note 3: Bright

Field Bright Pixel

Note 4: Bright Field

Exposure Control

Average

Pixel

Note 2: Dark

Field Bright

Pixel

Bright Defect

Average

Pixel

Note 4: Bright

Note 3: Bright

Field Dark Pixel

Field Exposure

Control Dark

Defect

Exposure

Figure 13. Illustration of Defect Classifications

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17

KLI−8023

OPERATION

Table 7. ABSOLUTE MAXIMUM RATINGS

Description

Gate Pin Voltage

Symbol

Minimum

Maximum

Unit

V

Notes

25, 26

25, 27

25, 28

29

V

GATE

−0.5

−

16

Pin-to-Pin Voltage

V

PIN−PIN

Diode Pin Voltage

V

DIODE

−0.5

−

16

V

Output Bias Current

Output Load Capacitance

CCD Clocking Frequency

I

−10

15

mA

pF

MHz

DD

VID,LOAD

C

−

f

C

−

20

30

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

25.Referenced to substrate voltage.

26.Includes pins: f1n (n = A or B), f2n (n = A or B), TG1, TG2, fR, OG, IG, and LOGn (n = R, G, B).

27.Voltage difference (either polarity) between any two pins.

28.Includes pins: VIDn, VSSn, RD, VDD, LS and ID (n = R, G, B).

29.Care must be taken not to short output pins to ground during operation as this may cause permanent damage to the output structures.

30.Charge transfer efficiency will degrade at frequencies higher than the maximum clocking frequency. VIDn load resistor values may need to

be decreased as well.

31.Noise performance will degrade with increasing temperatures.

32.Long-term storage at the maximum temperature will accelerate color filter degradation.

33.Exceeding the upper limit on output load capacitance will greatly reduce the output frequency response. Thus, direct probing of the output

pins with conventional oscilloscope probes is not recommended.

34.The absolute maximum ratings for the entire table indicate the limits of this device beyond which damage may occur. The Operating ratings

indicate the conditions where the design should operate the device. Operating at or near these ratings do not guarantee specific performance

limits. Guaranteed specifications and test conditions are contained in the Imaging Performance section.

Device Input ESD Protection Circuit (Schematic)

To Device

I/O Pin

Function

V − 20 V

t

SUB

CAUTION: To allow for maximum performance, this device was designed with limited input protection; thus, it is sensitive to electrostatic

induced damage. These devices should be installed in accordance with strict ESD handling procedures!

Figure 14. ESD Protection Circuit

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18

KLI−8023

DC Bias Operating Conditions

Table 8. DC BIAS OPERATING CONDITIONS

Description

Symbol

Minimum

Nominal

Maximum

−

Units

V

Notes

Substrate

V

−

0

SUB

Output Buffer Return

0.5

0.65

11.0

0.75

11.5

15.5

−2

V

VSS

Reset Drain Bias (Normal Mode)

Reset Drain Bias (High DR Mode)

Output Buffer Supply

V

RD

10.5

14.5

−8

V

RD

V

VDD

V

15.0

V

VDD

IDD

Output Bias Current/Channel

Output Gate Bias

I

−4

0.65

15.0

0

mA

V

35

V

OG

0.5

0.75

15.5

−

Light Shield/Drain Bias

Test Pin − Input Gate

V

LS

12.0

−

V

IG

Test Pin − Input Diode

12.0

15.0

15.5

V

ID

35.A current sink must be supplied for each output. Load capacitance should be minimized so as not to limit bandwidth. R serves as the load

X

bias for the on-chip amplifiers. Values of R and R should be chose to optimize performance for a given operating frequency, but R should

X

L

X

not be less than 75 W. Figure 15 below shows one such solution.

Typical Output Bias/Buffer Circuit

V

DD

0.1 mF

2N2369

or Similar*

To Device

Output Pin: VIDn

(Minimize Path Length)

Buffered Output

R

= 180 W*

X

R = 750 W*

L

Figure 15. Typical Output Bias/Buffer Circuit

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19

KLI−8023

AC Operating Conditions

Table 9. AC ELECTRICAL CHARACTERISTICS − AC TIMING REQUIREMENTS

Description

CCD Element Duration

Symbol

1e (= 1/f

Minimum

Nominal

Maximum

Units

Notes

)

167

20

1,000

100

8,054

16,000

1,000

−

ns

ms

ns

1e Count

CLK

H1A/B, H2A/B Rise Time

Line Integration Period

PD−CCD Transfer Period

Transfer Gate 1 Clear

Transfer Gate 2 Clear

Charge Drain Duration

Reset Pulse Duration

Clamp to H2 Delay

t

RISE

1L (= t

)

1.343

2666

167

1,000

20

8,054e Counts

INT

t

16e Counts

PD

t

1e Count

TG1

TG2

t

1e Count

t

38

36

37

DR

t

−

RST

t

6

−

CD

Sample to Reset Edge Delay

t

6

−

SD

36.Minimum values given are for 6 MHz CCD operation.

37.Recommended delays for Correlated Double Sampling (CDS) for output.

38.Minimum value required to ensure proper operation, allowing for on-chip propagation delay.

Table 10. AC ELECTRICAL CHARACTERISTICS − CLOCK LEVEL CONDITIONS FOR OPERATION

Description

Symbol

Minimum

6.25

Nominal

6.5

Maximum

7.0

Units

V

Notes

CCD Readout Clocks High (n = A or B)

CCD Readout Clocks Low (n = A or B)

Transfer Clocks High (n = 1 or 2)

Transfer Clocks Low (n = 1 or 2)

Reset Clock High (Normal Mode)

Reset Clock High (High DR Mode)

Reset Clock Low

V

, V

H2nH

, V

H2nL

H1nH

V

−0.1

0.0

0.1

V

39

H1nL

V

TGnH

6.25

6.5

7.0

V

TGnL

−0.1

0.0

0.1

V

f

V

f

6.25

6.5

7.0

V

RH

11.5

12.0

0.0

12.5

0.1

V

f

−0.1

V

39

40

RL

Exposure Clocks High (n = R, G, B)

Exposure Clocks Low (n = R, G, B)

V

6.25

6.5

7.0

V

LOGnH

V

LOGnL

−0.1

0.0

0.1

V

39, 40

39.Care should be taken to insure that low rail overshoot does not exceed –0.5 VDC. Exceeding this value may result in non-photogenerated

charge being injected into the video signal.

40.Connect pin to ground potential for applications where exposure control is not required.

Table 11. CLOCK LINE CAPACITANCE

Description

Symbol

Minimum

Nominal

Maximum

Units

Notes

CHROMA

Phase 1 Clock Capacitance

Phase 2 Clock Capacitance

Transfer Gate 1 Capacitance

Transfer Gate 2 Capacitance

Exposure Gate Capacitance

Reset Gate Capacitance

C

−

4,180

2,000

925

−

pF

41

f

1

2

C

TG1

TG2

LOG

475

C

190

C

11

f

R

41.This is the total load capacitance per CCD phase. Since the CCDs are driven from both ends of the sensor, the effective load capacitance

per drive pin is approximately half the value listed.

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20

KLI−8023

TIMING

6e 16e

8002e

14e 6e

6e 16e

8002e

14e 6e

f1

f2

6e 16e

TG1

t

INT

TG2

LOGn

t

EXP

DR

Figure 16. Line Timing

First Dark Reference

Pixel Data Valid

1e

f1

f2

TG1

TG2

t

PD

t

TG1

TG2

t

DR

LOGn

Figure 17. Photodiode-to-CCD Transfer

1e

f2

t

RISE

V

DARK

V

FEEDTHRU

VIDn

V

SAT

t

SD

t

RST

t

CD

fR

Clamp*

t

CLP

Sample*

t

SPL

* Required for Correlated Double Sampling

Figure 18. Output Timing

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21

KLI−8023

STORAGE AND HANDLING

Table 12. STORAGE CONDITIONS

Description

Symbol

Minimum

Maximum

Unit

°C

Notes

42

Storage Temperature

T

ST

−25

0

80

70

Operating Temperature

T

OP

°C

43

42.Long-term storage toward the maximum temperature may accelerate color filter degradation.

43.Noise performance will degrade with increasing temperatures.

For information on ESD and cover glass care and

cleanliness, please download the Image Sensor Handling

and Best Practices Application Note (AN52561/D) from

www.onsemi.com.

For quality and reliability information, please download

the Quality & Reliability Handbook (HBD851/D) from

www.onsemi.com.

For information on device numbering and ordering codes,

please download the Device Nomenclature technical note

(TND310/D) from www.onsemi.com.

For information on soldering recommendations, please

download the Soldering and Mounting Techniques

Reference

www.onsemi.com.

Manual

(SOLDERRM/D)

from

For information on Standard terms and Conditions of

Sale, please download Terms and Conditions from

www.onsemi.com.

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22

KLI−8023

MECHANICAL INFORMATION

Completed Assembly

Figure 19. Completed Assembly Drawing (1/2)

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23

KLI−8023

Figure 20. Completed Assembly Drawing (2/2)

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24

KLI−8023

Cover Glass

Maximum Reflectance Allowed (Two-Sided)

2.40

2.20

2.00

1.80

1.60

1.40

1.20

1.00

0.80

0.60

0.40

0.20

Reflectance (Two-Sided)

650

0.00

400

450

500

550

600

700

Wavelength (nm)

Figure 21. Two-Sided Multilayer Anti-Reflective Cover Glass Specification (MAR)

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型号：	KLI-8023-SAA-ED-AA
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