LC72725KV-TLM-E [ONSEMI]

RDS 解调器;


型号：	LC72725KV-TLM-E
厂家：	ONSEMI
描述：	RDS 解调器 PC 光电二极管商用集成电路
文件：	总9页 (文件大小：95K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Ordering number : ENA0503A

LC72725KV

CMOS IC

http://onsemi.com

RDS(RBDS) Demodulation IC

Overview

The LC72725KV is IC that implement the signal processing required by the European Broadcasting Union RDS

(Radio Data System) standard and by the US NRSC (National Radio System Committee) RBDS (Radio Broadcast

Data System) standard. This IC include band-pass filter, demodulator, and data buffer on chip. RDS data can be read

out from this on-chip memory by external clock input in slave operation mode.

Functions

• Bandpass filter: Switched capacitor filter (SCF)

• RDS Demodulation: 57KHz carrier and RDS data clock regeneration, biphase decode, differential decode.

• Buffer: 128 bit (about 100ms) can be restored in the on-chip data buffer RAM.

• Data output: Master or slave output mode can be selected.

• RDS-ID: Detect RDS signal which can be reset by RST signal input.

• Standby control: Crystal oscillator can be stopped.

• Fully adjustment free

• Low Voltage

Specifications

Absolute Maximum Ratings at Ta = 25°C, V d = V a = 0V

Parameter

Symbol

Pin Name

Conditions

Ratings

-0.3 to +6.5

Unit

Maximum supply voltage

Maximum input voltage

max

d, V a *

DD DD

a≤V d+0.3V

TEST, MODE, XIN, RDCL, RST

-0.3 to V d+0.3

max

MPXIN, CIN

-0.3 to V a+0.3

max

Maximum output voltage

Maximum output current

1 max

RDS-ID(READY)

XOUT, RDDA, RDCL

FLOUT

-0.3 to +6.5

2 max

3 max

-0.3 to V d+0.3

-0.3 to V a+0.3

1 max

XOUT, FLOUT, RDDA, RDCL

RDS-ID(READY)

+2.0

+8.0

2 max

* V a≤V d+0.3V

DD DD

Continued on next page.

Semiconductor Components Industries, LLC, 2013

June, 2013

60612HK 20060913-S00003/83006HKIM 20060822-S00002,20060823-S00002 No.A0503-1/9

LC72725KV

Continued from preceding page.

Parameter

Symbol

Pd max

Topr1

Topr2

Tstg

Pin Name

Conditions

Ratings

Unit

°C

Allowable power dissipation

Operating temperature

Ta≤85°C

100

= 2.7V to 5.5V

= 3.0V to 5.5V

-20 to +70

-40 to +85

-40 to +125

°C

Storage temperature

°C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating

Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

Allowable Operating Ranges at Ta = -20 to +70°C, V d = V a = 0V, V d = V a = 2.7V to 5.5V

SS SS DD DD

Ta = -40 to +85°C, V d = V a = 0V, V d = V a = 3.0V to 5.5V

Ratings

Parameter

Supply voltage

Symbol

Pin Name

Conditions

unit

min

typ

max

d, V

Ta = -20 to +70°C

Ta = -40 to +85°C

2.7

5.5

6.5

3.0

Input high-level voltage

TEST, MODE, RST

RDCL

0.7V

Input low-level voltage

Output voltage

TEST, MODE, RST,

RDCL

0.3V

RDDA, RDCL

RDS-ID(READY)

MPXIN

6.5

Input amplitude

f = 57 2kHz

1.6

mVrms

VXIN

Xtal

XIN

400

1500

100

Guaranteed crystal

oscillator frequencies

Crystal oscillator operating

range

XIN, XOUT

CI≤120Ω

4.332

MHz

ppm

TXtal

XIN, XOUT

Fo = 4.332MHz

RDCL setup time

tCS

tCH

tCL

tDC

tRC

tRL

RDCL, RDDA

RDCL

0.75

μs

RDCL high-level time

RDCL low-level time

Data output time

RDCL

RDCL, RDDA

RDCL, READY

READY

0.75

107

READY output time

READY low-level time

No.A0503-2/9

LC72725KV

Electrical Characteristics for the Allowable Operating Ranges

Ratings

typ

Parameter

Symbol

Pin Name

Conditions

unit

min

max

Input resistance

Rmpxin

Rcin

MPXIN-V

f = 57kHz

100

kΩ

CIN-V

XIN

f = 57kHz

100

1.0

Internal feedback

resistance

MΩ

Center frequency

BW-3dB

Gain

Att1

FLOUT

56.5

57.0

3.0

57.5

kHz

-3dB band width

Gain

2.5

3.5

MPXIN-FLOUT

FLOUT

f = 57kHz

Stop band attenuation

Δf = 7kHz

Att2

FLOUT

F<45kHz, f>70kHz

F<20kHz

Att3

FLOUT

Reference voltage output

Hysteresis

Vref

a = 3V

1.5

VHIS

TEST, MODE, RST,

RDCL

0.1V

Output low-level voltage

RDDA, RDCL

I = 2mA

I = 8mA

I = 2mA

0.4

RDS-ID(READY)

RDDA, RDCL

Output high-level voltage

Input high-level current

d-0.4

2.0

TEST, MODE, RST,

V = 6.5V

5.0

μA

RDCL

XIN

V = V

Input low-level current

TEST, MODE, RST,

V = 0V

5.0

RDCL

XIN

V = 0V

2.0

Output off leakage

current

IOFF

RDS-ID(READY)

= 6.5V

5.0

Current drain

d+V

DD DD

(V d = V a = 3V)

DD DD

Package Dimensions

unit : mm (typ)

3178B

5.2

0.65

0.15

(0.33)

0.22

SANYO : SSOP16(225mil)

No.A0503-3/9

LC72725KV

Pin Assignment

16 15 14 13 12 11 10

LC72725KV

Top view

Block Diagram

VREF

FLOUT

CIN

+3V

CLOCK

RECOVERY

(1187.5Hz)

PLL

(57kHz)

REFERENCE

VOLTAGE

VREF

57kHz

MPXIN

BPF

(SCF)

DATA

DECODER

RDDA

RDCL

SMOOTHING

FILTER

ANTIALIASING

FILTER

RAM

(128bit)

MODE

RST

CLK(4.332MHz)

OSC

RDS-ID

DETECT

RDS-ID/

READY

TEST

XIN

XOUT

No.A0503-4/9

LC72725KV

Pin Descriptions

Pin No.

Pin Name

I/O

Function

Pin Circuit

VREF

Output

Reference voltage output (Vdda/2)

MPXIN

Input

Baseband (multiplexed) signal input

FLOUT

Output

Input

Subcarrier output (filter output)

CIN

Subcarrier input (comparator input)

VREF

Analog system power supply (+3V)

Analog system ground

XOUT

XIN

Output

Input

Crystal oscillator output (4.332MHz)

Crystal oscillator input

(external reference signal input)

XIN

XOUT

TEST

MODE

RST

Test input

Read out mode (0:master, 1:slave)

RDS-ID/RAM reset (active high)

RDDA

Output

RDS data output

RDCL

I/O

RDS clock output (master mode) /

RDS read out clock input (slave mode)

RDS-ID/

READY

Output

RDS reliability data output

(High:data with high RDS reliability

Low: data with low RDS reliability)

READY output (active high)

Digital system power supply (+3V)

Digital system ground

No.A0503-5/9

LC72725KV

Input/Output Data Format

TEST

MODE

Circuit Operation Mode

Master read out mode

Slave read out mode

RDCL Pin

RDS-ID/READY Pin

Clock output

RDS-ID output

Clock input

READY output

Standby mode (crystal oscillator stopped)

IC test mode which is not available to user applications.

RST Pin

RST = 0

RST = 1

Normal operation

RDS-ID • demodulation circuit clear + READY • memory clear (when slave mode)

RDS-ID/READY Pin

Master mode

Slave mode

RDS-ID output (Active-high)

READY output (Active-high)

Note: RDS-ID(READY) pin is an n-channel open-drain output, and requires an external pull-up resistor to output data.

RDCL/RDDA Output Timing in Master Mode

421μs 421μs

Tp1

RDCL output

RDDA output

Tp2

17μs

RDS-ID Output Timing

RDS-ID

RDCL

High/Low High/Low High/Low High/Low High/Low High/Low High/Low

RDDA

Note: RDS-ID is High: data with high RDS reliability, Low: data with low RDS reliability

No.A0503-6/9

LC72725KV

RST Operation in Master Mode

Tp3≥250ns

RST

RDSdetection circuit output

(IC internal)

RDCL

RDDA

Note: RDCL and RDDA outputs keep high level after input of RST until RDS detection circuit output is

detected.

RDCL Operation in Slave Mode

tRH

tRC

tCS

tCH

tCL

tDC

READY

RDCL

tCS

RDDA

Ratings

typ

Parameter

RDCL setup time

Symbol

Pin Name

Conditions

unit

min

max

tCS

tCH

tCL

tDC

tRC

tRH

RDCL,RDDA

RDCL

μs

RDCL high-level time

RDCL low-level time

Data output time

0.75

RDCL

RDCL,RDDA

RDCL,READY

READY

0.75

READY output time

READY high-level time

0.75

107

No.A0503-7/9

LC72725KV

Notes: 1. RDCL input must be started after READY signal goes high. When READY signal is low, RDCL must be

low level.

2. READY status must be checked after tRC time from RDCL is set low. If the READY status is high, then next

read cycle can be continued. If the READY status is low, next RDCL clock input must be stopped.

3. If the above condition is satisfied, RDS data (RDDA) can be read out at both rising and falling edge of RDCL.

4. READY signal goes low after the last data is read out from on-chip memory. If one RDS data is stored in the

memory, READY signal goes high again.

5. When the reception channel is changed, a memory and READY reset must be applied using RST input. If a

reset is not applied, reception data from the previous channel may remain in memory. If RST input is applied,

reception data is not stored in memory until the first RDS-ID is detected, and READY output goes high after

the first RDS-ID is detected. After the first RDS-ID is detected, reception data is stored even if RDS-ID is not

detected.

6. The readout mode may be switched between master and slave modes during readout.

Applications must observe the following points to assure data continuity during this operation.

1) Data acquisition timing in master made

Data must be read on the falling edge of RDCL

2) Timing of the switch from master mode to slave mode

After the RDCL output goes low and the RDDA data has been acquired, the application must set MODE

high immediately.

Then, the microcontroller starts output by setting the RDCL signal low.

The microcontroller RDCL output must start within 840μs (tms) after RDCL went low.

In this case, if the last data read in master mode was data item n, then data starting with item n+1

will be written to memory.

3) Timing of the switch from slave mode to master mode

After all data has been read from memory and READY has gone high, the application must then wait

until READY goes low once again the next time (timing A in the figure), immediately read out one bit of

data and input the RDCL clock.

Then, at the point READY goes high, the microcontroller must terminate RDCL output and then set

MODE low.

The application must switch MODE to low within 840μs (tms) after READY goes low (timing A in the

figure).

tms

RDCL (microcontroller status)

RDCL (IC status)

INPUT

OUTPUT

INPUT

OUTPUT

INPUT

OUTPUT

undefined

RDCL

MODE

READY

RDDA

tsm

Timing A

n-2

n-1

n+1

m+1

m+2

No.A0503-8/9

LC72725KV

Sample Application Connection Circuit (for master mode operation)

10kΩ

RDCL

RST

RDSID/READY

RDDA

RDSID/READY

RDCL

RST

RDDA

VREF

XOUT

XIN

10μF

4.332MHz

MPXIN

22pF

330pF

22pF

V d

0.1μF

MODE

TEST

FLOUT

CIN

560pF

Note: If the RST pin is unused, it must be connected to ground.

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www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no

warranty, representation or guarantee regarding the suitabilityof its products for any particular purpose, nor does SCILLC assume any liability arising out of the

application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental

damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual

performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical

experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use

as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in

which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for

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PS No.A0503-9/9

LC72725KV-TLM-E [ONSEMI]

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