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LC72725KVS-TLM-H [ONSEMI]

RDS (RBDS) Demodulation IC;
LC72725KVS-TLM-H
型号： LC72725KVS-TLM-H
厂家： ONSEMI    ONSEMI
描述：

RDS (RBDS) Demodulation IC

光电二极管 商用集成电路
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Ordering number : ENA1744  
LC72725KVS  
CMOS IC  
http://onsemi.com  
RDS(RBDS) Demodulation IC  
Overview  
The LC72725KVS is ICs that implement the signal processing required by the European Broadcasting Union RDS  
(Radio Data System) standard and by the US NRSC (National Radio System Committee) RBDS (Radio Broadcast  
Data System) standard. These ICs include band-pass filter, demodulator,and data buffer on chip. RDS data can be  
read out from this on-chip memory by external clock input in slave operation mode.  
Functions  
• Bandpass filter  
• RDS Demodulation  
• Buffer  
: Switched capacitor filter (SCF)  
: 57KHz carrier and RDS data clock regeneration, biphase decode, differential decode.  
: 128 bit (about 100ms) can be restored in the on-chip data buffer.  
: Master or slave output mode can be selected.  
• Data output  
• RDS-ID  
: Detect RDS signal which can be reset by RST signal input.  
: Crystal oscillator can be stopped.  
• Standby control  
• Fully adjustment free  
• Low Voltage  
Semiconductor Components Industries, LLC, 2013  
June, 2013  
60910HKIM 20100427-S00009 No.A1744-1/9  
LC72725KVS  
Specifications  
Absolute Maximum Ratings at Ta = 25°C, V d = V a = 0V  
SS  
SS  
Parameter  
Symbol  
max  
Pin Name  
Conditions  
Ratings  
-0.3 to +6.5  
Unit  
V
Maximum supply voltage  
Maximum input voltage  
V
V
d, V  
a
V
a≤V d+0.3V  
DD  
DD DD  
DD  
DD  
V
V
V
V
V
V
I
1 max  
2 max  
3 max  
TEST, MODE, RST  
XIN, RDCL  
-0.3 to +6.5  
V
IN  
IN  
IN  
-0.3 to V d+0.3  
DD  
V
MPXIN, CIN  
-0.3 to V a+0.3  
DD  
V
Maximum output voltage  
Maximum output current  
1 max  
2 max  
3 max  
RDS-ID(READY)  
XOUT, RDDA, RDCL  
FLOUT  
-0.3 to +6.5  
V
O
O
O
-0.3 to V d+0.3  
DD  
V
-0.3 to V a+0.3  
DD  
V
1 max  
XOUT, FLOUT, RDDA, RDCL  
RDS-ID(READY)  
+3.0  
+20.0  
mA  
mA  
mW  
°C  
°C  
O
I
2 max  
O
Allowable power dissipation  
Operating temperature  
Storage temperature  
Pd max  
Topr  
(Ta≤85°C)  
= 3.0V to 5.5V  
100  
V
-40 to +85  
-40 to +125  
DD  
Tstg  
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating  
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.  
Allowable Operating Ranges at Ta = -40 to +85°C, V d = V a = 0V, V d = V a = 3.0V to 5.5V  
SS  
SS  
DD  
DD  
Ratings  
typ  
Parameter  
Symbol  
Pin Name  
Conditions  
unit  
min  
max  
Supply voltage  
V
V
d, V  
a
Ta = -40 to +85°C  
3.0  
5.5  
6.5  
d
V
V
V
DD  
DD DD  
Input high-level voltage  
V
V
V
1
TEST, MODE, RST  
RDCL  
0.7V  
0.7V  
d
d
IH  
IH  
IL  
DD  
2
V
DD  
DD  
Input low-level voltage  
Output voltage  
TEST, MODE, RST,  
RDCL  
0
0.3V  
V
d
V
DD  
V
V
V
1
RDDA, RDCL  
d
V
O
DD  
2
RDS-ID(READY)  
MPXIN  
6.5  
50  
V
O
Input amplitude  
f = 57 2kHz  
1.6  
mVrms  
mVrms  
IN  
VXIN  
Xtal  
XIN  
400  
1500  
100  
Guaranteed crystal  
oscillator frequencies  
Crystal oscillator operating  
range  
XIN, XOUT  
CI≤120Ω  
4.332  
MHz  
ppm  
TXtal  
XIN, XOUT  
Fo = 4.332MHz  
RDCL setup time  
tCS  
tCH  
tCL  
tDC  
tRC  
tRL  
RDCL, RDDA  
RDCL  
0
0.75  
0.75  
μs  
μs  
μs  
μs  
μs  
ms  
RDCL high-level time  
RDCL low-level time  
Data output time  
RDCL  
RDCL, RDDA  
RDCL, READY  
READY  
0.75  
0.75  
107  
READY output time  
READY low-level time  
No.A1744-2/9  
LC72725KVS  
Electrical Characteristics at Ta = -40 to +85°C, V d = V a = 0V, V d = V a = 3.0V to 5.5V  
SS  
SS  
DD  
DD  
Ratings  
typ  
Parameter  
Symbol  
Rf  
Pin Name  
Conditions  
unit  
min  
max  
Internal feedback  
resistance  
XIN  
1.0  
MΩ  
Hysteresis  
VHIS  
TEST, MODE, RST,  
RDCL  
0.1V  
d
V
DD  
Output low-level voltage  
V
V
1
2
RDDA, RDCL  
I = 2mA  
0.4  
0.4  
V
V
V
OL  
RDS-ID(READY)  
RDDA, RDCL  
I = 8mA  
I = -2mA  
OL  
Output high-level voltage  
Input high-level current  
V
OH  
V
d-0.54  
2.0  
DD  
I
1
TEST, MODE, RST,  
V = 6.5V  
I
IH  
5.0  
11  
μA  
μA  
μA  
μA  
μA  
RDCL  
XIN  
I
2
V = V  
d
IH  
I
DD  
Input low-level current  
I
1
TEST, MODE, RST,  
V = 0V  
I
IL  
5.0  
11  
RDCL  
XIN  
I
2
V = 0V  
I
2.0  
IL  
Output off leakage  
current  
IOFF  
RDS-ID(READY)  
V
= 6.5V  
O
5.0  
Current drain  
I
V
d+V  
a
V
d+V  
a
DD  
DD DD  
DD  
DD  
1.5  
2.5  
3.5  
mA  
(V d = V a = 3.3V)  
DD DD  
Bandpass Filter Characteristics at Ta = 25°C, V d = V a = 0V, V d = V a = 3.0V to 5.5V  
SS  
SS  
DD  
DD  
Ratings  
typ  
Parameter  
Symbol  
Pin Name  
Conditions  
unit  
min  
max  
Input resistance  
Rmpxin  
Rcin  
fc  
MPXIN-V  
a
f = 57kHz  
100  
kΩ  
kΩ  
kHz  
kHz  
dB  
dB  
dB  
dB  
V
SS  
a
CIN-V  
f = 57kHz  
100  
57.0  
3.0  
SS  
Center frequency  
-3dB band width  
Gain  
FLOUT  
FLOUT  
56.5  
2.5  
28  
57.5  
3.5  
34  
BW-3dB  
Gain  
Att1  
MPXIN-FLOUT  
FLOUT  
f = 57kHz  
31  
Stop band attenuation  
Δf = 7kHz  
f<45kHz, f>70kHz  
f<20kHz  
30  
Att2  
FLOUT  
40  
Att3  
FLOUT  
50  
Reference voltage output  
Vref  
Vref  
V
a = 3V  
DD  
1.5  
No.A1744-3/9  
LC72725KVS  
Package Dimensions  
unit : mm (typ)  
Pin Assignment  
3178B  
5.2  
16  
9
16 15 14 13 12 11 10  
9
8
LC72725KV  
1
2
3
4
5
6
7
1
8
0.65  
0.15  
Top view  
(0.33)  
0.22  
SSOP16(225mil)  
Block Diagram  
VREF  
FLOUT  
CIN  
+3V  
+3V  
V
a
a
DD  
V
V
d
DD  
CLOCK  
RECOVERY  
(1187.5Hz)  
PLL  
(57kHz)  
REFERENCE  
VOLTAGE  
V
d
SS  
SS  
VREF  
57kHz  
MPXIN  
BPF  
(SCF)  
DATA  
DECODER  
RDDA  
RDCL  
SMOOTHING  
FILTER  
ANTIALIASING  
FILTER  
RAM  
(128bit)  
MODE  
RST  
CLK(4.332MHz)  
OSC  
RDS-ID  
DETECT  
RDS-ID/  
READY  
TEST  
TEST  
XIN  
XOUT  
No.A1744-4/9  
LC72725KVS  
Pin Descriptions  
Pin No.  
Pin Name  
I/O  
Function  
Pin Circuit  
3
VREF  
Output  
Reference voltage output (V a/2)  
DD  
V
a
DD  
V
a
SS  
4
MPXIN  
Input  
Baseband (multiplexed) signal input  
V
a
DD  
V
a
SS  
7
8
FLOUT  
Output  
Input  
Subcarrier output (filter output)  
CIN  
Subcarrier input (comparator input)  
V
a
DD  
V
a
SS  
VREF  
5
6
V
a
a
-
-
Analog system power supply (+3V)  
Analog system ground  
-
-
DD  
V
SS  
14  
13  
XOUT  
XIN  
Output  
Input  
Crystal oscillator output (4.332MHz)  
V
d
DD  
Crystal oscillator input  
(external reference signal input)  
XIN  
V
d
SS  
XOUT  
9
TEST  
MODE  
RST  
Test input  
S
10  
15  
Read out mode (0:master, 1:slave)  
RDS-ID/RAM reset (active high)  
V
d
SS  
2
RDDA  
Output  
RDS data output  
V
d
DD  
V
d
SS  
16  
RDCL  
I/O  
RDS clock output (master mode) /  
V
d
DD  
RDS read out clock input (slave mode)  
V
d
SS  
S
1
RDS-ID/  
READY  
Output  
RDS reliability data output  
(High:data with high RDS reliability  
Low: data with low RDS reliability)  
READY output (active high)  
V
d
SS  
12  
11  
V
d
d
-
-
Digital system power supply (+3V)  
Digital system ground  
-
DD  
V
-
SS  
No.A1744-5/9  
LC72725KVS  
Input/Output Data Format  
TEST  
MODE  
Circuit Operation Mode  
Master read out mode  
Slave read out mode  
RDCL Pin  
RDS-ID/READY Pin  
0
0
1
1
0
1
0
1
Clock output  
RDS-ID output  
Clock input  
READY output  
Standby mode (crystal oscillator stopped)  
-
-
-
-
IC test mode which is not available to user applications.  
RST Pin  
RST = 0  
RST = 1  
Normal operation  
RDS-ID • demodulation circuit clear + READY • memory clear (when slave mode)  
RDS-ID/READY Pin  
Master mode  
Slave mode  
RDS-ID output (Active-high)  
READY output (Active-high)  
Note: RDS-ID(READY) pin is an n-channel open-drain output, and requires an external pull-up resistor to output data.  
RDCL/RDDA Output Timing in Master Mode  
421μs 421μs  
Tp1  
RDCL output  
RDDA output  
Tp21  
17μs  
17μs  
RDS-ID Output Timing  
RDS-ID  
RDCL  
High/Low High/Low High/Low High/Low High/Low High/Low High/Low  
RDDA  
Note: RDS-ID is High: data with high RDS reliability, Low: data with low RDS reliability  
No.A1744-6/9  
LC72725KVS  
RST Operation in Master Mode  
Tp3≥250ns  
RST  
RDSdetection circuit output  
(IC internal)  
RDCL  
RDDA  
Note: RDCL and RDDA outputs keep high level after input of RST until RDS detection circuit  
output is detected.  
RDCL Operation in Slave Mode  
tRH  
tRC  
tCS  
tCH  
tCL  
tDC  
READY  
RDCL  
tCS  
RDDA  
Ratings  
typ  
Parameter  
RDCL setup time  
Symbol  
Pin Name  
Conditions  
unit  
min  
max  
tCS  
tCH  
tCL  
tDC  
tRC  
tRH  
RDCL,RDDA  
RDCL  
0
μs  
μs  
μs  
μs  
μs  
ms  
RDCL high-level time  
RDCL low-level time  
Data output time  
0.75  
0.75  
RDCL  
RDCL,RDDA  
RDCL,READY  
READY  
0.75  
READY output time  
READY high-level time  
0.75  
107  
No.A1744-7/9  
LC72725KVS  
Notes: 1. RDCL input must be started after READY signal goes high. When READY signal is low, RDCL must be  
low level.  
2. READY status must be checked after tRC time from RDCL is set low. If the READY status is high, then next  
read cycle can be continued. If the READY status is low, next RDCL clock input must be stopped.  
3. If the above condition is satisfied, RDS data (RDDA) can be read out at both rising and falling edge of RDCL.  
4. READY signal goes low after the last data is read out from on-chip memory. If one RDS data is stored in the  
memory, READY signal goes high again.  
5. When the reception channel is changed, a memory and READY reset must be applied using RST input. If a  
reset is not applied, reception data from the previous channel may remain in memory. If RST input is applied,  
reception data is not stored in memory until the first RDS-ID is detected, and READY output goes high after  
the first RDS-ID is detected. After the first RDS-ID is detected, reception data is stored even if RDS-ID is not  
detected.  
6. The readout mode may be switched between master and slave modes during readout.  
Applications must observe the following points to assure data continuity during this operation.  
1) Data acquisition timing in master made  
Data must be read on the falling edge of RDCL  
2) Timing of the switch from master mode to slave mode  
After the RDCL output goes low and the RDDA data has been acquired, the application must set MODE  
high immediately.  
Then, the microcontroller starts output by setting the RDCL signal low.  
The microcontroller RDCL output must start within 840μs (tms) after RDCL went low.  
In this case, if the last data read in master mode was data item n, then data starting with item n+1  
will be written to memory.  
3) Timing of the switch from slave mode to master mode  
After all data has been read from memory and READY has gone high, the application must then wait  
until READY goes low once again the next time (timing A in the figure), immediately read out one bit of  
data and input the RDCL clock.  
Then, at the point READY goes high, the microcontroller must terminate RDCL output and then set  
MODE low.  
The application must switch MODE to low within 840μs (tms) after READY goes low (timing A in the  
figure).  
tms  
RDCL (microcontroller status)  
RDCL (IC status)  
INPUT  
OUTPUT  
INPUT  
OUTPUT  
INPUT  
OUTPUT  
undefined  
RDCL  
MODE  
READY  
RDDA  
tsm  
Timing A  
n
n-2  
n-1  
n+1  
m+1  
m+2  
m
No.A1744-8/9  
LC72725KVS  
Sample Application Connection Circuit (for master mode operation)  
V
d
DD  
10kΩ  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
RDCL  
RST  
RDSID/READY  
RDDA  
RDSID/READY  
RDDA  
RDCL  
RST  
XOUT  
VREF  
+
10μF  
4.332MHz  
V
a
SS  
MPXIN  
XIN  
MPXIN  
22pF  
330pF  
22pF  
V d  
SS  
V
d
V
a
DD  
V
d
DD  
V
d
DD  
SS  
V
V
a
DD  
0.1μF  
0.1μF  
V
d
a
SS  
SS  
V
a
SS  
V
d
SS  
10  
9
MODE  
TEST  
FLOUT  
CIN  
560pF  
V
d
SS  
Note: If the RST pin is unused, it must be connected to ground.  
ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number  
of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at  
www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no  
warranty, representation or guarantee regarding the suitabilityof its products for any particular purpose, nor does SCILLC assume any liability arising out of the  
application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental  
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual  
performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical  
experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use  
as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in  
which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for  
any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors  
harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or  
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part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.  
PS No.A1744-9/9  

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