LC74731WS-9818-E [ONSEMI]
On-Screen Display Controller;
| 型号： | LC74731WS-9818-E |
| 厂家： | 
ONSEMI |
| 描述： | On-Screen Display Controller |
| 文件： | 总39页 (文件大小：339K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LC74731W
LC74732W
www.onsemi.com
CMOS LSI
On-Screen Display Controller
Overview
The LC74731W and LC74732W are on-screen display CMOS ICs that
display characters and patterns on a TV screen under the control of a
microcontroller. These ICs display 16 16-dot characters and up to 12 lines
of text with 24 characters per line.
Features
SPQFP64 10x10 / SQFP64
Text structure : 12 lines 24 characters (Up to 288 characters)
Character format : 16 16 dots
Character display clock frequency : about 9 MHz
Character sizes : Four sizes each in the horizontal and vertical directions with the size set in line units.
Number of characters supported :
LC74731W : 256 (internal)
LC74732W : 512 (internal)
Up to 8192 using an external ROM (for Japanese)
[Reference] JIS X0298 (1990) : 6877 characters
JIS level 1 kanji : 2965 characters
JIS level 2 kanji : 3388 characters
Special characters : 524 characters
Display start positions : 128 positions each in the horizontal and vertical directions
Blinking, reverse video, reversed blinking, and character outlining : May be specified in individual character units.
Blinking types : Two types with periods of about 1.0 and about 0.5 seconds.
Blanking : The whole font area (16 16 dots) can be blanked in line units
(Four types : no blanking, character size blanking, character plus outlining size blanking, and whole area up to
adjacent character blanking)
Line spacing control : Zero to seven scan lines, in line units
Character color : Eight colors in character units (in internal synchronization mode) : 2 fsc and 4 fsc
(Black, red, green, yellow, blue, magenta, cyan, and white)
Character background color : Eight colors (in internal synchronization mode) : 2 fsc and 4 fsc
(Black, red, green, yellow, blue, magenta, cyan, and transparent)
Screen background color : Eight colors (in internal synchronization mode) : 2 fsc and 4 fsc
(Black, red, green, yellow, blue, magenta, cyan, and white)
External control inputs : Serial interface with an 8-bit data size.
Built-in sync separator circuit
Video outputs : NTSC, PAL, PALM, PALN, NTSC 4.43, and PAL 60 composite video signal outputs
Supports Y/C input
ORDERING INFORMATION
See detailed ordering and shipping information on page 39 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
March 2015 - Rev. 1
1
Publication Order Number :
LC74731W_32W/D
LC74731W, LC74732W
Pin Assignment
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VSS
1
1
A6
48
47
46
45
44
43
42
41
40
39
38
37
36
35
XTALin
XTALout
CTRL1
2
A7
3
A8
4
A9
OSCin
5
A10
A11
A12
A13
A14
A15
A16
A17
VDD
OSCout
6
MUTE
7
CDLR
8
SYNCjdg/Rout
CHARA/Gout
BLANK/Bout
IEOUT/BLKout
OUTMOD
CS
9
10
11
12
13
14
15
16
1
RST
SIN
SEPin
SEPout
(V)
34
33
SCLK
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
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LC74731W, LC74732W
Pin Functions
Pin No.
Pin
Function
Description
1
2
3
V
SS1
Ground
Ground connection. (Digital system ground)
Xtalin
Connections for the crystal element and capacitors that form the internal sync signal generating
crystal oscillator. Xtalin can also be used to input an external clock signal. (2fsc or 4fsc)
Crystal oscillator connections
Xtalout
Switches the crystal oscillator Selects external clock input mode or crystal oscillator mode. Low: crystal oscillator mode, high:
4
CTRL1
input
external clock input mode.
5
6
OSCin
LC oscillator connections
Connections for the coil and capacitor that form the character output dot clock generation oscillator.
OSCout
This is an active-low input with hysteresis characteristics (MORE+).
When low, the
CVout, Yout, and Cout outputs are set to either,
7
MUTE
CDLR
Muting control input
(1) CSYNC,
(2) PE
CSYNC,
PE,
PE, or
PE.
In the initial state, (1) is selected. This setting is switched by commands.
Background color phase
adjustment
8
9
Connection for the resistor used to adjust the background color phase
Outputs the result of the judgment as to whether or not the external sync signal is present.
SYNCJDG External sync signal judgment A high level is output when a sync signal is present.
/Rout
output (Rout output)
The dot clock (LC oscillator) is output when RST is low.
(The IC can be set up to not output this signal during resets by commands.)
Character output
(Gout output)
10
11
12
CHARA/Gout
Character signal output
BLANK/Bout Blank output (Bout output)
Blank signal output pin
Internal/external output
IEout/BLKout
Internal synchronization (high)/external synchronization (low) state output pin
(BLKout output)
Switches between output from pins 9 to 12 and input to pin 32.
Low: normal operation, high: RGB output supported
13
14
OUTMOD
CS
Output switching input
Enable input
Serial data input enable
Serial data input is enabled when low.
more+ (Hysteresis input characteristics)
Serial data input
more+ (Hysteresis input characteristics)
15
16
SIN
Data input
Clock input
Serial data input clock input
more+ (Hysteresis input characteristics)
SCLK
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
VDD
2
Power supply
Composite video signal level adjustment power supply. (Analog system power supply)
Color (C) signal output
COUT
NC
Color signal output
This pin must either be left open or connected to ground.
Color (C) signal input
CIN
Color signal input
CBIAS
NC
Chrominance bias output
Chrominance signal bias level output
This pin must be either left open or connected to ground.
Luminance signal (Y) output
YOUT
NC
Luminance signal output
This pin must be either left open or connected to ground.
Luminance signal (Y) input
YIN
Luminance signal input
Ground
V
SS2
Ground
CVOUT
NC
Video signal output
Composite video signal output
This pin must either be left open or connected to ground.
Composite video signal input
CVIN
Video signal input
CVCR
HFTin
SYNin
SEPout
Video signal input
SECAM chrominance signal input
Halftone signal input
Sync separator circuit input
Halftone signal input
Video signal input to the internal sync separator circuit
Composite sync signal output Composite sync signal output from the internal sync separator circuit
Vertical sync signal input
Vertical sync signal input
34
SEPin
RST
MORE+ (Hysteresis input characteristics)
System reset input
Reset input
35
36
A built-in pull-up resistor can be included in this pin’s input circuit. (Hysteresis input characteristics)
V
DD1
Power supply (+5 V)
Power supply (+5 V: digital system power supply)
Continued on next page.
3/39
LC74731W, LC74732W
Continued from preceding page.
Pin No.
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Pin
A17
A16
A15
A14
A13
A12
A11
A10
A9
Function
Address output 17
Address output 16
Address output 15
Address output 14
Address output 13
Address output 12
Address output 11
Address output 10
Address output 9
Address output 8
Address output 7
Address output 6
Address output 5
Address output 4
Address output 3
Address output 2
Address output 1
Address output 0
Output enable
Description
ROM address output 17
ROM address output 16
ROM address output 15
ROM address output 14
ROM address output 13
ROM address output 12
ROM address output 11
ROM address output 10
ROM address output 9
ROM address output 8
ROM address output 7
ROM address output 6
ROM address output 5
ROM address output 4
ROM address output 3
ROM address output 2
ROM address output 1
ROM address output 0
A8
A7
A6
A5
A4
A3
A2
A1
A0
OE
CE
D7
ROM output enable output. This is an active-low output.
ROM chip enable output. This is an active-low output.
Chip enable
Data input 7
ROM data input 7. MORE+ (Hysteresis input characteristics)
ROM data input 6. MORE+ (Hysteresis input characteristics)
ROM data input 5. MORE+ (Hysteresis input characteristics)
ROM data input 4. MORE+ (Hysteresis input characteristics)
ROM data input 3. MORE+ (Hysteresis input characteristics)
ROM data input 2. MORE+ (Hysteresis input characteristics)
ROM data input 1. MORE+ (Hysteresis input characteristics)
ROM data input 0. MORE+ (Hysteresis input characteristics)
D6
Data input 6
D5
Data input 5
D4
Data input 4
D3
Data input 3
D2
Data input 2
D1
Data input 1
D0
Data input 0
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LC74731W, LC74732W
Specifications
Maximum Ratings at Ta = 25°C
Ratings
Parameter
Supply voltage
Symbol
Conditions
Unit
min
max
VDD
VIN
VDD1 and VDD
2
VSS – 0.3
VSS – 0.3
VSS + 6.5
VDD1 + 0.3
V
V
Input voltage
All input pins
SYNCJDG, BLANK, CHARA, SEPOUT, A0 to A17,
CE, and OE
Output voltage
VOUT
V
SS – 0.3
VDD1 + 0.3
V
Allowable power dissipation
Operating temperature
Storage temperature
Pdmax
Topr
—
–30
–40
275
+70
mW
°C
Tstg
+125
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
Recommended Operating Conditions
Ratings
Parameter
Symbol
Conditions
Unit
min
typ
max
V
V
DD1
DD2
VDD
VDD
VDD
VDD
1
2
1
2
4.5
4.5
2.7
2.7
5.0
5.0
5.0
5.0
—
5.5
6.5
5.5
6.5
5.5
V
V
V
V
V
V
V
V
V
V
V
Supply voltage
VDD
1
Supply voltage
[Only for RGB output]
V
DD2
V
IH1
IH2
IH3
IH4
CS, SIN, SCLK, SEPIN, and MUTE
RST
0.8 VDD
0.8 VDD
0.7 VDD
0.8 VDD
1
1
1
1
V
—
V
V
1 + 0.3
1 + 0.3
5.5
DD
High-level input voltage
V
V
CTRL1 and OUTMOD
D0 to D7
—
DD
—
V
V
V
IL1
IL2
IL3
RST, CS, SIN, SCLK, SEPIN, and MUTE
CTRL1 and OUTMOD
D0 to D7
VSS – 0.3
VSS – 0.3
VSS – 0.3
—
0.2 VDD
1
1
1
Low-level input voltage
Pull-up resistor
—
0.3 VDD
0.2 VDD
—
RST, CS, SIN, SCLK, and MUTE (when the pull-up
resistor option is specified)
RPU
25
50
90
—
kΩ
VIN
1
2
CVIN and CVCR
SYNIN
VDD1 = 5 V
—
2.0
2.0
Vp-p
Composite video signal input
voltage
VIN
VDD1 = 5 V
1.5
2.5 Vp-p
XtalIN (when an external clock input is used)
fin = 2 fsc, 4 fsc
Input voltage
VIN3
VDD1 = 5 V
—
—
5.0 Vp-p
The XtalIN and XtalOUT oscillator pins (2 fsc: NTSC)
The XtalIN and XtalOUT oscillator pins (4 fsc: NTSC)
The XtalIN and XtalOUT oscillator pins (2 fsc: PAL)
The XtalIN and XtalOUT oscillator pins (4 fsc: PAL)
The OSCin and OSCout oscillator pins (LC oscillator)
7.159
14.318
8.867
17.734
10
MHz
MHz
FOSC1
Oscillator frequency
—
—
—
—
—
—
MHz
MHz
MHz
FOSC2
Note: If the Xtalin pin is used in clock input mode, applications must take adequate input noise prevention and reduction measures.
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
5/39
LC74731W, LC74732W
Electrical Characteristics at Ta = –30 to +70°C, V 1 = 5 V unless otherwise specified.
DD
Ratings
typ
Parameter
Symbol
Pin
Conditions
Unit
min
max
Input off leakage current
Output off leakage current
Ileak1
Ileak2
CVIN, CVCR, CIN, and YIN
CVOUT, COUT, and YOUT
—
—
—
1
1
µA
µA
—
SYNCJDG, SETPOUT,
BLANK, CHARA, and IEOUT
VDD1 = 5.5 to 4.5 V
IOH = –1.0 mA
VOH11
VOH12
VOH21
VOH22
VOL11
VOL12
VOL21
VOL22
IIH
0.9 VDD1
—
—
—
—
—
V
V
SYNCJDG, SETPOUT,
BLANK, CHARA, and IEOUT
VDD1 = 4.4 to 2.7 V
IOH = –0.5 mA
0.9 VDD1
—
—
—
—
—
—
—
—
—
High-level output voltage
VDD1 = 5.5 to 4.5 V
A0 to A17, OE, and CE
A0 to A17, OE, and CE
0.9 VDD1
V
I
OH = –1.0 mA
VDD1 = 4.4 to 2.7 V
OH = –0.5 mA
VDD1 = 5.5 to 4.5 V
OL = 1.0 mA
0.9 VDD1
V
I
SYNCJDG, SEPOUT,
BLANK, CHARA, and IEOUT
—
—
—
—
—
–1
0.1 VDD1
0.1 VDD1
0.1 VDD1
0.1 VDD1
1
V
I
SYNCJDG, SEPOUT,
BLANK, CHARA, and IEOUT
VDD1 = 4.4 to 2.7 V
IOL = 0.5 mA
V
Low-level output voltage
VDD1 = 5.5 to 4.5 V
A0 to A17, OE, and CE
A0 to A17, OE, and CE
V
I
OL = 1.0 mA
VDD1 = 4.4 to 2.7 V
OL = 0.5 mA
V
I
RST, CS, SIN, SCLK, CTRL1,
MUTE, and OUTMOD
V
IN = VDD
1
µA
µA
Input current
CS, SIN, SCLK, CTRL1, and
OUTMOD
IIL
V
IN = VSS
1
—
All outputs: open
Xtal: 17.734 MHz
LC: 10 MHz
I
DD1
VDD
1
2
—
—
40
20
mA
mA
Operating current drain
IDD
2
VDD
VDD2 = 5 V
Continued on next page.
6/39
LC74731W, LC74732W
Continued from preceding page.
Ratings
typ
Parameter
Symbol
VSN
Pin
Conditions
Unit
V
min
max
(1)
(2)
(3)
(1)
(2)
(3)
(1)
(2)
(3)
(1)
(2)
(3)
(1)
(2)
(3)
(1)
(2)
(3)
(1)
(2)
(3)
(1)
(2)
(3)
(1)
(2)
(3)
(1)
(2)
(3)
(1)
(2)
(3)
(1)
(2)
(3)
(1)
(2)
(3)
0.80
1.00
1.40
1.37
1.57
1.97
1.07
1.27
1.67
1.67
1.87
1.27
1.23
1.43
1.83
2.37
2.57
2.97
1.52
1.72
2.12
2.01
2.21
2.61
1.50
1.70
2.10
1.80
2.00
2.40
2.08
2.28
2.68
2.65
2.85
3.25
2.23
2.43
2.83
SYNC level
Pedestal level
VPD
VCBL
VCBH
V
V
V
V
V
V
V
V
V
V
V
V
Color burst low level
Color burst high level
Background color 1 low level
Background color 1 high level
Background color 2 low level
Background color 2 high level
Outlining level 1
CVOUT
VRSL1
(1): When SYNC – LEVEL = 0.8 V VDD1 = 5.0 V
(2): When SYNC – LEVEL = 1.0 V VDD2 = 5.0 V
(3): When SYNC – LEVEL = 1.4 V
VRSH
1
VRSL2
VRSH
2
VBK
VBK
VBK
1
Outlining level 2
2
Outlining level 3
3
Character level 1
VCHA
1
Character level 3
VCHA
3
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
7/39
LC74731W, LC74732W
OSD Write (See figure 1.) at Ta = –30 to +70°C, V 1 = 5 ± 0.5 V
DD
Ratings
typ
—
Parameter
Minimum input pulse width
Data setup time
Symbol
w (sclk) SCLK
Conditions
Unit
min
200
max
t
—
ns
µs
ns
ns
µs
ns
µs
µs
t
w (cs)
su (cs)
su (sin) SIN
CS (the period when CS is high)
1
200
200
2
—
—
—
—
—
—
—
—
t
CS
—
t
—
t
h (cs)
CS
—
Data hold time
t
h (sin)
tword
twt
SIN
200
4.2
1
—
The time to write 8 bits of data
RAM data write time
—
One word write time
—
Supplementary Materials
tw(cs)
CS
tsu(cs)
tw(sclk) tw(sclk)
th(cs)
SCLK
tsu(sin)
th(sin)
SIN
CS
tword
twt
SCLK
0
1
5
6
7
0
1
4
5
6
7
Figure 1 OSD Serial Data Input Timing
8/39
LC74731W, LC74732W
System Block Diagram
D e c o d e r
9/39
LC74731W, LC74732W
Display Control Commands
Display control commands have an 8-bit format and are transferred using the serial input function. Commands consist of
a command identification code in the first byte and command data in the following bytes.
Display Control Commands
First byte
Command identification code
Second byte
Data
Command
Data
7
6
5
4
3
2
1
0
7
0
6
0
5
0
4
3
2
1
0
COMMAND0
(Write address setup)
1
0
0
0
V3
V2
V1
V0
H4
H3
H2
H1
H0
at2
0
at1
0
CB2 CB1 CB0 CC2 CC1 CC0
COMMAND1 (Character write)
1
0
0
1
IR
SD2 SD1 SD0
0
C12 C11 C10
C4 C3 C2
C9
C1
C8
C0
C7
C6
C5
COMMAND20
(Vertical display start position)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
RRM1 RRM0
0
0
0
0
VP6 VP5 VP4 VP3 VP2 VP1 VP0
HP6 HP5 HP4 HP3 HP2 HP1 HP0
COMMAND21
(Horizontal display start position)
0
0
0
0
COMMAND22
(Character size)
SRM
LSZUD
0
0
0
0
VS1 VS0 HS1 HS0
COMMAND23
(Character size - in line units)
LSZB5 LSZA4 LSZ93 LSZ82 LSZ71 LSZ60
COMMAND3
(Display control)
TSTMOD RAMERS OSCSTP SYSRST
LCSOFF XN53S BLKSEL
LC
FS
BK
DSPON
0
0
0
0
0
0
0
0
0
0
0
0
0
0
COMMAND4
(Display control)
NP2 NP1 NP0
I/N
HLFINT BCL1 BCL0 CB
PH2 PH1 PH0
COMMAND50
(Sync signal detection 1)
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
DISLIN I/E
MUT1 MUT0
EVEBSS LSPSS
RSLG1 RSLG0
RN2 RN1 RN0 SN3 SN2 SN1 SN0
COMMAND51
(Sync signal detection 2)
O
CINSEL
0
RNE0 SJN3 SJN2 SJN1 SJC1 SJC0
COMMAND52
(Display control)
CINCTL
CTL3
VNPSEL VSPSEL MSKERS MSKSEL EGLSEL
COMMAND53
(Display control)
SPOSEL PALAL4 IHSEL
VSSEL HSSEL
COMMAND60
(Outlining setting)
0
0
0
0
0
0
BRM
LFCUD
GRM
LGYUD
LRM
BXBLV1 BXBLV0 BXWLV1 BXWLV0 ATSEL
BLK1
BLK0
COOMAND61
(Outlining setting - in line units)
0
O
0
0
0
0
LFCB5 LFCA4 LFC93 LFC82 LFC71 LFC60
COMMAND62
(Line spacing)
BXC1 GS1 GS0 GY2 GY1 GY0
LGYB5 LGYA4 LGY93 LGY82 LGY71 LGY60
BKLC1 BKLC0 CHLC1 CHLC0 RSLC1 RSLC0
LCLB5 LCLA4 LCL93 LCL82 LCL71 LCL60
LHTB5 LHTA4 LHT93 LHT82 LHT71 LHT60
COMMAND63
(Line spacing - in line units)
COMMAND70
(Display level)
COMMAND71
(Display level - in line units)
LCLUD
COMMAND72
(Halftone - in line units)
LHTDAT LHTUD
COMMAND73
(RGB control)
0
0
DASSS GBSEL OUTSEL HSPSW XONSS BLK01
BLK00
Note that when the display character data write command (COMMAND1) is written, tthese ICs lock into the display character data write mode, and another
first byte cannot be written.
When the CS pin is set high, the these ICs are set to the COMMAND0 (display memory write address setup mode) state.
10/39
LC74731W, LC74732W
COMMAND0 (Display memory write address setup command)
• First byte
Content
DA0 to 7
Register
Notes
State
Function
Command 0 identification code
7
6
5
4
—
—
—
—
1
0
0
0
0
1
0
1
0
1
0
1
Display memory write address setup
Display memory line address (0 to B (hexadecimal))
3
2
1
0
V3
V2
V1
V0
• Second byte
Content
Function
DA0 to 7
Register
Notes
State
7
6
5
—
—
—
0
0
0
0
1
0
1
0
1
0
1
0
1
Second byte identification code
Display memory line address (0 to 17 (hexadecimal))
4
3
2
1
0
H4
H3
H2
H1
H0
Note that all registers are set to 0 when these ICs are reset by the RST pin.
11/39
LC74731W, LC74732W
COMMAND1 (Display character data write setup command)
• First byte
Content
DA0 to 7
Register
Notes
State
Function
7
6
5
4
—
—
—
—
1
0
0
1
0
1
0
1
0
1
0
1
Note that when this command is input, the
LC74731W/74732W lock into the display character
data write mode until the CS pin is set high.
Command 1 identification code
Display character data write settings
Internal ROM
Switching between internal and external ROM
Character frame specification
3
2
1
0
IR
External ROM
White-on-black (convex) display
Black-on-white (concave) display
Character frame start: off
Character frame start: on
Character frame stop: off
Character frame stop: on
SD2
SD1
SD0
• Second byte (1)
Content
Function
DA0 to 7
Register
Notes
State
0
Character attribute 2: off
(Character frame upper side: off)
Character attribute 2: on
(Character frame upper side: on)
Character attribute 1: off
(Character frame lower side: off)
Character attribute 1: on
(Character frame lower side: on)
Blinking specification
Selected by COM60 second byte and ATSEL.
7
at2
1
0
1
Reverse video specification
Selected by COM60 second byte and ATSEL.
6
at1
0
1
0
1
0
cb2
( B
cb1
G
0
cb0 Character background color
R )
Character background color specification
5
4
cb2
cb1
0
0
0
1
0
1
0
1
0
1
Black
0
Red
0
1
Green
Yellow
Blue
0
1
1
0
3
cb0
1
1
0
Magenta
Cyan
1
1
1
1
Transparent
0
1
0
1
0
cc2
cc1
G
0
cc0 Character color
R )
Character color specification
2
1
cc2
cc1
( B
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
Black
Red
0
1
Green
Yellow
Blue
1
0
0
cc0
1
0
Magenta
Cyan
1
1
White
12/39
LC74731W, LC74732W
• Second byte (2)
Content
DA0 to 7
Register
Notes
State
Function
7
6
5
—
—
—
0
0
0
0
1
0
1
0
1
0
1
0
1
Character code (00xx to 1Fxx (hexadecimal))
External ROM upper address
4
3
2
1
0
c12
c11
c10
c09
c08
Note that all registers are set to 0 when these ICs are reset by the RST pin.
• Second byte (3)
Content
DA0 to 7
Register
c07
Notes
State
0
Function
Character code (00 to FF (hexadecimal))
FE (hexadecimal): Space character
External ROM lower address
Internal ROM address
7
6
5
4
3
2
1
0
1
0
FF (hexadecimal): Transparent space character
c06
1
0
c05
1
0
c04
1
0
c03
1
0
c02
1
0
c01
1
0
c00
1
Note that all registers are set to 0 when these ICs are reset by the RST pin.
Continuous mode (cleared by setting CS high) operates as follows according to IR.
When internal ROM is specified: 1-1
When external ROM is specified: 1-1
1-2-1
1-2-1
1-2-2
1-2-2
1-2-3
1-2-3
1-2-3
1-2-2
1-2-3
1-2-3
1-2-3
1-2-2
1-2-3
13/39
LC74731W, LC74732W
COMMAND20 (Vertical display start position setup command)
• First byte
Content
DA0 to 7
Register
Notes
State
Function
Command 2 identification code
7
6
5
4
3
2
—
—
—
—
—
—
1
0
1
0
0
0
0
1
0
Vertical display position and vertical direction character size
settings
Extended command 0 identification code
RRM1
RRM0
Continuous RAM write mode specification
1
RRM1
0
0
1
1
0
1
0
1
Initial value (depends on IR)
1-2-1
1-2-2
1-2-3
1-2-2
1-2-3
Fixed
1-2-3 Fixed
Fixed
0
RRM0
1
• Second byte
Content
DA0 to 7
Register
Notes
State
0
Function
Second byte identification bit
7
6
—
0
If VS is the vertical display start position then:
VP6
(MSB)
The vertical display start position is set by the 7 bits
VP0 to VP6.
1
6
VS = α + H × ( 2 ∑ 2n V P n )
0
The weight of bit 1 is 2H.
n=0
5
4
3
2
1
0
VP5
VP4
VP3
VP2
VP1
1
H: the horizontal synchronization pulse period
α = 20H (525H systems)
= 25H (625H systems)
0
1
0
HSYNC
1
0
VS
1
0
1
HS
Character display area
0
VP0
(LSB)
1
14/39
LC74731W, LC74732W
COMMAND21 (Horizontal display start position setup command)
• First byte
Content
DA0 to 7
Register
Notes
State
Function
Command 2 identification code
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
1
0
1
0
0
1
0
0
Horizontal display position setup and horizontal direction
character size settings
Extended command 1 identification code
• Second byte
Content
Function
DA0 to 7
Register
Notes
State
0
7
6
—
Second byte identification bit
If HS is the horizontal start position then:
0
The horizontal display start position is set by the 7
bits HP0 to HP6.
HP6
(MSB)
1
6
HS =Tc × ( 2∑ 2 n H P n )
0
The weight of bit 1 is 2Tc.
n=0
5
4
3
2
1
0
HP5
HP4
HP3
HP2
HP1
1
0
Tc: Period of the oscillator connected to OSCIN/OSCOUT in
operating mode.
1
0
1
0
1
0
1
0
HP0
(LSB)
1
Note that all registers are set to 0 when these ICs are reset by the RST pin.
15/39
LC74731W, LC74732W
COMMAND22 (Character size setting command)
• First byte
Content
Function
DA0 to 7
Register
Notes
State
7
6
5
4
3
2
1
—
—
—
—
—
—
—
1
0
1
0
1
0
0
0
1
Command 2 identification code
Horizontal display position setup and horizontal direction
character size settings
Extended command 2 identification code
Continuous mode: off
Continuous mode: on
Character size continuous mode specification
0
SRM
• Second byte
Content
Function
DA0 to 7
Register
Notes
State
7
6
5
4
—
—
—
—
0
0
0
0
0
1
0
Second byte identification bit
VS1
VS0
0
Character size
Vertical direction character size, in line units
Horizontal direction character size, in line units
3
2
1
0
VS1
VS0
HS1
HS0
0
0
1×
2×
3×
4×
1
1
0
1
1
1
0
1
0
HS1
0
HS0 Character size
0
1
0
1
1×
2×
3×
4×
0
1
1
1
Note that all registers are set to 0 when these ICs are reset by the RST pin.
16/39
LC74731W, LC74732W
COMMAND23 (Character size and line setup command)
• First byte
Content
Function
DA0 to 7
Register
Notes
State
7
6
5
4
3
2
1
—
—
—
—
—
—
—
1
0
1
0
1
1
0
0
1
Command 2 identification code
Horizontal display position setup and horizontal direction
character size settings
Extended command 3 identification code
Lower lines: 0 to 5 (hexadecimal)
Upper lines: 6 to B (hexadecimal)
Upper/lower line specification
0
LSZUD
• Second byte
Content
Function
DA0 to 7
Register
Notes
State
7
6
—
—
0
0
0
1
0
1
0
1
0
1
0
1
0
1
Second byte identification bit
Line 6 (line 12) specification: off
Line 6 (line 12) specification: on
Line 5 (line 11) specification: off
Line 5 (line 11) specification: on
Line 4 (line 10) specification: off
Line 4 (line 10) specification: on
Line 3 (line 9) specification: off
Line 3 (line 9) specification: on
Line 2 (line 8) specification: off
Line 2 (line 8) specification: on
Line 1 (line 7) specification: off
Line 1 (line 7) specification: on
The line shown in parentheses is specified when
LSZUD is 1.
5
4
3
2
1
0
LSZB5
LSZA4
LSZ93
LSZ82
LSZ71
LSZ60
Note that all registers are set to 0 when these ICs are reset by the RST pin.
17/39
LC74731W, LC74732W
COMMAND3 (Display control setup command)
• First byte
Content
Function
DA0 to 7
Register
Notes
State
7
6
5
4
—
—
—
—
1
0
1
1
0
1
0
1
0
1
0
1
Command 3 identification code
Display character data write settings
Normal operating mode
Test mode
This bit must always be 0.
3
2
1
0
TSTMOD
RAMERS
OSCSTP
SYSRST
The RAM erase operation takes about 500 µs. (It
must be executed in the DSPOFF state.)
This setting is valid in external synchronization
mode when character display is off.
Erase display RAM (sets the data to FF (hexadecimal))
Do not stop the crystal and LC oscillator circuits.
Stop the crystal and LC oscillator circuits.
The reset occurs when the CS pin is low, and is
cleared when CS is set high.
Reset all registers. This turns the display off.
• Second byte
Content
Function
DA0 to 7
Register
Notes
State
0
7
6
—
Second byte identification bit
Normal operation
0
Switches the LC oscillator STOP control
Switches the crystal oscillator capability
LCSOFF
1
LC oscillator STOP: Disabled
Normal
0
5
4
3
2
1
0
XN53S
BLKSEL
LC
1
Switching
0
Character display area
Video display area
Specifies the character size that fills the whole
character area.
1
0
The LC oscillator is used as the dot clock.
The crystal oscillator is used as the dot clock.
Crystal oscillator frequency: 2 fsc
Crystal oscillator frequency: 4 fsc
Blinking period: 0.5 s
Selects the dot clock used for character display in
the horizontal direction.
1
0
Sets the crystal oscillator frequency.
FS
1
0
Switches the blinking period.
BK
1
Blinking period: 1 s
0
Character display: off
DSPON
1
Character display: on
Note that all registers are set to 0 when these ICs are reset by the RST pin.
18/39
LC74731W, LC74732W
COMMAND4 (Display control setup command)
• First byte
Content
Function
DA0 to 7
Register
Notes
State
7
6
5
4
—
—
—
—
1
1
0
0
0
1
0
1
0
1
Command 4 identification code
Display control settings
NP2
NP1
0
NP0 Signal format
Switches the signal format
3
2
NP2
NP1
0
0
1
0
1
0
1
NTSC
0
0
PAL-M
PAL
0
1
0
1
PAL-N
NTSC4.43
PAL60
1
0
NP0
I/N
1
0
1
0
0
1
Interlaced
Switches between interlaced and noninterlaced
Noninterlaced
• Second byte
Content
Function
DA0 to 7
Register
Notes
State
7
6
—
0
0
1
0
1
0
Second byte identification bit
Normal mode
HLFINT
Semi-internal synchronization mode
BCL1 BCL0
Only valid in internal synchronization mode.
5
4
BCL1
BCL0
0
0
1
1
0
1
0
1
Background color shown
No background color (RSL1)
No background color (CBH)
No background color (RSH1)
1
0
1
0
1
0
1
0
The color burst signal is output.
Only valid when BCL is high.
Background color specification
3
2
1
CB
Color burst signal output is stopped.
PH2
B
0
PH1
G
0
PH0 Background color
R
PH2
PH1
0
1
0
1
0
1
0
1
Black (RSLx)
Red
0
0
0
1
Green
0
1
Yellow
1
0
Blue
0
PH0
1
1
0
Magenta
Cyan
1
1
1
1
White (RSHx)
Note that all registers are set to 0 when these ICs are reset by the RST pin.
19/39
LC74731W, LC74732W
COMMAND50 (Sync signal detection 1 setup command)
• First byte
Content
Function
DA0 to 7
Register
Notes
State
7
6
5
4
3
2
—
—
—
—
—
—
1
1
0
1
0
0
0
1
0
1
Command 5 identification code
Sync signal control settings
Extended command 0 identification code
12 lines
Switches the number of lines displayed.
1
0
DISLIN
I/E
10 lines
External synchronization
Internal synchronization
Switches between internal and external
synchronization
• Second byte
Content
Function
DA0 to 7
Register
Notes
State
0
7
6
—
Second byte identification bit
0
RN2
RN1
RN0 Number of times HSYNC detected
External sync signal detection control
Recognition of the transition from the no signal
state to the signal present state.
Sets the sampling period in which the sync signal
can be detected continuously in the horizontal sync
signal period (1H).
RN2
1
0
0
0
1
0
0
1
0
0
1
0
0
0 times (32 times)
4 times (64 times)
8 times (128 times)
16 times (256 times)
0
5
4
3
2
1
0
RN1
RN0
SN3
SN2
SN1
SN0
1
0
The values in parentheses apply when RNE0
(COM51) is 1.
1
0
SN3 SN2 SN1 SN0 Number of times HSYNC detected
External sync signal detection control
Recognition of the transition from the signal
present state to the no signal state.
Sets the sampling period time in which the sync
signal cannot be detected continuously in the
horizontal sync signal period (1H).
1
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
Not detected
32 times
0
1
64 times
0
128 times
256 times
1
0
1
Note that all registers are set to 0 when these ICs are reset by the RST pin.
20/39
LC74731W, LC74732W
COMMAND51 (Sync signal detection 2 setup command)
• First byte
Content
Function
DA0 to 7
Register
Notes
State
7
6
5
4
3
2
—
—
—
—
—
—
1
1
0
1
0
1
0
1
0
1
Command 5 identification code
Display control settings
Extended command 1 identification code
MUT1 MUT0 Output
Video signal output muting function selection
Valid when the MUTE pin is low.
1
0
MUT1
MUT0
0
0
1
0
1
0
CSYNC
PE
A0-17 “Z”
• Second byte
Content
Function
DA0 to 7
Register
Notes
State
7
6
—
—
0
0
Second byte identification bit
Changes the judgment criterion values for sync
signal recognition for the no signal to signal
present transition. (COM50)
Sync signal no signal to signal present discrimination - Normal
values
0
1
5
RNE0
Sync signal no signal to signal present discrimination - Values
shown in parentheses
0
1
0
1
0
SJNS3 SJNS2 SJNS1
Times
None
4
Noise ignoring circuit setting for sync signal
recognition for the no signal to signal present
transition
4
3
SJNS3
SJNS2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
If more than the number of horizontal signals
shown at the left are input during a 1H period, the
circuit recognizes a no signal state.
8
16
32
2
SJNS1
64
1
128
256
0
1
0
1
SJCS1 SJCS0
PAL
NTSC
Synchronization discrimination
1
0
SJCS1
SJCS0
0
0
1
0
1
0
677 ns (1/3)
903 ns (1/4)
450 ns (1/2)
558 ns (1/2)
838 ns (1/3)
1117 ns (1/4)
Selects the clock used to delimit the HSYNI signal.
Note that all registers are set to 0 when these ICs are reset by the RST pin.
21/39
LC74731W, LC74732W
COMMAND52 (Display control setup command)
• First byte
Content
Function
DA0 to 7
Register
Notes
State
7
6
5
4
3
2
—
—
—
—
—
—
1
1
0
1
1
0
0
1
0
1
Command 5 identification code
Display control settings
Extended command 2 identification code
Normal
Switches the ENBVI signal
LCSTOP control signal
1
0
EVEBSS
LSPSS
Always high
Normal
HT12 “on” HT34 “off”
• Second byte
Content
Function
DA0 to 7
Register
Notes
State
0
7
6
—
Second byte identification bit
0
Blank area (the logical OR of the character and outlining signals) Switches the CVCR on state signal
Video signal display area
CINSEL
1
0
CVCR: off
CVCR on/off switching
5
4
3
2
1
0
CINCTL
VNPSEL
VSPSEL
MSKERS
MSKSEL
EGL
1
CVCR: on
0
V signal falling edges detected
V signal rising edges detected
VSEP: About 8.9 µs (NTSC)
VSEP: About 17.8 µs (NTSC)
Mask enabled
Switches the V signal acquisition polarity when
external mode/internal V separation is used
1
0
Switches the internal vertical separation time
Clears the HSYNC and VSYNC masks
Switches the VSYNC mask
1
0
1
Mask disabled
0
3H (NTSC)
1
20H (NTSC)
0
Outlining level 0 only (VBK0)
Two-stage outlining level (VBK0, VBK1)
Switches the outlining level (Only valid when BLK0
is 0 and BLK1 is 1.)
1
Note that all registers are set to 0 when these ICs are reset by the RST pin.
22/39
LC74731W, LC74732W
COMMAND53 (Display control setup command)
• First byte
Content
Function
DA0 to 7
Register
Notes
State
7
6
5
4
3
2
—
—
—
—
—
—
1
1
0
1
1
1
0
1
0
1
Command 5 identification code
Display control settings
Extended command 3 identification code
RSLG1 RSLG0
Switches the screen background color level
1
0
RSLG1
RDLG0
0
0
1
0
1
0
NO1
NO2
NO3
RS1
RS2
RS3
• Second byte
Content
Function
DA0 to 7
Register
Notes
State
7
6
—
—
0
0
0
1
0
1
0
1
0
1
0
1
0
1
Second byte identification bit
Internal vertical separation circuit
External input
Switches the VSYNC signal input
Switches the SEPout pin output
5
4
3
2
1
0
CTL3
SP0SEL
PALAL4
IHSEL
CSYNC (sync separator output)
Halftone output
Normal
Always use 4 fsc timing (PAL)
SYNin pin input signal
SEPin pin input signal
Negative polarity
Switches the internal vertical separation input
signal
Switches the SEPin input polarity
VSSEL
HSSEL
Positive polarity
Negative polarity
Switches the SYNin input polarity (Invalid for
CVIDEO input)
Positive polarity
Note that all registers are set to 0 when these ICs are reset by the RST pin.
SYnin: CVIDEO (Built-in sync separator circuit)
SEPin: None (internal vertical separation)
SYNin: HSYNC
SEPin: VSYNC
or
:VSYNC
SYNin: HD
SYNin: CSYNC (internal vertical separation)
SEPin: None
SEPin: CSYNC (internal vertical separation)
23/39
LC74731W, LC74732W
COMMAND60 (Outlining control setup command)
• First byte
Content
Function
DA0 to 7
Register
Notes
State
7
6
5
4
3
2
1
—
—
—
—
—
—
—
1
1
1
0
0
0
0
0
1
Command 6 identification code
Display control settings
Extended command 0 identification code
Normal mode
Specifies continuous mode
0
BRM
Continuous mode
• Second byte
Content
Function
DA0 to 7
Register
Notes
State
7
6
—
0
0
1
0
1
0
1
0
1
0
1
0
1
0
Second byte identification bit
BXBLV1 BXBLV0
Character frame - black level specification
In line units
BXBLV1
0
0
1
0
1
0
NO1
NO2
NO3
BK1
BK2
BK3
5
4
3
2
1
BXBLV0
BXWLV1
BXWLV0
ATSEL
BXWLV1 BXWLV0
Character frame - white level specification
In line units
0
0
1
0
1
0
NO1
NO2
NO3
CHA1
CHA2
CHA3
Reverse video, blinking
Character frame specified
Setup for the at1 and at2 function
In line units
BLK1
BLK0
Mode
Outlining mode specification
In line units
BLK1
0
0
1
1
0
1
0
1
Normal
Character size
Outlining size
Full area size
0
BLK0
1
Note that all registers are set to 0 when these ICs are reset by the RST pin.
24/39
LC74731W, LC74732W
COMMAND61 (Outlining control and line specification setup command)
• First byte
Content
DA0 to 7
Register
Notes
State
Function
Command 6 identification code
7
6
5
4
3
2
1
—
—
—
—
—
—
—
1
1
1
0
0
1
0
0
1
Display control settings
Extended command 1 identification code
Lower lines (0 to 5 (hexadecimal))
Upper lines (6 to B (hexadecimal))
Outlining control line specification
0
LFCUD
• Second byte
Content
Function
DA0 to 7
Register
Notes
State
7
6
—
—
0
0
0
1
0
1
0
1
0
1
0
1
0
1
Second byte identification bit
Line 6 (line 12) setting: off
Line 6 (line 12) setting: on
Line 5 (line 11) setting: off
Line 5 (line 11) setting: on
Line 4 (line 10) setting: off
Line 4 (line 10) setting: on
Line 3 (line 9) setting: off
Line 3 (line 9) setting: on
Line 2 (line 8) setting: off
Line 2 (line 8) setting: on
Line 1 (line 7) setting: off
Line 1 (line 7) setting: on
Outlining line setting
5
4
3
2
1
0
LFCB5
LFCA4
LFC93
LFC82
LFC71
LFC60
The values in parentheses apply when LFCUD is 1.
Note that all registers are set to 0 when these ICs are reset by the RST pin.
25/39
LC74731W, LC74732W
COMMAND62 (Line spacing control setup command)
• First byte
Content
Function
DA0 to 7
Register
Notes
State
7
6
5
4
3
2
1
—
—
—
—
—
—
—
1
1
1
0
1
0
0
0
1
Command 6 identification code
Display control settings
Extended command 2 identification code
Normal mode
Continuous mode specification
0
GRM
Continuous mode
• Second byte
Content
Function
DA0 to 7
Register
Notes
State
7
6
—
—
0
0
0
1
0
1
0
Second byte identification bit
Display outside the character area
Box left/right display specification
In line units
5
4
BXC1
GS1
Forces display within the character area
GS1
GS0
Mode
In line units
0
0
0
1
Normal (character background color)
Full area and reverse invalid (other than ±1)
Transparent 1 (all)
3
GS0
1
0
1
1
1
Transparent 2 (other than ±1)
0
1
0
1
0
GY2
0
GY1
0
GY0
0
Line spacing
In line units
2
1
GY2
GY1
0
0
0
1
±1
2
0
1
0
0
1
1
3
1
0
0
4
0
GY0
1
0
1
5
1
1
1
0
6
1
1
1
7
Note that all registers are set to 0 when these ICs are reset by the RST pin.
26/39
LC74731W, LC74732W
COMMAND63 (Line spacing control - line specification setup command)
• First byte
Content
DA0 to 7
Register
Notes
State
Function
Command 6 identification code
7
6
5
4
3
2
1
—
—
—
—
—
—
—
1
1
1
0
1
1
0
0
1
Display control settings
Extended command 3 identification code
Lower lines (0 to 5 (hexadecimal))
Upper lines (6 to B (hexadecimal))
Line spacing control - line specification
0
LGYUD
• Second byte
Content
Function
DA0 to 7
Register
Notes
State
7
6
—
—
0
0
0
1
0
1
0
1
0
1
0
1
0
1
Second byte identification bit
Line 6 (line 12) setting: off
Line 6 (line 12) setting: on
Line 5 (line 11) setting: off
Line 5 (line 11) setting: on
Line 4 (line 10) setting: off
Line 4 (line 10) setting: on
Line 3 (line 9) setting: off
Line 3 (line 9) setting: on
Line 2 (line 8) setting: off
Line 2 (line 8) setting: on
Line 1 (line 7) setting: off
Line 1 (line 7) setting: on
Line setting for line spacing control
5
4
3
2
1
0
LGYB5
LGYA4
LGY93
LGY82
LGY71
LGY60
The values in parentheses apply when LGYUD is 1.
Note that all registers are set to 0 when these ICs are reset by the RST pin.
27/39
LC74731W, LC74732W
COMMAND70 (Display control setup command)
• First byte
Content
Function
DA0 to 7
Register
Notes
State
7
6
5
4
3
2
1
—
—
—
—
—
—
—
1
1
1
1
0
0
0
0
1
Command 7 identification code
Display control settings
Extended command 0 identification code
Normal mode
Continuous mode specification
0
LRM
Continuous mode
• Second byte
Content
Function
DA0 to 7
Register
Notes
State
7
6
—
—
0
0
0
1
0
1
0
1
0
1
0
1
0
1
Second byte identification bit
BKLC1
BKLC0
Character color and character background color:
black level specification
In line units
5
4
3
2
1
0
BKLC1
BKLC0
CHLC1
CHLC0
RSLC2
RSLC1
0
0
NO1
NO2
NO3
BK1
BK2
BK3
0
1
1
0
CHLC1
CHLC0
Character color and character background color:
white level specification
In line units
0
0
NO1
NO2
NO3
CHA1
CHA2
CHA3
0
1
1
0
RSLC1
RSLC0
Character color and character background color:
color level specification
In line units
0
0
1
0
1
0
NO1
NO2
NO3
RS1
RS2
RS3
Note that all registers are set to 0 when these ICs are reset by the RST pin.
28/39
LC74731W, LC74732W
COMMAND71 (Display levels - line specification setup command)
• First byte
Content
DA0 to 7
Register
Notes
State
Function
Command 7 identification code
7
6
5
4
3
2
1
—
—
—
—
—
—
—
1
1
1
1
0
1
0
0
1
Display control settings
Extended command 1 identification code
Lower lines (0 to 5 (hexadecimal))
Upper lines (6 to B (hexadecimal))
Display levels - line specification
0
LCLUD
• Second byte
Content
Function
DA0 to 7
Register
Notes
State
7
6
—
—
0
0
0
1
0
1
0
1
0
1
0
1
0
1
Second byte identification bit
Line 6 (line 12) setting: off
Line 6 (line 12) setting: on
Line 5 (line 11) setting: off
Line 5 (line 11) setting: on
Line 4 (line 10) setting: off
Line 4 (line 10) setting: on
Line 3 (line 9) setting: off
Line 3 (line 9) setting: on
Line 2 (line 8) setting: off
Line 2 (line 8) setting: on
Line 1 (line 7) setting: off
Line 1 (line 7) setting: on
Display level line setting
5
4
3
2
1
0
LCLB5
LCLA4
LCL93
LCL82
LCL71
LCL60
The values in parentheses apply when LCLUD is 1.
Note that all registers are set to 0 when these ICs are reset by the RST pin.
29/39
LC74731W, LC74732W
COMMAND72 (Halftone - line specification setup command)
• First byte
Content
DA0 to 7
Register
Notes
State
Function
Command 7 identification code
7
6
5
4
3
2
—
—
—
—
—
—
1
1
1
1
1
0
0
1
0
1
Display control setup
Extended command 2 identification code
Halftone: off
Halftone control
1
0
LHTDAT
LHTUD
Halftone: on
Lower lines (0 to 5 (hexadecimal))
Upper lines (6 to B (hexadecimal))
Halftone line specification
• Second byte
Content
Function
DA0 to 7
Register
Notes
State
7
6
—
—
0
0
0
1
0
1
0
1
0
1
0
1
0
1
Second byte identification bit
Line 6 (line 12) setting: off
Line 6 (line 12) setting: on
Line 5 (line 11) setting: off
Line 5 (line 11) setting: on
Line 4 (line 10) setting: off
Line 4 (line 10) setting: on
Line 3 (line 9) setting: off
Line 3 (line 9) setting: on
Line 2 (line 8) setting: off
Line 2 (line 8) setting: on
Line 1 (line 7) setting: off
Line 1 (line 7) setting: on
Halftone line setting
The values in parentheses apply when LHTUD is 1.
5
4
3
2
1
0
LHTB5
LHTA4
LHT93
LHT82
LHT71
LHT60
Note that all registers are set to 0 when these ICs are reset by the RST pin.
30/39
LC74731W, LC74732W
COMMAND73 (RGB control setup command)
• First byte
Content
Function
DA0 to 7
Register
Notes
State
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
1
1
1
1
1
1
0
0
Command 7 identification code
Display control setup
Extended command 3 identification code
• Second byte
Content
Function
DA0 to 7
Register
Notes
State
7
6
—
0
0
1
0
Second byte identification bit
Normal
Switches the XTALIN amplifier input
DASSS
CLKD = CLKX
Only valid when RGB output is specified.
Switches the background color in RGB output mode
Background color: off
5
GBSEL
The background color is specified by COM4 second
byte.
1
Background color: on
0
1
0
1
0
1
0
1
0
Switches the P9 to P12 outputs
The logical OR with the OUTMOD input.
Switches the SYNin input
4
3
2
1
OUTSEL
HSPSW
XONSS
BLK02
RGB output switching
Internal Sync separator used
Internal Sync separator not used
Operation depends on the CTRL1 pin
Feedback resistor disconnected
BLK01 BLK00
The logical OR with the OUTMOD input.
Enables or disables the feedback resistor for the
XTALIN clock.
Switches the BLKout output
Box is always on.
0
0
1
1
0
1
0
1
CHA + BK + CHAB
CHA +BK only
CHA only
Always on when GBSEL = 1.
0
BLK01
1
BK only
31/39
LC74731W, LC74732W
Display Screen Structure
The display consists of 12 lines of 24 characters.
Up to 288 characters can be displayed.
The number of characters that can be displayed is less than the 288 maximum when enlarged characters are displayed.
Display memory addresses are specified as row (0 to 11 decimal) and column (0 to 23 decimal) addresses.
Display Screen Structure (display memory addresses)
24 Characters
00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23
00
01
02
03
04
05
06
07
08
09
10
11
0
1
2
3
4
5
12 Rows
6
7
8
9
A
B HEX
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17HEX
32/39
LC74731W, LC74732W
Composite Video Signal Output Levels (internally generated levels)
• CVOUT Output Level Waveform (V 2 = 5.00 V)
DD
①
②
③
[V]
2.80 3.00 3.30
2.65 2.85 3.15
VCHA1
VRSH3 VRSH2
2.37 2.57 2.87
VCHA2
VCHA3
2.08 2.28 2.58
2.01 2.21 2.51
VBK3
VRSH1
VBK2
VCBH
VPD
1.67 1.87 2.17
VRSL3
1.52 1.72 2.02
1.50 1.70 2.00
VRSL1
VBK1
1.37 1.57 1.87
1.23 1.43 1.73
VRSL2
1.07 1.27 1.67
VCBL
0.80 1.00 1.40
VSN
1H
Output level
Output voltage (1) [V]
Output voltage (2) [V]
Output voltage (3) [V]
V
V
V
V
V
V
V
V
V
V
V
V
V
CHA1: Character 1
2.65
2.37
2.23
2.08
2.01
1.80
1.67
1.52
1.50
1.37
1.23
1.07
0.80
2.85
2.57
2.43
2.28
2.21
2.00
1.87
1.72
1.70
1.57
1.43
1.27
1.00
3.25
2.97
2.83
2.68
2.61
2.40
2.27
2.12
2.10
1.97
1.83
1.67
1.40
RSH2: Background color 2: high
CHA3: Character 3
BK3: Outlining: 3
RSH1: Background color 1: high
BK2: Outlining: 2
CBH: Color burst: high
RSL1: Background color 1: low
BK1: Outlining: 1
PD: Pedestal
RSL2: Background color 2: low
CBL: Color burst: low
SN: Sync
BCOL01: RSL1
BCOL0: CBH
BCOL11:RSH1
33/39
LC74731W, LC74732W
YOUT Output Level Waveform (V 2 = 5.00 V)
DD
①
②
③
[V]
2.80 3.00 3.30
YCHA1
2.65 2.85 3.15
YCHA2
YCHA3
YBK3
YRS3
2.08 2.28 2.58
YRS2
YBK2
YRS1
1.50 1.70 2.00
1.37 1.57 1.87
YCB
YBK1
YPD
0.80 1.00 1.40
YSN
1H
Output level
Output voltage (1) [V]
Output voltage (2) [V]
Output voltage (3) [V]
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
CHA1: Character 1
2.65
2.37
2.23
2.08
2.02
1.80
1.76
1.50
1.37
1.37
0.80
2.85
2.57
2.43
2.28
2.22
2.00
1.96
1.70
1.57
1.57
1.00
3.25
2.97
2.83
2.68
2.62
2.40
2.36
2.10
1.97
1.97
1.40
CHA2: Character 2
CHA3: Character 3
BK3: Outlining: 3
RS3: Background color 3
RS2: Background color 2
RS1: Background color 1
BK1: Outlining: 1
CB: Color burst
PD: Pedestal
SN: Sync
BCOL01: YBK1
BCOL10: YRS1
BCOL11: YRS3
34/39
LC74731W, LC74732W
• COUT Output Level Waveform (V 2 = 5.00 V)
DD
CRSH2
CCBH
CRSH1
CBIAS
2.50 V
CRSL1
CCBL
CRSL3
CRSL2
Output level
Output voltage (1) [V]
Output voltage (2) [V]
Output voltage (3) [V]
C
C
C
C
C
C
C
RSH2: Background color 2: high
CBH: Color burst: high
3.07
2.80
2.74
2.50
2.25
2.20
1.93
3.07
2.80
2.74
2.50
2.25
2.20
1.93
3.07
2.80
2.74
2.50
2.25
2.20
1.93
RSH1: Background color 1: low
BIAS: Bias
RSL1: Background color 2: low
CBL: Color burst: low
RSL2: Background color 2: low
BCOL01, 10, 11: CBIAS
35/39
LC74731W, LC74732W
Sample Application Circuit
• Cvideo, Y/C
From external ROM
64
49
1
48
V
SS1
A6
XtalIN
A7
A8
XtalOUT
CTRL1
OSCIN
OSCOUT
MUTE
A9
To external ROM
A10
A11
A12
A13
A14
A15
A16
A17
CDLR
SYNCJDG/ROUT
CHARA/GOUT
BLANK/BOUT
IBOUT/BLKOUT
OUTMOD
V
1
DD
RST
SEPIN
CS
SIN
SEPOUT
SCLK
16
33
17
32
+5 V
Buffer
Buffer
Buffer
Clamp
Clamp
Clamp
36/39
LC74731W, LC74732W
• RGB
From external ROM
64
49
1
48
VSS
1
A6
XtalIN
A7
A8
XtalOUT
CTRL1
OSCIN
OSCOUT
MUTE
A9
To external ROM
A10
A11
A12
A13
A14
A15
A16
A17
CDLR
SYNCJDG/ROUT
CHARA/GOUT
BLANK/BOUT
IBOUT/BLKOUT
OUTMOD
V
1
DD
RST
SEPIN
CS
SIN
SEPOUT
SCLK
16
33
vsync
17
32
+5 V
hsync
37/39
LC74731W, LC74732W
Package Dimensions
unit : mm
SPQFP64 10x10 / SQFP64
CASE 131AK
ISSUE A
12.0 0.2
10.0 0.1
1 2
0.15 0.05
0.5
0.18
0.10
(1.25)
0 to10
0.10
SOLDERING FOOTPRINT*
GENERIC MARKING DIAGRAM*
11.40
XXXXXXXX
YDD
XXXXXXXX
YMDDD
(Unit: mm)
XXXXX = Specific Device Code
Y = Year
XXXXX = Specific Device Code
Y = Year
DD = Additional Traceability Data
M = Month
DDD = Additional Traceability Data
*This information is generic. Please refer to
device data sheet for actual part marking.
0.50
0.28
NOTE: The measurements are not to guarantee but for reference only.
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
38
LC74731W, LC74732W
ORDERING INFORMATION
Device
Package
Shipping (Qty / Packing)
SPQFP64 10x10 / SQFP64
(Pb-Free)
LC74731W-9818-E
LC74731WS-9818-E
LC74732W-9811-E
500 / Tray Foam
500 / Tray Foam
500 / Tray Foam
SPQFP64 10x10 / SQFP64
(Pb-Free)
SPQFP64 10x10 / SQFP64
(Pb-Free)
ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiariesin the United States
and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of
SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without
further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitabilityof its products for any particular purpose,
nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including
without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can
and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are
not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicationsintended to support or
sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers,
employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was
negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all
applicable copyright laws and is not for resale in any manner.
www.onsemi.com
39
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