LC75879PT [ONSEMI]
Duty General-Purpose LCD Driver;
| 型号： | LC75879PT |
| 厂家： | 
ONSEMI |
| 描述： | Duty General-Purpose LCD Driver 驱动 CD 接口集成电路 |
| 文件： | 总35页 (文件大小：359K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LC75879PT
1/4, 1/3-Duty General-Purpose
LCD Driver
Overview
The LC75879PT is the 1/4 duty and 1/3 duty general-purpose
microprocessor-controlled LCD driver that can be used in applications such
as frequency display in products with electronic tuning.In addition to being
able to drive up to 272 segments directly, the LC75879PT can also control up
to 8 general-purpose output ports. Because it has the PWM output of a
maximum of 3 ch, the brightness control of the LED backlight of RGB can
be done. Incorporation of an oscillation circuit helps to reduce the number of
external resistors and capacitors required.
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Features
Support for 1/4-duty 1/3-bias or 1/3-duty 1/3-bias drive techniques under
serial data control.
TQFP80 12x12 / TQFP80J
When 1/4-duty: Capable of driving up to 272 segments
When 1/3-duty: Capable of driving up to 207 segments
Serial data input supports CCB* format communication with the system
controller (Support 3.3 V and 5 V operation).
Serial data control of the power-saving mode based backup function and
the all segments forced off function.
Serial data control of switching between the segment output port and
general-purpose output portfunction.
(Support for up to 8 general-purpose output ports)
Support for the PWM output function of a maximum of 3 ch (It can output
from the general-purpose output port).
Support for clock output function of 1 ch (It can output from the general-
purpose output port).
Serial data control of the frame frequency of the common and segment
output waveforms.
Serial data control of switching between the internal oscillator operating
mode and external clock operating mode.
High generality, since display data is displayed directly without the
intervention of a decoder circuit.
Built-in display contrast adjustment circuit.
The INH pin allows the display to be forced to the off state.
Incorporation of an oscillator circuit (Incorporation of resistor and
capacitor for an oscillation).
* Computer Control Bus (CCB) is an ON Semiconductor’s original bus format and
the bus addresses are controlled by ON Semiconductor.
ORDERING INFORMATION
See detailed ordering and shipping information on page 35 of this data sheet.
© Semiconductor Components Industries, LLC, 2017
July 2017 - Rev. 1
1
Publication Order Number :
LC75879PT/D
LC75879PT
Specifications
Absolute Maximum Ratings at Ta = 25C, V
= 0 V
SS
Parameter
Maximum supply voltage
Input voltage
Symbol
Conditions
2
Ratings
0.3 to +6.8
Unit
V
V
V
max
DD
DD
V
1
IN
2
0.3 to +6.8
CE, CL, DI, INH
OSCI, V 1, V
V
V
0.3 to V +0.3
DD
DD
IN
DD
Output voltage
Output current
S1 to S69, COM1 to COM4, P1 to P8
S1 to S68
V
0.3 to V +0.3
V
OUT
DD
I
1
2
3
300
A
OUT
OUT
OUT
COM1 to COM4, S69
P1 to P8
I
I
3
5
mA
Allowable power dissipation
Operating temperature
Storage temperature
Ta = 85C
Pd max
Topr
200
mW
C
40 to +85
55 to +125
Tstg
C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
Allowable Operating Ranges at Ta = 40 to +85C, V
SS
= 0 V
Ratings
typ
Parameter
Supply voltage
Symbol
Conditions
Unit
V
min
max
6.3
V
V
V
V
4.5
DD
DD
DD
DD
Input voltage
*1
V
V
1
DD
2
DD
1
2
2/3V
1/3V
0
V
V
0
0
DD
DD
V
0
DD
DD
Input high level voltage
V
1
IH
CE, CL, DI,
INH
0.4V
6.3
DD
V
V
V
2
OSCI: External clock operating
mode
IH
0.4V
V
DD
0
DD
DD
DD
Input low level voltage
V
V
1
2
CE, CL, DI,
INH
0.2V
0.2V
IL
IL
OSCI: External clock operating
mode
0
10
30
External clock
f
OSCI: External clock operating
CK
300
50
600
70
kHz
%
operating frequency
External clock duty cycle
mode
[Figure4]
D
OSCI: External clock operating
CK
mode
[Figure4]
Data setup time
Data hold time
tds
CL, DI
[Figure2], [Figure3]
160
160
160
160
160
160
160
ns
ns
ns
ns
ns
ns
ns
ns
ns
tdh
tcp
tcs
tch
tφH
tφL
tr
CL, DI
CE, CL
CE, CL
CE, CL
CL
[Figure2], [Figure3]
[Figure2], [Figure3]
[Figure2], [Figure3]
[Figure2], [Figure3]
[Figure2], [Figure3]
[Figure2], [Figure3]
[Figure2], [Figure3]
[Figure2], [Figure3]
CE wait time
CE setup time
CE hold time
High level clock pulse width
Low level clock pulse width
Rise time
CL
CE, CL, DI
CE, CL, DI
160
160
Fall time
tf
INH switching time
tc
, CE
[Figure5], [Figure6]
[Figure7], [Figure8]
INH
10
s
Note : *1. V 0 = 0.70V
DD
to V
DD
DD
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
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2
LC75879PT
Electrical Characteristics for the Allowable Operating Ranges
Ratings
typ
Parameter
Hysteresis
Symbol
Pin
Conditions
Unit
V
min
max
V
H
CE, CL, DI, INH
CE, CL, DI, INH
OSCI
0.03V
DD
Input high level
current
I
I
1
V = 6.3 V
I
5.0
5.0
IH
IH
A
A
2
V = V : External
DD
clock operating mode
I
Input low level
current
I
1
2
CE, CL, DI, INH
OSCI
V = 0 V
I
5.0
5.0
IL
IL
I
V = 0 V: External
I
clock operating mode
Output high level
voltage *1
V
V
V
1
S1 to S69
I
O
I
O
I
O
I
O
I
O
I
O
= 20 A
= 100 A
= 1mA
= 20 A
= 100 A
= 1 mA
V
V
00.9
00.9
0.9
OH
OH
OH
DD
2
3
1
2
3
COM1 to COM4
P1 to P8
V
V
DD
V
DD
Output low level
voltage
V
V
V
S1 to S69
0.9
0.9
0.9
OL
OL
OL
COM1 to COM4
P1 to P8
Output middle
V
V
V
V
1
2
3
4
S1 to S69
1/3 bias I = 20 A
2/3V
1/3V
2/3V
1/3V
0
2/3V
1/3V
2/3V
1/3V
0
MID
MID
MID
MID
O
DD
0.9
DD
+0.9
level
voltage
*1
S1 to S69
1/3 bias I = 20 A
0
DD
0.9
0
DD
0.9
0
DD
+0.9
O
V
*2
COM1 to COM4
COM1 to COM4
1/3 bias I = 100 A
0
DD
+0.9
O
1/3 bias I = 100 A
0
DD
0
DD
O
0.9
+0.9
360
100
Oscillator
fosc
Internal
Internal oscillator
operating mode
240
300
kHz
frequency
Current drain
oscillator circuit
I
1
DD
V
Power-saving mode
DD
I
2
DD
V
V
= 6.3 V
DD
DD
Output open
1000
2000
Internal oscillator
operating mode
I
3
DD
V
V
= 6.3 V
DD
DD
A
Output open
External clock
operating mode
1000
2000
f
= 300 kHz
CK
V
V
2 = 0.5V
IH
DD
DD
2 = 0.1V
IL
Note: *1. V 0 = 0.70V
DD
to V
DD
DD
Note: *2. Excluding the bias voltage generation divider resistors built in the V 1 and V 2. (See Figure 1.)
DD DD
V
DD
CONTRAST
ADJUSTER
V
0
DD
V
1
2
DD
To the common and segment drivers
Except these resistors.
V
DD
V
SS
[Figure 1]
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
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3
LC75879PT
1. When CL is stopped at the low level
V
1
IH
V
1
CE
IL
tH
tL
V
1
IH
50%
CL
DI
V
1
IL
tr
tf
tch
tcp tcs
V
1
1
IH
V
IL
tds
tdh
[Figure 2]
2. When CL is stopped at the high level
V
IH1
CE
V
IL1
tL
tH
V
1
IH
50%
CL
DI
V
1
IL
tf
tr
tch
tcp tcs
V
1
IH
V
1
IL
tds
tdh
[Figure 3]
3. OSCI pin clock timing in external clock operating mode
1
H+ t
t
H
t
L
CK
CK
[kHz]
f
=
=
CK
t
t
L
L
CK
CK
CK
CK
V
2
IH
50%
OSCI
t
H
V
2
IL
CK
H+ t
100[%]
D
CK
[Figure 4]
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4
LC75879PT
Package Dimensions
unit : mm
TQFP80 12x12 / TQFP80J
CASE 932AX
ISSUE A
14.00.2
12.00.1
1 2
0.125
0.5
0.2
0.10
(1.25)
0 to 10
0.10
SOLDERING FOOTPRINT*
GENERIC
MARKING DIAGRAM*
13.40
XXXXXXXX
YMDDD
(Unit: mm)
XXXXX = Specific Device Code
Y = Year
M = Month
DDD = Additional Traceability Data
*This information is generic. Please refer to
device data sheet for actual part marking.
0.50
0.28
NOTE: The measurements are not to guarantee but for reference only.
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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5
LC75879PT
Pin Assignment
60
61
50
41
40
S63
S64
S65
S42
S41
S40
S39
S38
S37
S36
S35
S34
S33
S32
S31
S30
S29
S28
S27
S26
S25
S24
S23
S66
COM1
COM2
COM3
S67/COM4
S68
LC75879PT
(TQFP80J)
V
70
DD
V
V
1
2
30
DD
DD
V
SS
S69/OSCI
INH
CE
CL
DI
P1/S1
P2/S2
21
20
80
10
1
Top view
Block Diagram
COMMON
DRIVER
SEGMENT DRIVER & LATCH
INH
CONTROL
REGISTER
CLOCK
GENERATOR
S69/OSCI
V
DD
CONTRAST
ADJUSTER
SHIFT REGISTER
V
0
DD
CCB INTERFACE
V
1
2
DD
V
DD
V
SS
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LC75879PT
Pin Functions
Handling
when
Pin
Pin No.
Function
Active
-
I/O
O
unused
OPEN
S1/P1 to
S8/P8
79, 80,
1 to 6
7 to 64
69
Segment outputs for displaying the display data transferred by serial data
input. The S1/P1 to S8/P8 pins can be used as general-purpose output
ports under serial data control.
S9 to S66
S68
COM1 to COM3
COM4/S67
65 to 67
68
Common driver outputs
-
O
OPEN
The frame frequency is fo[Hz].
The COM4/S67 pin can be used as a segment output in 1/3 duty.
Segment output. This pin can also be used as the external clock input pin
when the external clock operating mode is selected by control data.
Serial data transfer inputs. Must be connected to the controller.
CE: Chip enable
S69/OSCI
CE
74
76
77
-
I/O
OPEN
GND
H
I
I
CL
CL: Synchronization clock
DI: Transfer data
DI
78
75
-
I
I
INH
Display off control input
L
GND
INH
=low(V )….Display forced off S1/P1 to S8/P8=low (V
•
)
SS SS
(These pins are forcibly set to the general-purpose output
port function and held at the V level.)
SS
S9 to S66,S68=low(V
)
SS
COM1 to COM3=low(V
)
SS
COM4/S67=low(V
S69/OSCI=low(V
)
SS
)
SS
(This pin is forcibly set to the segment output port function
and held at the V level.)
SS
Stops the internal oscillator. Inhibits external clock input.
Display contrast adjustment circuit stopped.
INH
=high(V )…Display on
•
DD
Enables the internal oscillator circuit.
(Internal oscillator operating mode)
Enables external clock input.
(External clock operating mode)
Display contrast adjustment circuit operation is enabled.
However, serial data transfer is possible when the display is forced off.
Used to apply the LCD drive 2/3 bias voltage externally.
V
V
1
2
71
72
70
73
-
-
-
-
I
I
OPEN
DD
Used to apply the LCD drive 1/3 bias voltage externally.
Power supply pin. A power voltage of 4.5 to 6.3 V must be applied to this pin.
Ground pin. Must be connected to ground.
OPEN
DD
V
-
-
-
-
DD
V
SS
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LC75879PT
Serial Data Input
1. 1/4 duty
(1) When CL is stopped at the low level
CE
CL
DI
1
0
1
0
0
0
1
0
D1 D2
D60 D61 D62 D63 D64 D65 D66 D67 D68
0
0
0
PS10 PS11 PS2 PS3 PS4 EXF DN OC P0 P1 P2 P3 DT SC BU
0
0
B0 B1 B2 B3 A0 A1 A2 A3
Display data
68 bits
Control data
18 bits
DD
2bits
CCB address
8 bits
1
0
1
0
0
0
1
0
D69 D70
D128 D129 D130 D131 D132 D133 D134 D135 D136
0
0
0
0
0
0
0
0
PF0 PF1 PF2 PF3 FC0 FC1 FC2 CT0 CT1 CT2
0
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
68 bits
Control data
18 bits
DD
2bits
1
0
1
0
0
0
1
0
D137 D138
D196 D197 D198 D199 D200
0
0
0
0
W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35
1
0
B0 B1 B2 B3 A0 A1 A2 A3
DD
2bits
Display data
64 bits
CCB address
8 bits
Control data
22 bits
1
0
1
0
0
0
1
0
D201 D202
D260 D261 D262 D263 D264 D265 D266 D267 D268 D269 D270 D271 D272
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
72 bits
Fixed data
14 bits
DD
2bits
Note: DD is the direction data.
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LC75879PT
(2) When CL is stopped at the high level
CE
CL
DI
1
0
1
0
0
0
1
0
D1 D2
D60 D61 D62 D63 D64 D65 D66 D67 D68
0
0
0
PS10 PS11 PS2 PS3 PS4 EXF DN OC P0 P1 P2 P3 DT SC BU
0
0
B0 B1 B2 B3 A0 A1 A2 A3
Display data
68bits
Control data
18 bits
DD
2bits
CCB address
8 bits
1
0
1
0
0
0
1
0
D69 D70
D128 D129 D130 D131 D132 D133 D134 D135 D136
0
0
0
0
0
0
0
0
PF0 PF1 PF2 PF3 FC0 FC1 FC2 CT0 CT1 CT2
0
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
68 bits
Control data
18 bits
DD
2bits
1
0
1
0
0
0
1
0
D137 D138
D196 D197 D198 D199 D200
0
0
0
0
W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35
1
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
64 bits
Control data
22 bits
DD
2bits
1
0
1
0
0
0
1
0
D201 D202
D260 D261 D262 D263 D264 D265 D266 D267 D268 D269 D270 D271 D272
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
72 bits
Fixed data
14 bits
DD
2bits
Note: DD is the direction data
• CCB address ……………….. “45H”
• D1 to D272 ………………… Display data
• PS10, PS11, PS2 to PS4 …. .. General-purpose output port (P1 to P4) function setting control data
• EXF ………………………… External clock operating frequency setting control data
• DN …………………………. S68 pin and S69/OSCI pin state setting control data
• OC …………………………. Internal oscillator operating mode/external clock operating mode switching control data
• P0 to P3 …………………….. Segment output port/general-purpose output port switching control data
• DT ………………………….. 1/4-duty 1/3-bias drive or 1/3-duty 1/3-bias drive switching control data
• SC ………………………..… Segment on/off control data
• BU ………………………..… Normal mode/power-saving mode control data
• PF0 to PF3 ………………… PWM output waveform frame frequency setting control data
• FC0 to FC2 ………………… Common/segment output waveform frame frequency setting control data
• CT0 to CT2 ………………… Display contrast setting control data
• W10 to W15, W20 to W25, ... PWM data of the PWM output
W30 to W35
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LC75879PT
2. 1/3 duty
(1) When CL is stopped at the low level
CE
CL
DI
1
0
1
0
0
0
1
0
D1 D2
D60 D61 D62 D63 D64 D65 D66 D67 D68 D69
0
0
PS10 PS11 PS2 PS3 PS4 EXF DN OC P0 P1 P2 P3 DT SC BU
0
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
69 bits
Control data
17 bits
DD
2bits
1
0
1
0
0
0
1
0
D70 D71
D129 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 D140 D141
0
0
0
0
PF0 PF1 PF2 PF3 FC0 FC1 FC2 CT0 CT1 CT2
0
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
72 bits
Control data
14 bits
DD
2bits
1
0
1
0
0
0
1
0
D142 D143
D201 D202 D203 D204 D205 D206 D207
0
0
W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35
1
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
66 bits
Control data
20 bits
DD
2bits
Note: DD is the direction data.
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LC75879PT
(2) When CL is stopped at the low level
CE
CL
DI
1
0
1
0
0
0
1
0
D1 D2
D60 D61 D62 D63 D64 D65 D66 D67 D68 D69
0
0
PS10 PS11 PS2 PS3 PS4 EXF DN OC P0 P1 P2 P3 DT SC BU
0
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
69 bits
Control data
17 bits
DD
2bits
1
0
1
0
0
0
1
0
D70 D71
D129 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 D140 D141
0
0
0
0
PF0 PF1 PF2 PF3 FC0 FC1 FC2 CT0 CT1 CT2
0
1
B0 B1 B2 B3 A0 A1 A2 A3
Display data
72 bits
Control data
14 bits
DD
2bits
CCB address
8 bits
1
0
1
0
0
0
1
0
D142 D143
D201 D202 D203 D204 D205 D206 D207
0
0
W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35
1
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
66 bits
Control data
20 bits
DD
2bits
Note: DD is the direction data.
• CCB address ……………….. “45H”
• D1 to D207 ……………….... Display data
• PS10, PS11, PS2 to PS4 ….... General-purpose output port (P1 to P4) function setting control data
• EXF ………………………... External clock operating frequency setting control data
• DN …………………………. S68 pin and S69/OSCI pin state setting control data
• OC …………………………. Internal oscillator operating mode/external clock operating mode switching control data
• P0 to P3 ……………………. Segment output port/general-purpose output port switching control data
• DT …………………………. 1/4-duty 1/3-bias drive or 1/3-duty 1/3-bias drive switching control data
• SC ………………………….. Segment on/off control data
• BU …………………………. Normal mode/power-saving mode control data
• PF0 to PF3 …………………. PWM output waveform frame frequency setting control data
• FC0 to FC2 ………………… Common/segment output waveform frame frequency setting control data
• CT0 to CT2 ………………… Display contrast setting control data
• W10 to W15, W20 to W25, ... PWM data of the PWM output
W30 to W35
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LC75879PT
3. 1/4 duty (Simple mode transfer)
(1) When CL is stopped at the low level
CE
CL
DI
1
0
1
0
0
0
1
0
D1 D2
D69 D70
D137 D138
D201 D202
D55 D56 D57 D58 D59 D60 D61 D62 D63 D64 D65 D66 D67 D68
0
0
0
DN OC P0 P1 P2 P3 DT SC BU
0
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
68 bits
Control data
10 bits
DD
2bits
1
0
1
0
0
0
1
0
D123 D124 D125 D126 D127 D128 D129 D130 D131 D132 D133 D134 D135 D136
0
0
0
FC0 FC1 FC2 CT0 CT1 CT2
0
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
68 bits
Control data
10 bits
DD
2bits
1
0
1
0
0
0
1
0
D191 D192 D193 D194 D195 D196 D197 D198 D199 D200
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
64 bits
Fixed data
14 bits
DD
2bits
1
0
1
0
0
0
1
0
D255 D256 D257 D258 D259 D260 D261 D262 D263 D264 D265 D266 D267 D268 D269 D270 D271 D272
0
0
0
0
0
0
1
1
B0 B1 B2 B3 A0 A1 A2 A3
DD
2bits
Fixed data
6 bits
CCB address
8 bits
Display data
72 bits
Note: DD is the direction data.
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LC75879PT
(2) When CL is stopped at the high level
CE
CL
DI
1
0
1
0
0
0
1
0
D1 D2
D69 D70
D137 D138
D201 D202
D55 D56 D57 D58 D59 D60 D61 D62 D63 D64 D65 D66 D67 D68
0
0
0
DN OC P0 P1 P2 P3 DT SC BU
0
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
DD
2bits
Display data
68 bits
Control data
10 bits
1
0
1
0
0
0
1
0
D123 D124 D125 D126 D127 D128 D129 D130 D131 D132 D133 D134 D135 D136
0
0
0
FC0 FC1 FC2 CT0 CT1 CT2
0
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
68 bits
Control data
10 bits
DD
2bits
1
0
1
0
0
0
1
0
D191 D192 D193 D194 D195 D196 D197 D198 D199 D200
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
Fixed data
14 bits
DD
2bits
CCB address
8 bits
Display data
64 bits
1
0
1
0
0
0
1
0
D255 D256 D257 D258 D259 D260 D261 D262 D263 D264 D265 D266 D267 D268 D269 D270 D271 D272
0
0
0
0
0
0
1
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
DD
2bits
Fixed data
6 bits
Display data
72 bits
Note: DD is the direction data.
• CCB address ....... "45H"
• D1 to D272 .......... Display data
• DN ……………... S68 pin and S69/OSCI pin state setting control data
• OC ……………... Internal oscillator operating mode/external clock operating mode switching control data
• P0 to P3 ………... Segment output port/general-purpose output port switching control data
• DT ……………... 1/4-duty 1/3-bias drive or 1/3-duty 1/3-bias drive switching control data
• SC …………….... Segment on/off control data
• BU ……………... Normal mode/power-saving mode control data
• FC0 to FC2 …..... Common/segment output waveform frame frequency setting control data
• CT0 to CT2 ……. Display contrast setting control data
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LC75879PT
4. 1/3 duty (Simple mode transfer)
(1) When CL is stopped at the low level
CE
CL
DI
1
0
1
0
0
0
1
0
D1 D2
D70 D71
D142 D143
D55 D56 D57 D58 D59 D60 D61 D62 D63 D64 D65 D66 D67 D68 D69 DN OC P0 P1 P2 P3 DT SC BU
0
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
69 bits
Control data
9 bits
DD
2bits
1
0
1
0
0
0
1
0
D124 D125 D126 D127 D128 D129 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 D140 D141 FC0 FC1 FC2 CT0 CT1 CT2
0
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
72 bits
Control data
6 bits
DD
2bits
1
0
1
0
0
0
1
0
D196 D197 D198 D199 D200 D201 D202 D203 D204 D205 D206 D207
0
0
0
0
0
0
0
0
0
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
Display data
66 bits
CCB address
8 bits
Fixed data
12 bits
DD
2bits
Note: DD is the direction data.
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LC75879PT
(2) When CL is stopped at the high level
CE
CL
DI
1
0
1
0
0
0
1
0
D1 D2
D70 D71
D142 D143
D55 D56 D57 D58 D59 D60 D61 D62 D63 D64 D65 D66 D67 D68 D69 DN OC P0 P1 P2 P3 DT SC BU
0
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Control data
9 bits
DD
2bits
Display data
69 bits
1
0
1
0
0
0
1
0
D124 D125 D126 D127 D128 D129 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 D140 D141 FC0 FC1 FC2 CT0 CT1 CT2
0
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Control data
6 bits
DD
2bits
Display data
72 bits
1
0
1
0
0
0
1
0
D196 D197 D198 D199 D200 D201 D202 D203 D204 D205 D206 D207
0
0
0
0
0
0
0
0
0
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Fixed data
12 bits
DD
2bits
Display data
66 bits
Note: DD is the direction data
• CCB address …………… “45H”
• D1 to D207 …………….. Display data
• DN ……………………… S68 pin and S69/OSCI pin state setting control data
• OC ……………………… Internal oscillator operating mode/external clock operating mode switching control data
• P0 to P3 ………………… Segment output port/general-purpose output port switching control data
• DT ……………………… 1/4-duty 1/3-bias drive or 1/3-duty 1/3-bias drive switching control data
• SC ……………………… Segment on/off control data
• BU ……………………… Normal mode/power-saving mode control data
• FC0 to FC2 …………….. Common/segment output waveform frame frequency setting control data
• CT0 to CT2 …………….. Display contrast setting control data
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LC75879PT
Serial Data Transfer Example
(1) 1/4 duty
When 201 or more segments are used
All 352 bits of serial data must be sent.
8 bits
88 bits
1
0
1
0
0
0
1
0
D1 D2
D69 D70
D137 D138
D201 D202
D60 D61 D62 D63 D64 D65 D66 D67 D68
D128 D129 D130 D131 D132 D133 D134 D135 D136
0
0
0
0
0
PS10 PS11 PS2 PS3 PS4 EXF DN OC P0 P1 P2 P3 DT SC BU
0
0
1
1
0
1
0
1
B0 B1 B2 B3 A0 A1 A2 A3
1
0
1
0
0
0
1
0
0
0
0
0
0
0 PF0 PF1 PF2 PF3 FC0 FC1 FC2 CT0 CT1 CT2
B0 B1 B2 B3 A0 A1 A2 A3
1
0
1
0
0
0
1
0
D196 D197 D198 D199 D200
0
0
0
0 W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35
B0 B1 B2 B3 A0 A1 A2 A3
1
0
1
0
0
0
1
0
D260 D261 D262 D263 D264 D265 D266 D267 D268 D269 D270 D271 D272
0
0
0
0
0
0
0
0
0
0
0
0
0
0
B0 B1 B2 B3 A0 A1 A2 A3
When fewer than 201 segments are used
The 264 bits of serial data must be sent.
However, the serial data shown below (the D1 to D200 display data and the control data) must always be sent.
8 bits
88 bits
1
0
1
0
0
0
1
0
D1 D2
D69 D70
D137 D138
D60 D61 D62 D63 D64 D65 D66 D67 D68
D128 D129 D130 D131 D132 D133 D134 D135 D136
0
0
0
0
0
PS10 PS11 PS2 PS3 PS4 EXF DN OC P0 P1 P2 P3 DT SC BU
0
0
1
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
1
0
1
0
0
0
1
0
0
0
0
0
0
0 PF0 PF1 PF2 PF3 FC0 FC1 FC2 CT0 CT1 CT2
B0 B1 B2 B3 A0 A1 A2 A3
1
0
1
0
0
0
1
0
D196 D197 D198 D199 D200
0
0
0
0
W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35
B0 B1 B2 B3 A0 A1 A2 A3
2. 1/3 duty
All 264 bits of serial data must be sent.
8 bits
88 bits
1
0
1
0
0
0
1
0
D1 D2
D70 D71
D142 D143
D60 D61 D62 D63 D64 D65 D66 D67 D68 D69
0
0
PS10 PS11 PS2 PS3 PS4 EXF DN OC P0 P1 P2 P3 DT SC BU
0
0
1
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
1
0
1
0
0
0
1
0
D129 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 D140 D141
0
0
0
0 PF0 PF1 PF2 PF3 FC0 FC1 FC2 CT0 CT1 CT2
B0 B1 B2 B3 A0 A1 A2 A3
1
0
1
0
0
0
1
0
D201 D202 D203 D204 D205 D206 D207
0
0 W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35
B0 B1 B2 B3 A0 A1 A2 A3
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LC75879PT
3. 1/4 duty (Simple mode transfer)
When 201 or more segments are used
All 320 bits of serial data must be sent.
8 bits
80 bits
1
0
1
0
0
0
1
0
D1 D2
D69 D70
D137 D138
D201 D202
D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 D64 D65 D66 D67 D68
0
0
0
DN OC P0 P1 P2 P3 DT SC BU
0
0
1
1
0
1
0
1
B0 B1 B2 B3 A0 A1 A2 A3
1
0
1
0
0
0
1
0
D120 D121 D122 D123 D124 D125 D126 D127 D128 D129 D130 D131 D132 D133 D134 D135 D136
0
0
0
0
0
0
FC0 FC1 FC2 CT0 CT1 CT2
B0 B1 B2 B3 A0 A1 A2 A3
1
0
1
0
0
0
1
0
D188 D189 D190 D191 D192 D193 D194 D195 D196 D197 D198 D199 D200
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
B0 B1 B2 B3 A0 A1 A2 A3
1
0
1
0
0
0
1
0
D252 D253 D254 D255 D256 D257 D258 D259 D260 D261 D262 D263 D264 D265 D266 D267 D268 D269 D270 D271 D272
B0 B1 B2 B3 A0 A1 A2 A3
When fewer than 201 segments are used
Either 160 or 240 bits of serial data must be sent, depending on the number of segments to be used.
However, the serial data shown below (the D1 to D136 display data and the control data) must always be sent.
8 bits
80 bits
1
0
1
0
0
0
1
0
D1 D2
D69 D70
D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 D64 D65 D66 D67 D68
0
0
DN OC P0 P1 P2 P3 DT SC BU
0
0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
1
0
1
0
0
0
1
0
D120 D121 D122 D123 D124 D125 D126 D127 D128 D129 D130 D131 D132 D133 D134 D135 D136
0
0
0 FC0 FC1 FC2 CT0 CT1 CT2
B0 B1 B2 B3 A0 A1 A2 A3
4. 1/3duty (Simple mode transfer)
When 142 or more segments are used
All 240 bits of serial data must be sent.
8 bits
80 bits
1
0
1
0
0
0
1
0
D1 D2
D70 D71
D142 D143
D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 D64 D65 D66 D67 D68 D69 DN OC P0 P1 P2 P3 DT SC BU
D121 D122 D123 D124 D125 D126 D127 D128 D129 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 D140 D141 FC0 FC1 FC2 CT0 CT1 CT2
0
0
1
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
1
0
1
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
1
0
1
0
0
0
1
0
D193 D194 D195 D196 D197 D198 D199 D200 D201 D202 D203 D204 D205 D206 D207
0
0
0
0
0
0
0
0
0
0
0
0
B0 B1 B2 B3 A0 A1 A2 A3
When fewer than 142 segments are used
The 160 bits of serial data must be sent.
However, the serial data shown below (the D1 to D141 display data and the control data) must always be sent.
8 bits
80 bits
1
0
1
0
0
0
1
0
D1 D2
D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 D64 D65 D66 D67 D68 D69 DN OC P0 P1 P2 P3 DT SC BU
D121 D122 D123 D124 D125 D126 D127 D128 D129 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 D140 D141 FC0 FC1 FC2 CT0 CT1 CT2
0
0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
1
0
1
0
0
0
1
0
D70 D71
B0 B1 B2 B3 A0 A1 A2 A3
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LC75879PT
Control Data Functions
(1) PS10 and PS11, PS2 to PS4 … General-purpose output port (P1 to P4) function setting control data
These control data bits set the general-purpose output function (High or low level output), clock output function or
PWM output function of the P1 output pin, and the general-purpose output function (High or low level output) or
PWM output function of the P2 to P4 output pins.
However, be careful of being unable to set a PWM output function when the external clock operating frequency is
set the f 2 = 38[kHz] typ (EXF = "1") in external clock operating mode (OC = "1").
CK
In addition, be careful of setting of the general-purpose output function (High or low level output) in the case of the
simple mode transfer forcibly.
PS10
PS11
General-purpose output port (P1) function
General-purpose output function (High or low level output )
0
1
0
1
0
0
1
1
Clock output function (Clock frequency : fosc/2, f /2 )
CK
Clock output function (Clock frequency : fosc/8, f /8 )
CK
PWM output function (Support for PWM data W10 to W15)
PS2
0
General-purpose output port (P2) function
General-purpose output function (High or low level output )
PWM output function (Support for PWM data W20 to W25)
1
PS3
0
General-purpose output port (P3) function
General-purpose output function (High or low level output )
PWM output function (Support for PWM data W30 to W35)
1
PS4
0
General-purpose output port (P4) function
General-purpose output function (High or low level output )
PWM output function (Support for PWM data W10 to W15)
1
(2) EXF … External clock operating frequency setting control data
This control data bit sets the operating frequency of the external clock which input into the OSCI pin, when the
external clock operating mode (OC = "1") is set. However, be careful of setting the f 1 = 300[kHz]typ when the
CK
external clock operating mode (OC = "1") is set in the case of the simple mode transfer forcibly. In addition, this
data is effective only when external clock operating mode (OC = "1") is set.
EXF
External clock operating frequency f [kHz]
CK
f
f
1=300[kHz] typ
0
1
CK
2=38[kHz] typ
CK
(3) DN … S68 pin and S69/OSCI pin state setting control data
This control data bit sets state of the S68 pin and the S69/OSCI pin.
Number of display segments
DN
Pin state
1/4 duty
1/3 duty
S68
S69/OSCI
0
Up to 264 segments
Up to 272 segments
Up to 201 segment
Up to 207 segment
“L”(V
)
“L”(V )/OSCI
SS
SS
S68
1
S69/OSCI
Note: "L" (V
S68
)
: Low (V ) level output
SS
: Segment output
SS
"L" (V )/OSCI : Low (V ) level output in internal oscillator operating mode (OC = 0)
SS
SS
External clock input in external clock operating mode (OC = 1)
S69/OSCI
: Segment output in internal oscillator operating mode (OC = 0)
External clock input in external clock operating mode (OC = 1)
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LC75879PT
(4) OC … Internal oscillator operating mode/external clock operating mode switching control data
This control data bit selects either the internal oscillator operating mode or external clock operating mode.
OC
Fundamental clock operating mode
Internal oscillator operating mode
External clock operating mode
: Segment output
I/O pin (S69/OSCI) state
0
S69
1
OSCI
Note: S69
OSCI : External clock input
(5) P0 to P3 … Segment output port/general-purpose output port switching control data
These control data bits switch the segment output port/general-purpose output port functions of the S1/P1 to S8/P8
output pins.
Control data
Output pin state
P0
0
P1
0
P2
0
P3
0
S1/P1
S1
S2/P2
S2
S3/P3
S3
S4/P4
S4
S5/P5
S5
S6/P6
S6
S7/P7
S7
S8/P8
S8
0
0
0
1
P1
S2
S3
S4
S5
S6
S7
S8
0
0
1
0
P1
P2
S3
S4
S5
S6
S7
S8
0
0
1
1
P1
P2
P3
S4
S5
S6
S7
S8
0
1
0
0
P1
P2
P3
P4
S5
S6
S7
S8
0
1
0
1
P1
P2
P3
P4
P5
S6
S7
S8
0
1
1
0
P1
P2
P3
P4
P5
P6
S7
S8
0
1
1
1
P1
P2
P3
P4
P5
P6
P7
S8
1
0
0
0
P1
P2
P3
P4
P5
P6
P7
P8
Note1: Sn(n=1 to 8): Segment output ports
Pn(n=1 to 8): General-purpose output ports
Note2: When are setting (P0,P1,P2,P3)=(1,0,0,1), (1,0,1,0), (1,0,1,1) and (1,1,X,X), the all P1/S1 to P8/S8 output
pins selects the segment output port. X: don’t care
The table below lists the correspondence between the display data and the output pins when these pins are selected
to be general-purpose output ports (general-purpose output function).
Correspondence display data
Output pin
1/4 duty
1/3 duty
S1/P1
S2/P2
S3/P3
S4/P4
S5/P5
S6/P6
S7/P7
S8/P8
D1
D5
D1
D4
D9
D7
D13
D17
D21
D25
D29
D10
D13
D16
D19
D22
For example, if the circuit is operated in 1/4 duty and the S4/P4 output pin is selected to be a general-purpose output
port and is set general-purpose output function, the S4/P4 output pin will output a high level when the display data
D13 is 1, and will output a low level when D13 is 0.
(6) DT … 1/4-duty 1/3-bias drive or 1/3-duty 1/3-bias drive switching control data
This control data bit selects either 1/4-duty 1/3-bias drive or 1/3-duty 1/3-bias drive.
DT
Drive scheme
The COM4/S67 pin state
0
1/4-duty 1/3-bias drive
1/3-duty 1/3-bias drive
COM4
S67
1
Note: COM4 : Common output
S67 : Segment output
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LC75879PT
(7) SC … Segment on/off control data
This control data bit controls the on/off state of the segments.
SC
Display state
0
On
Off
1
Note that when the segments are turned off by setting SC to 1, the segments are turned off by outputting segment off
waveforms from the segment output pins.
(8) BU … Normal mode/power-saving mode control data
This control data bit selects either normal mode or power-saving mode.
BU
Mode
Normal mode
0
Power saving mode
In this mode, the internal oscillator circuit stops oscillation (the S69/OSCI pin is configured for segment output) if the IC is
in the internal oscillator operating mode (OC=0) and the IC stops receiving external clock signals (the S69/OSCI pin is
configured for external clock input) if the IC is in the external clock operating mode (OC=1).
1
The common and segment output pins go to the V
SS
level. However, the S1/P1 to S8/P8 output pins can be used as
general-purpose output ports under the control of the data bits P0 to P3.
(The general-purpose output port P1 to P4 can not be used as clock output or PWM output).
(9) PF0 to PF3 … PWM output waveform frame frequency setting control data
These control data bits set the frame frequency of the PWM output waveforms. However, when the PWM output
function isn’t used, these control data bits become invalid. In addition, when the external clock operating frequency
is set the f 2 = 38[kHz] typ (EXF = "1") in external clock operating mode (OC = "1") or when the serial data
CK
transfer is the simple mode transfer, these control data bits become invalid.
Control data
PWM output waveform frame frequency fp[Hz]
Internal oscillator operating mode
External clock operating mode
PF0
PF1
PF2
PF3
(The control data OC is 0,
fosc=300[kHz] typ)
(The control data OC is 1 and EXF is 0,
f
1=300[kHz] typ)
CK
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
fosc/1536
fosc/1408
fosc/1280
fosc/1152
fosc/1024
fosc/896
fosc/768
fosc/640
fosc/512
fosc/384
fosc/256
f
f
f
f
f
1/1536
1/1408
1/1280
1/1152
1/1024
1/896
CK
CK
CK
CK
0
1
1
0
0
1
1
0
0
1
0
0
0
1
1
1
1
0
0
0
CK
f
CK
CK
CK
CK
CK
CK
f
f
f
f
f
1/768
1/640
1/512
1/384
1/256
Note : When is setting (PF0,PF1,PF2,PF3) = (1,1,0,1) and (X,X,1,1), the frame frequency is same as frame
frequency at the time of the (PF0,PF1,PF2,PF3) = (1,0,1,0) setting (fosc/896, f 1/896).
CK
X: don’t care
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LC75879PT
(10) FC0 to FC2 … Common/segment output waveform fram frequency control data
These control data bits set the frame frequency of the common and segment output waveforms.
Control data
Common/segment output waveform frame frequency fo[Hz]
Internal oscillator
operating mode
External clock
External clock
operating mode
operating mode
FC0
FC1
FC2
(The control data OC is 0,
fosc=300[kHz] typ)
(The control data OC is 1
and EXF is 0,
(The control data OC is 1
and EXF is 1,
f
1=300[kHz] typ)
CK
f
2=38[kHz] typ)
CK
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
fosc/6144
fosc/4608
fosc/3072
fosc/2304
fosc/1536
fosc/1152
fosc/768
f
f
f
f
f
f
1/6144
1/4608
1/3072
1/2304
1/1536
1/1152
1/768
f
f
f
f
f
f
2/768
2/576
2/384
2/288
2/192
2/144
2/96
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
f
CK
f
CK
CK
Note: When is setting (FC0,FC1,FC2) = (1,0,1), the frame frequency is same as frame frequency at the time of the
(FC0,FC1,FC2) = (0,0,0) setting (fosc/3072, fCK1/3072, fCK2/384).
(11) CT0 to CT2 … Display contrast setting control data
These control data bits set display contrast.
CT0 to CT2: Sets the display contrast (7 steps)
CT0
CT1
CT2
LCD drive 3/3 bias voltage V 0 level
DD
0
0
0
1.00V =V -(0.05V ×0)
DD DD
DD
1
0
0
0.95V =V -(0.05V ×1)
DD DD DD
0
1
0
0.90V =V -(0.05V ×2)
DD DD DD
1
1
0
0.85V =V -(0.05V ×3)
DD DD DD
0
0
1
0.80V =V -(0.05V ×4)
DD DD DD
1
0
1
0.75V =V -(0.05V ×5)
DD DD DD
0
1
1
0.70V =V -(0.05V ×6)
DD DD DD
Note: When is setting (CT0,CT1,CT2) = (1,1,1), the LCD drive 3/3 bias voltage V 0 level is 1.00V
DD
.
DD
Note that although the display contrast can be adjusted by operating the built-in display contrast
adjustment circuit, it can also be adjusted by modifying the supply pin V
voltage level.
DD
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21
LC75879PT
(12) W10 to W15, W20 to W25, W30 to W35 …… PWM data of the PWM output
These control data bits set the pulse width of the PWM output P1 to P4. However, when the PWM output function
isn’t used, these control data bits become invalid. In addition, when the external clock operating frequency is set
the f 2 = 38[kHz] typ (EXF = "1") in external clock operating mode (OC = "1") or when the serial data transfer
CK
is the simple mode transfer, these control data bits become invalid.
Pulse width of
Pulse width of
PWM output
Wn0
Wn1
Wn2
Wn3
Wn4
Wn5
Wn0
Wn1
Wn2
Wn3
Wn4
Wn5
PWM output
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
(1/64)×Tp
(2/64)×Tp
(3/64)×Tp
(4/64)×Tp
(5/64)×Tp
(6/64)×Tp
(7/64)×Tp
(8/64)×Tp
(9/64)×Tp
(10/64)×Tp
(11/64)×Tp
(12/64)×Tp
(13/64)×Tp
(14/64)×Tp
(15/64)×Tp
(16/64)×Tp
(17/64)×Tp
(18/64)×Tp
(19/64)×Tp
(20/64)×Tp
(21/64)×Tp
(22/64)×Tp
(23/64)×Tp
(24/64)×Tp
(25/64)×Tp
(26/64)×Tp
(27/64)×Tp
(28/64)×Tp
(29/64)×Tp
(30/64)×Tp
(31/64)×Tp
(32/64)×Tp
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
(33/64)×Tp
(34/64)×Tp
(35/64)×Tp
(36/64)×Tp
(37/64)×Tp
(38/64)×Tp
(39/64)×Tp
(40/64)×Tp
(41/64)×Tp
(42/64)×Tp
(43/64)×Tp
(44/64)×Tp
(45/64)×Tp
(46/64)×Tp
(47/64)×Tp
(48/64)×Tp
(49/64)×Tp
(50/64)×Tp
(51/64)×Tp
(52/64)×Tp
(53/64)×Tp
(54/64)×Tp
(55/64)×Tp
(56/64)×Tp
(57/64)×Tp
(58/64)×Tp
(59/64)×Tp
(60/64)×Tp
(61/64)×Tp
(62/64)×Tp
(63/64)×Tp
(64/64)×Tp
Note: W10 to W15 … PWM data of the output pin S1/P1 and S4/P4
W20 to W25 … PWM data of the output pin S2/P2
1
fp
Tp=
W30 to W35 … PWM data of the output pin S3/P3
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22
LC75879PT
Display Data and Output Pin Correspondence (1/4 Duty)
Output pin
COM1
COM2
COM3
COM4
Output pin
COM1
COM2
COM3
COM4
S1/P1
S2/P2
S3/P3
S4/P4
S5/P5
S6/P6
S7/P7
S8/P8
S9
D1
D5
D2
D6
D3
D7
D4
D8
S35
S36
S37
S38
S39
S40
S41
S42
S43
S44
S45
S46
S47
S48
S49
S50
S51
S52
S53
S54
S55
S56
S57
S58
S59
S60
S61
S62
S63
S64
S65
S66
S68
S69/OSCI
D137
D141
D145
D149
D153
D157
D161
D165
D169
D173
D177
D181
D185
D189
D193
D197
D201
D205
D209
D213
D217
D221
D225
D229
D233
D237
D241
D245
D249
D253
D257
D261
D265
D269
D138
D142
D146
D150
D154
D158
D162
D166
D170
D174
D178
D182
D186
D190
D194
D198
D202
D206
D210
D214
D218
D222
D226
D230
D234
D238
D242
D246
D250
D254
D258
D262
D266
D270
D139
D143
D147
D151
D155
D159
D163
D167
D171
D175
D179
D183
D187
D191
D195
D199
D203
D207
D211
D215
D219
D223
D227
D231
D235
D239
D243
D247
D251
D255
D259
D263
D267
D271
D140
D144
D148
D152
D156
D160
D164
D168
D172
D176
D180
D184
D188
D192
D196
D200
D204
D208
D212
D216
D220
D224
D228
D232
D236
D240
D244
D248
D252
D256
D260
D264
D268
D272
D9
D10
D14
D18
D22
D26
D30
D34
D38
D42
D46
D50
D54
D58
D62
D66
D70
D74
D78
D82
D86
D90
D94
D98
D102
D106
D110
D114
D118
D122
D126
D130
D134
D11
D15
D19
D23
D27
D31
D35
D39
D43
D47
D51
D55
D59
D63
D67
D71
D75
D79
D83
D87
D91
D95
D99
D103
D107
D111
D115
D119
D123
D127
D131
D135
D12
D16
D20
D24
D28
D32
D36
D40
D44
D48
D52
D56
D60
D64
D68
D72
D76
D80
D84
D88
D92
D96
D100
D104
D108
D112
D116
D120
D124
D128
D132
D136
D13
D17
D21
D25
D29
D33
D37
D41
D45
D49
D53
D57
D61
D65
D69
D73
D77
D81
D85
D89
D93
D97
D101
D105
D109
D113
D117
D121
D125
D129
D133
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
Note: This table assumes that pins S1/P1 to S8/P8 and S69/OSCI are configured for segment output.
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23
LC75879PT
For example, the table below lists the output states for the S21 output pin.
Display data
Output pin (S21) state
D81
D82
D83
D84
The LCD segments corresponding to COM1, COM2, COM3, and COM4 are off.
The LCD segment corresponding to COM4 is on.
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
The LCD segment corresponding to COM3 is on.
The LCD segment corresponding to COM3 and COM4 are on.
The LCD segment corresponding to COM2 is on.
The LCD segment corresponding to COM2 and COM4 are on.
The LCD segment corresponding to COM2 and COM3 are on.
The LCD segments corresponding to COM2, COM3, and COM4 are on.
The LCD segment corresponding to COM1 is on.
The LCD segment corresponding to COM1 and COM4 are on.
The LCD segment corresponding to COM1 and COM3 are on.
The LCD segments corresponding to COM1, COM3, and COM4 are on.
The LCD segment corresponding to COM1 and COM2 are on.
The LCD segments corresponding to COM1, COM2, and COM4 are on.
The LCD segments corresponding to COM1, COM2, and COM3 are on.
The LCD segments corresponding to COM1, COM2, COM3, and COM4 are on.
Display Data and Output Pin Correspondence (1/3 Duty)
Output pin
S1/P1
S2/P2
S3/P3
S4/P4
S5/P5
S6/P6
S7/P7
S8/P8
S9
COM1
COM2
COM3
Output pin
S36
COM1
D106
D109
D112
D115
D118
D121
D124
D127
D130
D133
D136
D139
D142
D145
D148
D151
D154
D157
D160
D163
D166
D169
D172
D175
D178
D181
D184
D187
D190
D193
D196
D199
D202
D205
COM2
D107
D110
D113
D116
D119
D122
D125
D128
D131
D134
D137
D140
D143
D146
D149
D152
D155
D158
D161
D164
D167
D170
D173
D176
D179
D182
D185
D188
D191
D194
D197
D200
D203
D206
COM3
D108
D111
D114
D117
D120
D123
D126
D129
D132
D135
D138
D141
D144
D147
D150
D153
D156
D159
D162
D165
D168
D171
D174
D177
D180
D183
D186
D189
D192
D195
D198
D201
D204
D207
D1
D2
D3
D4
D5
D6
S37
D7
D8
D9
S38
D10
D13
D16
D19
D22
D25
D28
D31
D34
D37
D40
D43
D46
D49
D52
D55
D58
D61
D64
D67
D70
D73
D76
D79
D82
D85
D88
D91
D94
D97
D100
D103
D11
D14
D17
D20
D23
D26
D29
D32
D35
D38
D41
D44
D47
D50
D53
D56
D59
D62
D65
D68
D71
D74
D77
D80
D83
D86
D89
D92
D95
D98
D101
D104
D12
D15
D18
D21
D24
D27
D30
D33
D36
D39
D42
D45
D48
D51
D54
D57
D60
D63
D66
D69
D72
D75
D78
D81
D84
D87
D90
D93
D96
D99
D102
D105
S39
S40
S41
S42
S43
S44
S10
S45
S11
S46
S12
S47
S13
S48
S14
S49
S15
S50
S16
S51
S17
S52
S18
S53
S19
S54
S20
S55
S21
S56
S22
S57
S23
S58
S24
S59
S25
S60
S26
S61
S27
S62
S28
S63
S29
S64
S30
S65
S31
S66
S32
S67/COM4
S68
S33
S34
S69/OSCI
S35
Note: This table assumes that pins S1/P1 to S8/P8, S67/COM4 and S69/OSCI are configured for segment output.
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24
LC75879PT
For example, the table below lists the output states for the S21 output pin.
Display data
Output pin (S21) state
D61
0
D62
0
D63
0
The LCD segments corresponding to COM1, COM2, and COM3 are off.
The LCD segment corresponding to COM3 is on.
0
0
1
The LCD segment corresponding to COM2 is on.
0
1
0
The LCD segment corresponding to COM2 and COM3 are on.
The LCD segment corresponding to COM1 is on.
0
1
1
1
0
0
The LCD segment corresponding to COM1 and COM3 are on.
The LCD segment corresponding to COM1 and COM2 are on.
The LCD segments corresponding to COM1, COM2, and COM3 are on.
1
0
1
1
1
0
1
1
1
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25
LC75879PT
Output Waveforms (1/4-Duty 1/3-Bias Drive Scheme)
fo[Hz]
V
V
V
0
1
2
DD
DD
DD
COM1
COM2
COM3
COM4
0V
V
V
V
0
1
2
DD
DD
DD
0V
V
V
V
0
1
2
DD
DD
DD
0V
V
V
V
0
1
2
DD
DD
DD
0V
V
V
V
0
1
2
DD
DD
DD
LCD driver output when all LCD segments
corresponding to COM1, COM2, COM3, and
COM4 are off.
0V
V
V
V
0
1
2
DD
DD
DD
LCD driver output when only LCD segments
corresponding to COM1 are on.
0V
V
V
V
0
1
2
DD
DD
DD
LCD driver output when only LCD segments
corresponding to COM2 are on.
0V
V
V
V
0
1
2
DD
DD
DD
LCD driver output when LCD segments
corresponding to COM1 and COM2 are on.
0V
V
V
V
0
1
2
DD
DD
DD
LCD driver output when only LCD segments
corresponding to COM3 are on.
0V
V
V
V
0
1
2
DD
DD
DD
LCD driver output when LCD segments
corresponding to COM1 and COM3 are on.
0V
V
V
V
0
1
2
DD
DD
DD
LCD driver output when LCD segments
corresponding to COM2 and COM3 are on.
0V
V
V
V
0
1
2
DD
DD
DD
LCD driver output when LCD segments
corresponding to COM1, COM2, and COM3
are on.
0V
V
V
V
0
1
2
DD
DD
DD
LCD driver output when only LCD segments
corresponding to COM4 are on.
0V
V
V
V
0
1
2
DD
DD
DD
LCD driver output when LCD segments
corresponding to COM2 and COM4 are on.
0V
V
V
V
0
1
2
DD
DD
DD
LCD driver output when all LCD segments
corresponding to COM1, COM2, COM3, and
COM4 are on.
0V
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LC75879PT
Control data
FC1
Common/segment output waveform frame frequency fo[Hz]
Internal oscillator operating mode
External clock operating mode
(The control data OC is 1
External clock operating mode
FC0
FC2
(The control data OC is 0,
fosc=300[kHz] typ)
(The control data OC is 1
and EXF is 0, f 1=300[kHz] typ)
CK
and EXF is 1, f 2=38[kHz] typ)
CK
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
fosc/6144
fosc/4608
fosc/3072
fosc/2304
fosc/1536
fosc/1152
fosc/768
f
f
f
f
f
f
1/6144
1/4608
1/3072
1/2304
1/1536
1/1152
1/768
f
f
f
f
f
f
2/768
2/576
2/384
2/288
2/192
2/144
2/96
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
f
CK
f
CK
CK
Note: When is setting (FC0,FC1,FC2) = (1,0,1), the frame frequency is same as frame frequency at the time
of the (FC0,FC1,FC2) = (0,0,0) setting (fosc/3072, f 1/3072, f 2/384).
CK
CK
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27
LC75879PT
Output Waveforms (1/3-Duty 1/3-Bias Drive Scheme)
fo[Hz]
V
V
V
0
1
2
DD
DD
DD
COM1
COM2
COM3
0V
V
V
V
0
1
2
DD
DD
DD
0V
V
V
V
0
1
2
DD
DD
DD
0V
V
V
V
0
1
2
DD
DD
DD
LCD driver output when all LCD segments
corresponding to COM1, COM2, and COM3
are off.
0V
V
V
V
0
1
2
DD
DD
DD
LCD driver output when only LCD segments
corresponding to COM1 are on.
0V
V
V
V
0
1
2
DD
DD
DD
LCD driver output when only LCD segments
corresponding to COM2 are on.
0V
V
V
V
0
1
2
DD
DD
DD
LCD driver output when LCD segments
corresponding to COM1 and COM2 are on.
0V
V
V
V
0
1
2
DD
DD
DD
LCD driver output when only LCD segments
corresponding to COM3 are on.
0V
V
V
V
0
1
2
DD
DD
DD
LCD driver output when LCD segments
corresponding to COM1 and COM3 are on.
0V
V
V
V
0
1
2
DD
DD
DD
LCD driver output when LCD segments
corresponding to COM2 and COM3 are on.
0V
V
V
V
0
1
2
DD
DD
DD
LCD driver output when all LCD segments
corresponding to COM1, COM2,and COM3
are on.
0V
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LC75879PT
Control data
FC1
Common/segment output waveform frame frequency fo[Hz]
Internal oscillator operating mode
External clock operating mode
(The control data OC is 1
External clock operating mode
FC0
FC2
(The control data OC is 0,
fosc=300[kHz] typ)
(The control data OC is 1
and EXF is 0, f 1=300[kHz] typ)
CK
and EXF is 1, f 2=38[kHz] typ)
CK
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
fosc/6144
fosc/4608
fosc/3072
fosc/2304
fosc/1536
fosc/1152
fosc/768
f
f
f
f
f
f
1/6144
1/4608
1/3072
1/2304
1/1536
1/1152
1/768
f
f
f
f
f
f
2/768
2/576
2/384
2/288
2/192
2/144
2/96
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
f
CK
f
CK
CK
Note: When is setting (FC0,FC1,FC2) = (1,0,1), the frame frequency is same as frame frequency at the time of the
(FC0,FC1,FC2) = (0,0,0) setting (fosc/3072, f 1/3072, f 2/384).
CK CK
PWM output port waveforms
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DD
SS
DD
SS
DD
SS
DD
SS
DD
SS
DD
SS
DD
SS
DD
SS
DD
SS
P1/P4
(56/64)Tp
(48/64)Tp
(56/64)Tp
(48/64)Tp
(40/64)Tp
(1)
(2)
(3)
P2
P3
(40/64)Tp
P1/P4
P2
(8/64)Tp
(8/64)Tp
(16/64)Tp
(24/64)Tp
(32/64)Tp
(32/64)Tp
(32/64)Tp
(16/64)Tp
(24/64)Tp
(32/64)Tp
(32/64)Tp
(32/64)Tp
P3
P1/P4
P2
P3
1
fp
Tp=
Tp
Tp
Control data
PWM output
waveforms
W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
0
0
1
0
1
1
1
0
0
(1)
(2)
(3)
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29
LC75879PT
Control data
PWM output waveform frame frequency fp[Hz]
Internal oscillator operating mode
(The control data OC is 0,
fosc=300[kHz] typ)
External clock operating mode
(The control data OC is 1 and
PF0
PF1
PF2
PF3
EXF is 0, f 1=300[kHz] typ)
CK
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
fosc/1536
fosc/1408
fosc/1280
fosc/1152
fosc/1024
fosc/896
fosc/768
fosc/640
fosc/512
fosc/384
fosc/256
f
f
f
f
f
1/1536
1/1408
1/1280
1/1152
1/1024
1/896
CK
CK
CK
CK
0
1
1
0
0
1
1
0
0
1
0
0
0
1
1
1
1
0
0
0
CK
f
CK
CK
CK
CK
CK
CK
f
f
f
f
f
1/768
1/640
1/512
1/384
1/256
Note: When is setting (PF0,PF1,PF2,PF3) = (1,1,0,1) and (X,X,1,1), the frame frequency is same as frame frequency at
the time of the (PF0,PF1,PF2,PF3) = (1,0,1,0) setting (fosc/896, f 1/896).
CK
X: don’t care
Clock output waveforms
Control data
Clock frequency of clock output P1
fc(=1/Tc)[Hz]
PS10
PS11
P1
Tc/2
1
0
0
1
Clock output function (fosc/2, f /2)
CK
Clock output function (fosc/8, f /8)
CK
Tc
1
Tc=
fc
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30
LC75879PT
Display Control and the INH Pin
Since the LSI internal data (1/4 duty : the display data D1 to D272 and the control data, 1/3 duty : the display data D1 to
D207 and the control data) is undefined when power is first applied, applications should set the pin low at the same
INH
time as power is applied to turn off the display (This sets the S1/P1 to S8/P8, S9 to S66, COM1 to COM3, COM4/S67,
S68, and S69/OSCI pins to the V level.) and during this period send serial data from the controller. The controller
SS
pin high after the data transfer has completed. This procedure prevents meaningless display at
should then set the
INH
power on (See Figure 5, Figure 6, Figure 7 and Figure 8.)
(1)1/4 duty
t1
t2
V
DD
INH
CE
V
1
IL
tc
V
1
IL
Display data and control
data transferred
D1 to D68, PS10, PS11,
Internal data PS2 to PS4, EXF, DN, OC,
P0 to P3, DT, SC, BU
Undefined
Undefined
Undefined
Undefined
Defined
Defined
Defined
Undefined
Undefined
D69 to D136, PF0 to PF3,
FC0 to FC2, CT0 to CT2
Internal data
D137 to D200, W10 to W15,
Internal data
Undefined
Undefined
W20 to W25, W30 to W35
(D201 to D272)
Internal data
Defined
Note: t1>1ms
t2>0
[Figure 5]
tc … 10s min
(2) 1/3 duty
t1
t2
V
DD
INH
CE
V
1
IL
tc
V
1
IL
Display data and control
data transferred
D1 to D69, PS10, PS11,
PS2 to PS4, EXF, DN, OC,
P0 to P3, DT, SC, BU
Internal data
Internal data
Internal data
Defined
Defined
Defined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
D70 to D141, PF0 to PF3,
FC0 to FC2, CT0 to CT2
D142 to D207, W10 to W15,
W20 to W25, W30 to W35
Note: t1>1ms
t2>0
[Figure 6]
tc … 10s min
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31
LC75879PT
(3)1/4 duty (Simple mode transfer)
t1
t2
V
DD
INH
CE
V
IL1
tc
V
1
IL
Display data and control
data transferred
D1 to D68, DN, OC,
P0 to P3, DT, SC, BU
Internal data
Internal data
Defined
Defined
Defined
Defined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
D69 to D136,
FC0 to FC2, CT0 to CT2
Internal data (D137 to D200)
Internal data (D201 to D272)
Undefined
Note: t1>1ms
t2>0
tc …10s min
[Figure 7]
(4)1/3 duty (Simple mode transfer)
t2
t1
V
DD
INH
CE
V
1
IL
tc
V
1
IL
Display data and control
data transferred
D1 to D69, DN, OC,
P0 to P3, DT, SC, BU
Defined
Undefined
Internal data
Internal data
Undefined
Undefined
Undefined
D70 to D141,
FC0 to FC2, CT0 to CT2
Undefined
Undefined
Defined
Defined
Internal data (D142 to D207)
Note: t1>1ms
t2>0
tc …10s min
[Figure 8]
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32
LC75879PT
Notes on Controller Transfer of Display Data
When using the LC75879PT in 1/4 duty, applications transfer the display data (D1 to D272) in four operations, and in
1/3 duty, they transfer the display data (D1 to D207) in three operations. In either case, applications should transfer all
of the display data within 30 ms to maintain the quality of displayed image.
S69/OSCI Pin Peripheral Circuit
(1) Internal oscillator operating mode (control data OC=0)
Connect the S69/OSCI pin to the LCD panel when the internal oscillator operating mode is selected.
OSCI/S69
To LCD panel
(2) External clock operating mode (control data OC=1)
When the external clock operating mode is selected, insert a current protection resistor Rg (2.2 to 22 k) between
the S69/OSCI pin and external clock output pin (external oscillator). Determine the value of the resistance according
to the allowable current value at the external clock output pin. Also make sure that the waveform of the external
clock is not heavily distorted.
External clock output pin
External oscillator
OSCI/S69
Rg
V
DD
Rg
Note: Allowable current value at external clock output pin >
(3) Unused pin treatment
When the S69/OSCI pin is not to be used, select the internal oscillator operating mode (setting control data OC to 0)
to keep the pin open.
OPEN
OSCI/S69
P1 to P4 pin peripheral circuit
It is recommended the circuit shown below be used to adjust the brightness of the LED backlight using the PWM output
P1 to P4
+5V
LED
P1 to P4
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33
LC75879PT
Sample Application Circuit 1
1/4 Duty, 1/3Bias
General-purpose
output ports
(P1)
(P2)
Used for functions
such as backlight
control
(P8)
+5V
V
V
COM1
COM2
DD
1
DD
COM3
S67/COM4
P1/S1
V
V
2
DD
C
C
P2/S2
SS
P8/S8
S9
C0.047F
INH
CE
CL
DI
From the
controller
S66
S68
*3
*4 OSCI/S69
*3 The pins to be connected to the controller (CE, CL, DI, INH) can handle 3.3 V or 5 V.
*4 Connect the S69/OSCI pin to the LCD panel in the internal oscillator operating mode and insert a current protection
resistor Rg (2.2 to 22 k) between the S69/OSCI pin and external clock output pin (external oscillator) in the
external clock operating mode (see “S69/OSCI Pin Peripheral Circuit”).
Sample Application Circuit 2
1/3 Duty, 1/3 Bias
General-purpose
output ports
(P1)
(P2)
Used for functions
such as backlight
control
(P8)
V
V
COM1
COM2
COM3
P1/S1
P2/S2
+5V
DD
DD
1
V
V
2
DD
C
C
SS
P8/S8
S9
C0.047F
S66
COM4/S67
S68
INH
CE
CL
DI
From the
controller
*3
OSCI/S69
*4
*3 The pins to be connected to the controller (CE, CL, DI, INH) can handle 3.3 V or 5 V.
*4 Connect the S69/OSCI pin to the LCD panel in the internal oscillator operating mode and insert a current protection
resistor Rg (2.2 to 22 k) between the S69/OSCI pin and external clock output pin (external oscillator) in the
external clock operating mode (see “S69/OSCI Pin Peripheral Circuit”)
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34
LC75879PT
ORDERING INFORMATION
Device
Package
Shipping (Qty / Packing)
595 / Tray JEDEC
TQFP80 12x12 / TQFP80J
(Pb-Free / Halogen Free)
LC75879PT-H
LC75879PTH-H
LC75879PTS-H
TQFP80 12x12 / TQFP80J
(Pb-Free / Halogen Free)
119 / Tray JEDEC
119 / Tray JEDEC
TQFP80 12x12 / TQFP80J
(Pb-Free / Halogen Free)
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