LC75886PW [ONSEMI]
IC LIQUID CRYSTAL DISPLAY DRIVER, Display Driver;
| 型号： | LC75886PW |
| 厂家： | 
ONSEMI |
| 描述： | IC LIQUID CRYSTAL DISPLAY DRIVER, Display Driver 驱动 接口集成电路 |
| 文件： | 总36页 (文件大小：431K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : ENA1391
LC75886PW
CMOS IC
1/4 and 1/3-Duty LCD Display
Driver with Key Input Function
http://onsemi.com
Overview
The LC75886PW is 1/4 duty and 1/3 duty LCD display driver that can directly drive up to 224 segments and can
control up to 5 general-purpose output ports. This product also incorporates a key scan circuit that accepts input from
up to 30 keys to reduce printed circuit board wiring.
Features
• Key input function for up to 30 keys (A key scan is performed only when a key is pressed.)
• 1/4 duty 1/3 bias and 1/3 duty 1/3 bias drive schemes can be controlled from serial data.
• Capable of driving up to 224 segments using 1/4 duty and up to 171 segments using 1/3 duty.
• Switching between key scan output and segment output can be controlled from serial data.
• The key scan operation enabled/disabled state can be controlled from serial data.
• Switching between segment output port and general-purpose output port can be controlled from serial data.
• Switching between general-purpose output port, clock output port, and segment output port can be controlled from
serial data. (Up to 5 general-purpose output ports and up to one clock output port)
• Serial data I/O supports CCB format communication with the system controller. (Support 3.3V and 5V operation)
• Sleep mode and all segments off functions that are controlled from serial data.
• The frame frequency of the common and segment output waveforms can be controlled from serial data.
• Switching between RC oscillator operating mode and external clock operationg mode can be controlled from serial
data.
• Direct display of display data without the use of a decoder provides high generality.
• Provision of an on-chip voltage-detection type reset circuit prevents incorrect displays.
•
pin provided for forcibly initializing the IC internal circuits.
RES
• CCB is ON Semiconductor® ’s original format. All addresses are managed
by ON Semiconductor® for this format.
• CCB is a registered trademark of Semiconductor Components Industries, LLC.
Semiconductor Components Industries, LLC, 2013
July, 2013
51309HKIM 20081208-S00009 No.A1391-1/36
LC75886PW
Specifications
Absolute Maximum Ratings at Ta = 25°C, V = 0V
SS
Parameter
Symbol
max
Conditions
Ratings
-0.3 to +7.0
Unit
V
V
V
V
V
V
I
V
Maximum supply voltage
DD
DD
CE, CL, DI,
OSC, TEST, V 1, V 2, KI1 to KI5
RES
1
-0.3 to +7.0
IN
IN
Input voltage
V
2
-0.3 to V +0.3
DD
DD DD
1
2
DO
-0.3 to +7.0
OUT
OUT
Output voltage
V
OSC, S1 to S57, COM1 to COM4, KS1 to KS6, P1 to P5
-0.3 to V +0.3
DD
1
S1 to S57
300
μA
OUT
OUT
OUT
OUT
I
I
I
2
COM1 to COM4
KS1 to KS6
P1 to P5
3
Output current
3
4
1
5
mA
Pd max
Topr
Ta=85°C
200
Allowable power dissipation
Operating temperature
Storage temperature
mW
°C
-40 to +85
-55 to +125
Tstg
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Allowable Operating Ranges at Ta = -40 to +85°C, V = 0V
SS
Ratings
typ
Parameter
Symbol
Conditions
Unit
V
min
max
Supply voltage
V
V
V
V
V
V
V
V
V
V
V
V
4.5
6.0
DD
DD
DD
DD
DD
Input voltage
1
2
1
2
2/3V
V
V
DD
DD
DD
V
1/3V
DD
DD
6.0
RES
Input high level voltage
1
2
3
CE, CL, DI,
KI1 to KI5
0.4V
0.6V
0.4V
IH
IH
IH
DD
DD
V
V
DD
DD
DD
DD
DD
OSC: External clock operating mode
V
DD
0
RES
Input low level voltage
1
CE, CL, DI,
KI1 to KI5
0.2V
0.2V
0.2V
IL
IL
IL
2
V
0
0
3
OSC: External clock operating mode
OSC: RC oscillation operating mode
Recommended external
R
C
f
OSC
39
kΩ
resistor for RC oscillation
Recommended external
OSC: RC oscillation operating mode
OSC
1000
38
pF
capacitor for RC oscillation
Guaranteed range of RC oscillation
OSC: RC oscillation operating mode
19
10
76
76
kHz
kHz
OSC
CK
External clock operating frequency
f
OSC: External clock operating mode
[Figure4]
38
External clock duty cycle
D
OSC: External clock operating mode
[Figure4]
CK
30
50
70
%
Data setup time
Data hold time
t
CL, DI
CL, DI
CE, CL
CE, CL
CE, CL
CL
[Figure2], [Figure3]
[Figure2], [Figure3]
[Figure2], [Figure3]
[Figure2], [Figure3]
[Figure2], [Figure3]
[Figure2], [Figure3]
[Figure2], [Figure3]
[Figure2], [Figure3]
[Figure2], [Figure3]
160
160
160
160
160
160
160
ns
ns
ns
ns
ns
ns
ns
ns
ns
ds
t
t
t
t
t
t
t
t
t
dh
CE wait time
cp
cs
ch
φH
φL
r
CE setup time
CE hold time
High level clock pulse width
Low level clock pulse width
Rise time
CL
CE, CL, DI
CE, CL, DI
160
160
Fall time
f
DO output deley time
DO R =4.7kΩ C =10pF *1
PU
dc
L
1.5
1.5
μs
μs
[Figure2], [Figure3]
DO rise time
t
DO R =4.7kΩ C =10pF *1
dr
PU
L
[Figure2], [Figure3]
Note: *1 Since the DO pin is an open-drain output, these times depend on the values of the pull-up resistor
and the load capacitance C .
R
PU
L
No.A1391-2/36
LC75886PW
Electrical Characteristics for the Allowable Operating Ranges
Ratings
typ
Parameter
Symbol
Pin
Conditions
Unit
min
max
RES
Hysteresis
V
V
V
I
1
2
CE, CL, DI,
KI1 to KI5
0.03V
H
DD
V
V
0.1V
H
DD
2.3
Power-down detection voltage
Input high level current
2.0
2.6
DET
1
RES
RES
CE, CL, DI,
OSC
V =6.0V
I
5.0
5.0
IH
μA
μA
I
2
V =V : External clock
DD
IH
I
operating mode
Input low level current
I
I
1
2
CE, CL, DI,
OSC
V =0V
I
-5.0
-5.0
IL
V =0V: External clock
I
IL
operating mode
Input floating voltage
Pull-down resistance
V
KI1 to KI5
KI1 to KI5
DO
0.05V
V
IF
DD
RPD
V
=5.0V
DD
50
100
-0.5
250
kΩ
Output off leakage
current
I
V
=6.0V
O
OFFH
6.0
μA
Output high level voltage
V
V
V
V
V
V
V
V
V
V
1
2
3
4
KS1 to KS6
P1 to P5
I
=-500μA
=-1mA
=-20μA
=-100μA
=25μA
=1mA
V
V
V
V
-1.0
-0.9
-0.9
-0.9
0.2
V
V -0.2
DD
OH
OH
OH
OH
O
DD
DD
DD
DD
DD
I
I
I
I
I
I
I
I
O
O
O
O
O
O
O
O
V
S1 to S57
COM1 to COM4
KS1 to KS6
P1 to P5
Output low level voltage
1
0.5
0.1
1.5
0.9
0.9
0.9
0.3
OL
OL
OL
OL
OL
2
3
4
5
S1 to S57
COM1 to COM4
DO
=20μA
=100μA
=1mA
V
Output middle level voltage
*2
1
2
3
4
S1 to S57
1/3 bias I =±20μA
2/3V
2/3V
MID
MID
MID
MID
OSC
O
DD
-0.9
DD
+0.9
V
V
V
S1 to S57
1/3 bias I =±20μA
1/3V
1/3V
DD
O
DD
-0.9
+0.9
V
COM1 to COM4
COM1 to COM4
OSC
1/3 bias I =±100μA
2/3V
2/3V
DD
O
DD
-0.9
+0.9
1/3 bias I =±100μA
1/3V
1/3V
DD
O
DD
-0.9
+0.9
Oscillator frequency
Current drain
f
R
=39kΩ, C =1000pF
OSC OSC
30.4
38
45.6
100
kHz
RC oscillation operating mode
Sleep mode
I
I
1
V
DD
DD
2
V
V
=6.0V, Output open,
DD
DD
DD
RC oscillation operating mode,
450
550
900
f
=38kHz
OSC
μA
I
3
V
V =6.0V, Output open,
DD
External clock operating mode,
DD
DD
1100
f
=38kHz, V 3=0.5V
IH
,
DD
CK
V
3=0.1V
DD
IL
Note: *2. Excluding the bias voltage generation divider resistor built into the V 1 and V 2. (See [Figure 1])
DD DD
V
DD
V
V
1
2
DD
To the common and segment drivers
Excluding these resistors
DD
[Figure 1]
No.A1391-3/36
LC75886PW
1. When CL is stopped at the low level
V
1
IH
CE
V
1
IL
t
t
φH
φL
V
1
IH
CL 50%
V
1
IL
t
t
f
r
t
t
t
ch
cp
cs
V
1
IH
DI
V
1
IL
t
t
t
t
dr
ds
dh
dc
DO
D0
D1
[Figure 2]
2. When CL is stopped at the high level
V
1
IH
CE
V
1
IL
t
t
φL
φH
V
1
IH
50%
CL
DI
V
1
IL
t
t
f
r
t
t
t
ch
cp
cs
V
V
1
IH
1
IL
t
t
dh
ds
DO
D0
D1
t
t
dr
dc
[Figure 3]
3. OSC pin clock timing in external clock operating mode
1
t
t
CKL
CKH
f
=
[kHz]
CK
t
t
+t
CKH CKL
V
3
IH
50%
IL
OSC
t
V
3
CKH
D
=
×100[%]
CK
+t
CKH CKL
[Figure 4]
No.A1391-4/36
LC75886PW
Package Dimensions
unit : mm (typ)
3220
14.0
12.0
0.135
1.25
1.25
0.5
60
41
61
40
21
80
1
20
0.2
0.5
0.5
SQFP80(12X12)
Pin Assignment
60
50
41
KS6
KI1
KI2
KI3
KI4
KI5
61
40
S42
S41
S40
S39
S38
S37
S36
S35
S34
S33
S32
S31
S30
S29
S28
S27
S26
S25
S24
S23
S57/P5
V
DD
V
V
1
2
DD
DD
70
LC75886PW
V
30
SS
TEST
OSC
RES
DO
CE
CL
DI
P1/S1
P2/S2
80
21
1
10
20
Top view
No.A1391-5/36
LC75886PW
Block Diagram
V
DD
GENERAL
PURPOSE
PORT
SEGMENT DRIVER & LATCH
V
1
DD
DD
COMMON
DRIVER
V
2
V
SS
CLOCK
GENERATOR
CONTROL
REGISTER
OSC
DO
SHIFT REGISTER
CCB
DI
CL
CE
INTERFACE
KEY BUFFER
RES
KEY SCAN
V
DD
VDET
TEST
No.A1391-6/36
LC75886PW
Pin Functions
Handling
when
Symbol
Pin No.
Function
Active
I/O
O
unused
Segment outputs for displaying the display data transferred by serial data
input. The S1/P1 to S4/P4 pins can be used as general-purpose output ports
under serial data control.
S1/P1 to S4/P4
S5 to S53
79,80,1,2
3 to 51
-
-
OPEN
OPEN
Common driver outputs.
COM1 to COM3
COM4/S54
52 to 54
55
The frame frequency is f [Hz].
O
O
The COM4/S54 pin can be used as a segment output in 1/3 duty.
Key scan outputs. Although normal key scan timing lines require diodes to
be inserted in the timing lines to prevent shorts, since these outputs are
unbalanced CMOS transistor outputs, these outputs will not be damaged by
shorting when these outputs are used to form a key matrix. The KS1/S55
and KS2/S56 pins can be used as segment outputs when so specified by the
control data.
KS1/S55
KS2/S56
56
57
-
O
OPEN
KS3 to KS6
58 to 61
Key scan inputs.
KI1 to KI5
P5/S57
62 to 66
67
H
-
I
GND
These pins have built-in pull-down resistors.
General-purpose output port.
This pin can be used as clock output port or segment output port under
serial data control.
O
OPEN
Oscillator connections. An oscillator circuit is formed by connecting an
external resistor and capacitor at this pin. This pin can also be used as the
external clock input pin if the external clock operating mode is selected with
the control data.
OSC
73
-
I/O
V
DD
Serial data interface connections to the controller. Note that DO, being an
open-drain output, requires a pull-up resistor.
CE: Chip enable
CE
CL
76
77
H
I
I
GND
CL: Synchronization clock
DI
78
75
-
-
I
DI: Transfer data
DO
O
OPEN
DO: Output data
Reset signal input
• RES=Low·····Display off
- S1/P1 to S4/P4, KS1/S55, KS2/S56=Low
(These pins are forcibly set to the segment output port function and
fixed at the low level.)
- S5 to S53=Low
- COM1 to COM3=Low
- COM4/S54=Low
(This pin is forcibly set to the common output function and fixed at the
low level.)
- P5/S57=Low
(This pin is forcibly set to the general-purpose output port function and
fixed at the low level.)
RES
74
L
I
V
DD
- KS3 to KS6=Low
- Key scanning disabled
- All the key data is reset to low.
- OSC=”Z”(High impedance)
- RC oscillation stopped
- Inhibits external clock input
• RES=High ···· Display on
- General-purpose output port state setting is enabled
- Key scanning is enabled.
- RC oscillation enabled (RC oscilltator operating mode)
- Enables external clock input (external clock operating mode)
However, serial data can be transferred when the RES pin is low
TEST
72
69
70
68
71
This pin must be connected to ground.
-
-
-
-
-
I
I
-
V
V
1
Used to apply the LCD drive 2/3 bias voltage externally.
Used to apply the LCD drive 1/3 bias voltage externally.
Power supply connections. Provide a voltage of between 4.5 to 6.0V.
Power supply connections. Connect to ground.
OPEN
DD
2
I
OPEN
DD
V
-
-
-
-
DD
V
SS
No.A1391-7/36
LC75886PW
Serial Data Input
1. 1/4 duty
(1) When CL is stopped at the low level
CE
CL
DI
0
1
0
0
0
0
1
0
D1 D2
D47 D48 D49 D50 D51 D52 D53 D54 D55 D56
0
0
0
0
OC
PC51 KSC
K1 P0 P1 P2 SC
S0 S1 K0
0
0
0
PC50
Display data (56 bits)
Control data (13 bits)
B0 B1 B2 B3 A0 A1 A2 A3
DD
(3 bits)
DO
0
1
0
0
0
0
1
0 D57 D58
D103 D104 D105 D106 D107
0
0
FC0 FC1 FC2
0
0
1
D108 D109 D110 D111 D112
0 0 0 0 0 0 0
Display data (56 bits)
Control data (13 bits)
DD
B0 B1 B2 B3 A0 A1 A2 A3
(3 bits)
0
1
0
0
0
0
1
0
D113 D114
D159 D160 D161 D162 D163
0
0
0
0
0
0
1
0
D164 D165 D166 D167 D168
0
0
0 0 0 0 0
Display data (56 bits)
Fixed data (13 bits)
B0 B1 B2 B3 A0 A1 A2 A3
DD
(3 bits)
0
1
0
0
0
0
1
0
D169 D170
D215 D216 D217 D218 D219
0
0
0
0
0
0
1
1
D220 D221 D222 D223 D224
0
0
0 0 0 0 0
Display data (56 bits)
Fixed data (13 bits)
DD
B0 B1 B2 B3 A0 A1 A2 A3
(3 bits)
Note: B0 to B3, A0 to A3 ·········CCB address
DD ·································Direction data
No.A1391-8/36
LC75886PW
(2) When CL is stopped at the high level
CE
CL
DI
0
1
0
0
0
0
1
0
D1 D2
D57 D58
D113 D114
D169 D170
D47 D48 D49 D50 D51 D52 D53 D54 D55 D56
0
0
0
0
OC PC50 PC51 KSC
K1 P0 P1 P2 SC
0
0
0
S0 S1 K0
DD
B0 B1 B2 B3 A0 A1 A2 A3
Display data (56 bits)
Control data (13 bits)
(3 bits)
DO
0
1
0
0
0
0
1
0
D103 D104 D105 D106 D107
0
0
FC0 FC1 FC2
0
0
1
D108 D109 D110 D111 D112
0
0
0
0
0
0
0 0 0 0 0
B0 B1 B2 B3 A0 A1 A2 A3
DD
Display data (56 bits)
Control data (13 bits)
(3 bits)
0
1
0
0
0
0
1
0
D159 D160 D161 D162 D163
0
0
0
0
0
0
1
0
D164 D165 D166 D167 D168
0 0 0 0 0
DD
B0 B1 B2 B3 A0 A1 A2 A3
Display data (56 bits)
Fixed data (13 bits)
(3 bits)
0
1
0
0
0
0
1
0
D215 D216 D217 D218 D219
0
0
0
0
0
0
1
1
D220 D221 D222 D223 D224
0 0 0 0 0
DD
B0 B1 B2 B3 A0 A1 A2 A3
Display data (56 bits)
Fixed data (13 bits)
(3 bits)
Note: B0 to B3, A0 to A3 ·········CCB address
DD ·································Direction data
• CCB address ···············“42H”
• D1 to D224 ·················Display data
• OC ······························RC oscillator operating mode/external clock operationg mode switching control data
• PC50, PC51·················General-purpose output port/clock output port/segment output port switching control data
• KSC ····························Key scan operation enabled/disabled state setting control data
• S0, S1··························Sleep control data
• K0, K1 ························Key scan output/segment output switching control data
• P0 to P2·······················Segment output port/general-purpose output port switching control data
• SC·······························Segment on/off control data
• FC0 to FC2 ·················Common and segment output waveform frame frequency control data
No.A1391-9/36
LC75886PW
2. 1/3 duty
(1) When CL is stopped at the low level
CE
CL
DI
0
1
0
0
0
0
1
0
D1 D2
D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 OC PC50 PC51 KSC S0 S1 K0 K1 P0 P1 P2 SC
1
0
0
DD
Display data (57 bits)
Control data (12 bits)
B0 B1 B2 B3 A0 A1 A2 A3
(3 bits)
DO
0
1
0
0
0
0
1
0
D58 D59
D104 D105 D106 D107 D108
0
0
FC0 FC1 FC2
1
0
1
D109 D110 D111 D112 D113 D114
0 0 0 0 0 0 0
Display data (57 bits)
Control data (12 bits)
DD
B0 B1 B2 B3 A0 A1 A2 A3
(3 bits)
0
1
0
0
0
0
1
0
D115
D116
D161 D162 D163 D164 D165
0
0
0
0
0
1
1
0
D166 D167 D168 D169 D170 D171
0 0 0 0 0 0 0
Display data (57 bits)
Fixed data (12 bits)
B0 B1 B2 B3 A0 A1 A2 A3
DD
(3 bits)
Note: B0 to B3, A0 to A3 ········ CCB address
DD ································· Direction data
No.A1391-10/36
LC75886PW
(2) When CL is stopped at the high level
CE
CL
DI
0
1
0
0
0
0
1
0
D1 D2
D58 D59
D115 D116
D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 OC PC50 PC51 KSC
K1 P0 P1 P2 SC
1
0
0
S0 S1 K0
B0 B1 B2 B3 A0 A1 A2 A3
Display data (57 bits)
Control data (12 bits)
DD
(3 bits)
DO
0
1
0
0
0
0
1
0
D104 D105 D106 D107 D108
0
0
FC0 FC1 FC2
1
0
1
D109 D110 D111 D112 D113 D114
0 0 0 0 0 0 0
Display data (57 bits)
Control data (12 bits)
B0 B1 B2 B3 A0 A1 A2 A3
DD
(3 bits)
0
1
0
0
0
0
1
0
D161 D162 D163 D164 D165
0
0
0
0
0
1
1
0
D166 D167 D168 D169 D170 D171
0 0 0 0 0 0 0
Display data (57 bits)
Fixed data (12 bits)
B0 B1 B2 B3 A0 A1 A2 A3
DD
(3 bits)
Note: B0 to B3, A0 to A3 ········· CCB address
DD ································· Direction data
• CCB address ·········· “42H”
• D1 to D171 ············· Display data
• OC ························· RC oscillator operating mode/external clock operationg mode switching control data
• PC50, PC51 ············ General-purpose output port/clock output port/segment output port switching control data
• KSC ······················· Key scan operation enabled/disabled state setting control data
• S0, S1 ····················· Sleep control data
• K0, K1 ··················· Key scan output/segment output switching control data
• P0 to P2 ·················· Segment output port/general-purpose output port switching control data
• SC ·························· Segment on/off control data
• FC0 to FC2 ············· Common and segment output waveform frame frequency control data
No.A1391-11/36
LC75886PW
Control Data Functions
1. OC … RC oscillator operating mode/external clock operating mode switching control data
This control data bit selects the OSC pin function (RC oscillator operating mode or external clock operating mode)
OC
OSC pin function
0
RC oscillator operating mode
External clock operating mode
1
Note: If RC oscillator operating mode is selected, connect an external resistor R
to the OSC pin.
and an external capacitor C
OSC
OSC
2. PC50, PC51 … General-purpose output port/clock output port/segment output port switching control data
These control data bits swithes the functions of the P5/S57 output pin between the general-purpose output port, the
clock output port, and the segment output port.
Control data
The state of P5/S57 output pin
PC50
PC51
0
1
0
1
0
0
1
1
General-purpose output port (P5) (”L” level output)
General-purpose output port (P5) (“H” level output)
Clock output port (P5) (Clock frequency is f /2 or f /2)
OSC CK
Segment output port (S57)
Note: If the sleep mode is set, the P5/S57 output pin can not be used as the clock output port.
3. KSC … Key scan operation enabled/disabled state setting control data
This control data bit enables or disables key scan operation.
KSC
Key scan operating state
Key scan operation enabled
0
(A key scan operation is performed if any key on the lines corresponding to KS1 to KS6 pin which is set
high is pressed.)
Key scan operation disabled
(No key scan operation is performed, even if any of the keys in the key matrix are pressed.
If this state is set up, the key data is forcibly reset to 0 and the key data read request is also cleared.
(DO is set high.))
1
4. S0, S1 … Sleep control data
These control data bits switch between normal mode and sleep mode, and set the states of the KS1 to KS6 key scan
output during key scan standby.
OSC pin state
(RC oscillator
or acceptance
of the external
clock signal)
Control data
Output pin states during key scan standby
Segment
output /
Common
output
Mode
S0
S1
KS1
KS2
KS3
KS4
KS5
KS6
0
0
Normal
Sleep
Sleep
Sleep
Operating
Stopped
Stopped
Stopped
Operating
H
L
H
L
H
L
H
L
H
L
H
H
H
H
0
1
1
1
0
1
L
L
L
L
L
L
L
H
H
H
H
H
H
Note: This assumes that the KS1/S55 and KS2/S56 output pins are selected for key scan output.
No.A1391-12/36
LC75886PW
5. K0, K1 … Key scan output/segment output switching control data
These control data bits switch the functions of the KS1/S55 and KS2/S56 output pins between the key scan output
and the segment output.
Control data
Output pin state
Maximum number
of input keys
K0 K1
KS1/S55
KS2/S56
KS2
0
0
KS1
S55
S55
30
25
20
0
1
1
KS2
Note: KSn (n=1 or 2): Key scan output
Sn (n=55 or 56): Segment output
X
S56
X : don't care
6. P0 to P2 … Segment output port/general-purpose output port switching control data
These control data bits switch the functions of the S1/P1 to S4/P4 output pins between the segment output port and
the general-purpose output port.
Control data
Output pin state
P0
0
P1
0
P2
0
S1/P1
S1
S2/P2
S3/P3
S3
S4/P4
S4
S2
S2
P2
P2
P2
0
0
1
P1
S3
S4
0
1
0
P1
S3
S4
Note: Sn (n=1 to 4): Segment output port
Pn (n=1 to 4): General-purpose output port
0
1
1
P1
P3
S4
1
0
0
P1
P3
P4
The table below lists the correspondence between the display data and the output pins when these pins are selected to
be general-purpose output ports.
Correspondence display data
Output pin
1/4 duty
1/3 duty
S1/P1
S2/P2
S3/P3
S4/P4
D1
D1
D5
D4
D9
D7
D13
D10
For example, if the circuit is operated in 1/4 duty and the S4/P4 output pin is selected to be a general-purpose output
port, the S4/P4 output pin will output a high level when the display data D13 is 1, and will output a low level when
D13 is 0.
7. SC … Segment on/off control data
This control data bit controls the on/off state of the segments.
SC
Display state
0
On
Off
1
However, note that when the segments are turned off by setting SC to 1, the segments are turned off by outputting
segment off waveforms from the segment output pins.
8. FC0 to FC2 … Common and segment output waveform frame frequency control data
These control data bits set the common and segment output waveform frequency.
Control data
Frame frequency
[Hz]
f
FC0
1
FC1
1
FC2
0
O
f
f
f
f
f
/768, f /768
CK
OSC
OSC
OSC
OSC
OSC
1
1
1
/576, f /576
CK
0
0
0
/384, f /384
CK
0
0
1
/288, f /288
CK
0
1
0
/192, f /192
CK
No.A1391-13/36
LC75886PW
Display Data and Output Pin Correspondence
1. 1/4 duty
Output pin
S1/P1
S2/P2
S3/P3
S4/P4
S5
COM1
D1
COM2
D2
COM3
D3
COM4
D4
Output pin
S29
COM1
D113
D117
D121
D125
D129
D133
D137
D141
D145
D149
D153
D157
D161
D165
D169
D173
D177
D181
D185
D189
D193
D197
D201
D205
D209
D213
D217
D221
COM2
D114
D118
D122
D126
D130
D134
D138
D142
D146
D150
D154
D158
D162
D166
D170
D174
D178
D182
D186
D190
D194
D198
D202
D206
D210
D214
D218
D222
COM3
D115
D119
D123
D127
D131
D135
D139
D143
D147
D151
D155
D159
D163
D167
D171
D175
D179
D183
D187
D191
D195
D199
D203
D207
D211
D215
D219
D223
COM4
D116
D120
D124
D128
D132
D136
D140
D144
D148
D152
D156
D160
D164
D168
D172
D176
D180
D184
D188
D192
D196
D200
D204
D208
D212
D216
D220
D224
D5
D6
D7
D8
S30
D9
D10
D14
D18
D22
D26
D30
D34
D38
D42
D46
D50
D54
D58
D62
D66
D70
D74
D78
D82
D86
D90
D94
D98
D102
D106
D110
D11
D15
D19
D23
D27
D31
D35
D39
D43
D47
D51
D55
D59
D63
D67
D71
D75
D79
D83
D87
D91
D95
D99
D103
D107
D111
D12
D16
D20
D24
D28
D32
D36
D40
D44
D48
D52
D56
D60
D64
D68
D72
D76
D80
D84
D88
D92
D96
D100
D104
D108
D112
S31
D13
D17
D21
D25
D29
D33
D37
D41
D45
D49
D53
D57
D61
D65
D69
D73
D77
D81
D85
D89
D93
D97
D101
D105
D109
S32
S33
S6
S34
S7
S35
S8
S36
S9
S37
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S38
S39
S40
S41
S42
S43
S44
S45
S46
S47
S48
S49
S50
S51
S52
S53
KS1/S55
KS2/S56
P5/S57
Note: This is for the case where the S1/P1 to S4/P4, KS1/S55, KS2/S56, P5/S57 output pins are selected for use as
segment outputs.
For example, the table below lists the segment output states for the S11 output pin.
Display data
Output pin state (S11)
D41
0
D42
0
D43
0
D44
0
The LCD segments for COM1, COM2, COM3 and COM4 are off.
The LCD segment for COM4 is on.
0
0
0
1
The LCD segment for COM3 is on.
0
0
1
0
The LCD segments for COM3 and COM4 are on.
The LCD segment for COM2 is on.
0
0
1
1
0
1
0
0
The LCD segments for COM2 and COM4 are on.
The LCD segments for COM2 and COM3 are on.
The LCD segments for COM2, COM3 and COM4 are on.
The LCD segment for COM1 is on.
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
The LCD segments for COM1 and COM4 are on.
The LCD segments for COM1 and COM3 are on.
The LCD segments for COM1, COM3 and COM4 are on.
The LCD segments for COM1 and COM2 are on.
The LCD segments for COM1, COM2 and COM4 are on.
The LCD segments for COM1, COM2 and COM3 are on.
The LCD segments for COM1, COM2, COM3 and COM4 are on.
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
No.A1391-14/36
LC75886PW
2. 1/3 duty
Output pin
COM1
D1
COM2
D2
COM3
Output pin
S31
COM1
D91
COM2
D92
COM3
D93
S1/P1
S2/P2
S3/P3
S4/P4
S5
D3
D4
D5
D6
S32
D94
D95
D96
D7
D8
D9
S33
D97
D98
D99
D10
D13
D16
D19
D22
D25
D28
D31
D34
D37
D40
D43
D46
D49
D52
D55
D58
D61
D64
D67
D70
D73
D76
D79
D82
D85
D88
D11
D14
D17
D20
D23
D26
D29
D32
D35
D38
D41
D44
D47
D50
D53
D56
D59
D62
D65
D68
D71
D74
D77
D80
D83
D86
D89
D12
D15
D18
D21
D24
D27
D30
D33
D36
D39
D42
D45
D48
D51
D54
D57
D60
D63
D66
D69
D72
D75
D78
D81
D84
D87
D90
S34
D100
D103
D106
D109
D112
D115
D118
D121
D124
D127
D130
D133
D136
D139
D142
D145
D148
D151
D154
D157
D160
D163
D166
D169
D101
D104
D107
D110
D113
D116
D119
D122
D125
D128
D131
D134
D137
D140
D143
D146
D149
D152
D155
D158
D161
D164
D167
D170
D102
D105
D108
D111
D114
D117
D120
D123
D126
D129
D132
D135
D138
D141
D144
D147
D150
D153
D156
D159
D162
D165
D168
D171
S35
S6
S36
S7
S37
S8
S38
S9
S39
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S40
S41
S42
S43
S44
S45
S46
S47
S48
S49
S50
S51
S52
S53
COM4/S54
KS1/S55
KS2/S56
P5/S57
Note: This is for the case where the S1/P1 to S4/P4, COM4/S54, KS1/S55, KS2/S56, P5/S57 output pins are selected
for use as segment outputs.
For example, the table below lists the segment output states for the S11 output pin.
Display data
Output pin state (S11)
D31
0
D32
0
D33
0
The LCD segments for COM1, COM2, and COM3 are off.
The LCD segment for COM3 is on.
0
0
1
0
1
0
The LCD segment for COM2 is on.
0
1
1
The LCD segments for COM2 and COM3 are on.
The LCD segment for COM1 is on.
1
0
0
1
0
1
The LCD segments for COM1 and COM3 are on.
The LCD segments for COM1 and COM2 are on.
The LCD segments for COM1, COM2 and COM3 are on.
1
1
0
1
1
1
No.A1391-15/36
LC75886PW
Serial Data Output
1. When CL is stopped at the low level
CE
CL
DI
1
1
0
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
DO
X
KD1 KD2
KD27 KD28 KD29 KD30 SA
Output data
X: don’t care
Note: B0 to B3, A0 to A3 … CCB address
2. When CL is stopped at the high level
CE
CL
DI
1
1
0
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2
A3
DO
X
KD1 KD2 KD3
KD28 KD29 KD30 SA
X
Output data
X: don’t care
Note: B0 to B3, A0 to A3 … CCB address
• CCB address ······ “43H”
• KD1 to KD30 ····· Key data
• SA ······················ Sleep acknowledge data
Note: If a key data read operation is executed when DO is high (DO does not generate a key data read request output),
the read key data (KD1 to KD30) and sleep acknowledge data (SA) will be invalid.
Output Data
1. KD1 to KD30 … Key data
When a key matrix of up to 30 keys is formed from the KS1 to KS6 output pins and KI1 to KI5 input pins and one of
those keys is pressed, the key output data corresponding to that key will be set to 1. The table shows the relationship
between those pins and the key data bits.
KI1
KI2
KI3
KI4
KI5
KS1/S55
KS2/S56
KS3
KD1
KD2
KD3
KD4
KD5
KD6
KD7
KD8
KD9
KD10
KD15
KD20
KD25
KD30
KD11
KD16
KD21
KD26
KD12
KD17
KD22
KD27
KD13
KD18
KD23
KD28
KD14
KD19
KD24
KD29
KS4
KS5
KS6
When the KS1/S55 and KS2/S56 output pins are selected to be segment outputs by control data bits K0 and K1 and a
key matrix of up to 20 keys is formed using the KS3 to KS6 output pins and the KI1 to KI5 input pins, the KD1 to
KD10 key data bits will be set to 0.
2. SA … Sleep acknowledge data
This output data bit is set to the state when the key was pressed. Also, while DO will be low in this case, if serial
data is input and the mode is set (to normal or sleep mode) during this period, that mode will be set. SA will be 1 in
sleep mode and 0 in normal mode.
No.A1391-16/36
LC75886PW
Sleep Mode Functions
Sleep mode is set up by setting S0 or S1 in the control data to 1. When sleep mode is set up, both the segment and
common outputs will go to the low level. In RC oscillator operating mode (OC=0), the oscillator on the OSC pin will
stop (although it will operate during key scan operations), and in exeternal clock operating mode (OC=1), acceptance of
the external clock signal on the OSC pin will stop (although the clock signal will be accepted during key scan
operations). Thus this mode reduces power consumption. However, the S1/P1 to S4/P4, P5/S57 output pins can be used
as general-purpose output ports under control of the P0 to P2, PC50 and PC51 bits in the control data even in sleep
mode (The P5/S57 output pin can not be used as clock output port). Sleep mode is cancelled by setting both S0 and S1
in control data to 0.
Key Scan Operation Functions
1. Key scan timing
The key scan period is 288T[s]. To reliably determine the on/off state of the keys, the LC75886PW scans the keys
twice and determines that a key has been pressed when the key data agrees. It outputs a key data read request (a low
level on DO) 615T[s] after starting a key scan. If the key data does not agree and a key was pressed at that point, it
scans the keys again. Thus the LC75886PW cannot detect a key press shorter than 615T[s].
KS1
KS2
KS3
KS4
KS5
KS6
*3
*3
*3
*3
*3
1
1
*3
*3
*3
*3
*3
2
2
3
3
4
4
5
5
1
1
6
6
T=
=
f
f
OSC
CK
Key on
576T[s]
Note: *3. These are set to the high or low level by the S0 and S1 bits in the control data.
Key scan output signals are not output from pins that are set to the low level.
No.A1391-17/36
LC75886PW
2. Normal mode, when key scan operations are enabled
(1) The KS1 to KS6 pins are set high. (See the description of the control data.)
(2) When a key is pressed, a key scan is started and the keys are scanned until all keys are released. Multiple key
presses are recognized by determining whether multiple key data bits are set.
(3) If a key is pressed for longer than 615T[s] (Where T=1/f
or T=1/f ), the LC75886PW outputs a key data read
OSC
CK
request (a low level on DO) to the controller. The controller acknowledges this request and reads the key data.
However, if CE is high during a serial data transfer, DO will be set high.
(4) After the controller reads the key data, the key data read request is cleared (DO is set high) and the LC75886PW
performs another key scan. Also note that DO, being an open-drain output, requires a pull-up resistor (between 1 and
10kΩ).
Key input 1
Key input 2
Key scan
615T[s]
615T[s]
615T[s]
CE
DI
Key
Key
Key
Serial data transfer
(KSC=0)
Serial data transfer
(KSC=0)
Serial data transfer
(KSC=0)
address(43H)
address(43H)
address(43H)
DO
Key data read
Key data read
Key data read
Key data read request
Key data read request
Key data read request
1
1
T=
f
=
f
OSC
CK
3. Sleep mode, when key scan operations are enabled
(1) The KS1 to KS6 pins are set to high or low level by the S0 and S1 bits in the control data.
(See the description of the control data.)
(2) If a key on one of the lines corresponding to a KS1 to KS6 pin which is set high is pressed, the oscillator on the OSC
pins starts in RC oscillator operating mode (the IC starts accepting the external clock signal in external clock
operating mode) and a key scan is performed. Keys are scanned until all keys are released.
Multiple key presses are recognized by determining whether multiple key data bits are set.
(3) If a key is pressed for longer than 615T[s] (Where T=1/f
or T=1/f ), the LC75886PW outputs a key data read
OSC
CK
request (a low level on DO) to the controller. The controller acknowledges this request and reads the key data.
However, if CE is high during a serial data transfer, DO will be set high.
(4) After the controller reads the key data, the key data read request is cleared (DO is set high) and the
LC75886PW performs another key scan. However, this does not clear sleep mode. Also note that DO, being an
open-drain output, requires a pull-up resistor (between 1 and 10kΩ).
(5) Sleep mode key scan example
Example: S0=0, S1=1 (Sleep with only KS6 high)
“L” KS1
“L” KS2
When any one of these keys is pressed, the
oscillator on the OSC pins starts in RC oscillator
operating mode (the IC starts accepting the external
clock signal in external clock operating mode) and a
key scan operation is performed.
“L” KS3
“L” KS4
“L” KS5
“H” KS6
*4
KI1
KI2
KI3
KI4
KI5
Note: *4. These diodes are required to reliably recognize multiple key presses on the KS6 line when sleep mode state
with only KS6 high, as in the above example. That is, these diodes prevent incorrect operations due to sneak
currents in the KS6 key scan output signal when keys on the KS1 to KS5 lines are pressed at the same time.
No.A1391-18/36
LC75886PW
Key input
(KS6 line)
Key scan
CE
615T[s]
615T[s]
Key
Key
Serial data transfer
(KSC=0)
Serial data transfer
(KSC=0)
Serial data transfer
(KSC=0)
address(43H)
address(43H)
1
1
T=
=
DI
f
f
OSC
CK
DO
Key data read
Key data read
Key data read request
Key data read request
4. Normal/sleep mode, when key scan operations are disabled
(1) The KS1 to KS6 pins are set to high or low level by the S0 and S1 bits in the control data.
(2) No key scan operation is performed, whichever key is pressed.
(3) If the key scan disabled state (KSC=1 in the control data) is set during a key scan, the key scan is stopped.
(4) If the key scan disabled state (KSC=1 in the control data) is set when a key data read request (a low level on DO) is
output to the controller, all the key data is set to 0 and the key data read request is cleared (DO is set high).
Note that DO, being an open-drain output, requires a pull-up resister (between 1 to 10kΩ).
(5) The key scan disabled state is cleared by setting KSC in the control data to 0.
Key input 1
Key input 2
Key scan
615T[s]
615T[s]
CE
DI
Key
Serial data transfer Serial data transfer
(KSC=0) (KSC=1)
Serial data transfer
(KSC=0)
Serial data transfer
(KSC=1)
Serial data transfer
(KSC=0)
address(43H)
DO
Key data read
Key data read request
Key data read request
1
1
T=
=
f
f
OSC
CK
Multiple Key Presses
Although the LC75886PW is capable of key scanning without inserting diodes for dual key presses, triple key presses
on the KI1 to KI5 input pin lines, or multiple key presses on the KS1 to KS6 output pin lines, multiple presses other
than these cases may result in keys that were not pressed recognized as having been pressed. Therefore, a diode must be
inserted in series with each key. Applications that do not recognize multiple key presses of three or more keys should
check the key data for three or more 1 bits and ignore such data.
No.A1391-19/36
LC75886PW
f [Hz]
O
1/4 Duty, 1/3 Bias Drive Technique
V
V
V
DD
DD
DD
1
2
COM1
0V
V
V
V
DD
DD
DD
1
2
COM2
COM3
COM4
0V
V
V
V
DD
DD
DD
1
2
0V
V
V
V
DD
DD
DD
1
2
0V
V
V
V
DD
DD
DD
LCD driver output when all LCD
segments corresponding to COM1,
COM2, COM3, and COM4 are turned off.
1
2
0V
V
V
V
DD
DD
DD
LCD driver output when only
LCD segments corresponding to
COM1 are on.
1
2
0V
V
V
V
DD
DD
DD
LCD driver output when only
LCD segments corresponding to
COM2 are on.
1
2
0V
V
V
V
DD
DD
DD
LCD driver output when
LCD segments corresponding to
COM1 and COM2 are on.
1
2
0V
V
V
V
DD
DD
DD
LCD driver output when only
LCD segments corresponding to
COM3 are on.
1
2
0V
V
V
V
DD
DD
DD
LCD driver output when
LCD segments corresponding to
COM1 and COM3 are on.
1
2
0V
V
V
V
DD
DD
DD
LCD driver output when
LCD segments corresponding to
COM2 and COM3 are on.
1
2
0V
V
V
V
DD
DD
DD
LCD driver output when
LCD segments corresponding to
COM1, COM2, and COM3 are on.
1
2
0V
V
V
V
DD
DD
DD
LCD driver output when only
LCD segments corresponding to
COM4 are on.
1
2
0V
V
V
V
DD
DD
DD
LCD driver output when
LCD segments corresponding to
COM2 and COM4 are on.
1
2
0V
V
V
V
DD
DD
DD
LCD driver output when all
LCD segments corresponding to
COM1, COM2, COM3, and COM4 are on.
1
2
0V
Control data
Common and segment output waveform
frame frequency f [Hz]
O
FC0
1
FC1
1
FC2
0
f
f
f
f
f
/768, f /768
CK
OSC
OSC
OSC
OSC
OSC
1
1
1
/576, f /576
CK
0
0
0
/384, f /384
CK
0
0
1
/288, f /288
CK
0
1
0
/192, f /192
CK
No.A1391-20/36
LC75886PW
f [Hz]
O
1/3 Duty, 1/3 Bias Drive Technique
V
V
V
DD
DD
DD
1
2
COM1
0V
V
V
V
DD
DD
DD
1
2
COM2
COM3
0V
V
V
V
DD
DD
DD
1
2
0V
V
V
V
DD
DD
DD
LCD driver output when all LCD
segments corresponding to COM1,
COM2, and COM3 are turned off.
1
2
0V
V
V
V
DD
DD
DD
LCD driver output when only
LCD segments corresponding to
COM1 are on.
1
2
0V
V
V
V
DD
DD
DD
LCD driver output when only
LCD segments corresponding to
COM2 are on.
1
2
0V
V
V
V
DD
DD
DD
LCD driver output when
LCD segments corresponding to
COM1 and COM2 are on.
1
2
0V
V
V
V
DD
DD
DD
LCD driver output when only
LCD segments corresponding to
COM3 are on.
1
2
0V
V
V
V
DD
DD
DD
LCD driver output when
LCD segments corresponding to
COM1 and COM3 are on.
1
2
0V
V
V
V
DD
DD
DD
LCD driver output when
LCD segments corresponding to
COM2 and COM3 are on.
1
2
0V
V
V
V
DD
DD
DD
LCD driver output when all
LCD segments corresponding to
COM1, COM2, and COM3 are on.
1
2
0V
Control data
Common and segment output waveform
frame frequency f [Hz]
FC0
1
FC1
1
FC2
0
O
f
f
f
f
f
/768, f /768
CK
OSC
OSC
OSC
OSC
OSC
1
1
1
/576, f /576
CK
0
0
0
/384, f /384
CK
0
0
1
/288, f /288
CK
0
1
0
/192, f /192
CK
No.A1391-21/36
LC75886PW
Clock Signal Output Waveform
Control data
The state of P5/S57 output pin
PC50
0
PC51
1
Clock output port (P5) (Clock frequency is f
/2 or f /2)
CK
OSC
P5
1
Tc/2
Tc=
fc
Tc
Voltage Detection Type Reset Circuit (V
This circuit generates an output signal and resets the system when power is first applied and when the voltage drops, i.e.,
)
DET
when the power supply voltage is less than or equal to the power down detection voltage V , which is 2.3V, typical.
DET
To assure that this function operates reliably, a capacitor must be added to the power supply line so that the power
supply voltage V rise time when the power is first applied and the power supply voltage V fall time when the
DD
DD
voltage drops are both at least 1ms. (See Figure 5 and Figure 6.)
System Reset
The LC75886PW supports the reset methods described below. When a system reset is applied, display is turned off, key
scanning is stopped, all the key data is reset to low, and the general-purpose output ports are fixed at the low level (The
S1/P1 to S4/P4 pins are forcibly set to the segment output port function and fixed at the low level. The P5/S57 pin is
forcibly set to the general-purpose output port function and fixed at the low level). When the reset is cleared, display is
turned on, key scanning is enabled and the general-purpose output ports state setting is enabled.
1. Reset methods
(1) Reset method by the voltage detection type reset circuit (V
)
DET
If at least 1ms is assured as the supply voltage V
by the V
DET
rise time when power is applied, a system reset will be applied
output signal when the supply voltage is brought up. If at least 1 ms is assured as the supply voltage
DD
V
fall time when power drops, a system reset will be applied in the same manner by the V output signal
DD
DET
when the supply voltage is lowered. Note that the reset is cleared at the point when all the serial data (1/4 duty: the
display data D1 to D224 and the control data, 1/3 duty: the display data D1 to D171 and the control data) has been
transferred, i.e., on the fall of the CE signal on the transfer of the last direction data, after all the direction data has
been transferred. (See Figure 5 and Figure 6.)
• 1/4 duty
t1
t2
V
DD
V
V
DET
DET
CE
V
1
IL
Display and control data transfer
D1 to D56
Internal data OC, PC50, PC51, KSC,
S0, S1, K0, K1, P0toP2, SC
Undefined
Undefined
Undefined
Undefined
Defined
Defined
Defined
Defined
Undefined
Undefined
Undefined
Undefined
Internal data (D57 to D112, FC0 to FC2)
Internal data (D113 to D168)
Internal data (D169 to D224)
System reset period
Note: t1≥1 [ms](Power supply voltage V
t2≥1 [ms](Power supply voltage V
rise time)
fall time)
DD
DD
[Figure 5]
No.A1391-22/36
LC75886PW
• 1/3 duty
t1
V
t2
V
DD
V
DET
DET
V
1
CE
IL
Display and control data transfer
D1 to D57
Undefined
Defined
Defined
Defined
Undefined
Undefined
Undefined
Internal data OC, PC50, PC51, KSC,
S0, S1, K0, K1, P0toP2, SC
Undefined
Internal data (D58 to D114, FC0 to FC2)
Undefined
Internal data (D115 to D171)
System reset period
Note: t1≥1 [ms](Power supply voltage V
t2≥1 [ms](Power supply voltage V
rise time)
fall time)
DD
DD
[Figure 6]
(2) Reset method by the
pin
RES
When power is applied, a system reset is applied by setting the
pin low level. The reset is cleared by setting the
RES
pin high level after all the serial data (1/4 duty: the display data D1 to D224 and the control data, 1/3 duty: the
RES
display data D1 to D171 and the control data) has been transferred.
In the allowable operating range (V =4.5 to 6.0V), A reset is applied by setting the
pin low level.
RES
DD
and the reset is cleared by setting the
pin high level
RES
2. Internal block states during the reset period
• CLOCK GENERATOR
A reset is applied and either the OSC pin oscillator is stopped or external clock reception is stopped
• COMMON DRIVER, SEGMENT DRIVER & LATCH
A reset is applied and the display is turned off. However, display data can be input to the latch circuit in this state.
• KEY SCAN
A reset is applied, the circuit is set to the initial state, and at the same time the key scan operation is disabled.
• KEY BUFFER
A reset is applied and all the key data is set to low.
• GENERAL PURPOSE PORT
A reset is applied, the circuit is set to the initial state.
• CCB INTERFACE, SHIFT REGISTER, CONTROL REGISTER
Since serial data transfer is possible, these circuits are not reset.
No.A1391-23/36
LC75886PW
V
DD
GENERAL
PURPOSE
PORT
SEGMENT DRIVER & LATCH
V
1
DD
DD
COMMON
DRIVER
V
2
V
SS
CONTROL
REGISTER
CLOCK
GENERATOR
OSC
DO
SHIFT REGISTER
CCB
INTERFACE
DI
CL
CE
KEY BUFFER
RES
KEY SCAN
V
DD
VDET
TEST
Blocks that are reset
No.A1391-24/36
LC75886PW
3. Pin states during the reset period
Pin
S1/P1 to S4/P4
S5 to S53
State during reset
L *5
L
COM1 to COM3
COM4/S54
KS1/S55, KS2/S56
KS3 to KS6
P5/S57
L
L *6
L *5
L *7
L *8
Z *9
H *10
OSC
DO
Note: *5. These output pins are forcibly set to the segment output function and held low.
*6. This output pin is forcibly set to the common output function and held low.
*7. These output pins are forcibly held fixed at the low level.
*8. This output pin is forcibly set to the general-purpose output port function and held low.
*9. This I/O pin is forcibly set to the high-impedance state.
*10.Since this output pin is an open-drain output, a pull-up resistor of between 1 and 10kΩ is required. This pin
remains high during the reset period even if a key data read operation is performed.
Notes on the OSC Pin Peripheral Circuit
1. RC oscillator operationg mode (Control data bit OC=0)
When RC oscillator operationg mode is selected, an external resistor R
connected between the OSC pin and GND.
and an external capacitor C must be
OSC
OSC
OSC
R
OSC
C
OSC
2. External clock operating mode (Control data bit OC=1 )
When selecting the external clock operating mode, connect a current protection resistor Rg (4.7 to 47kΩ) between the
OSC pin and the external clock output pin (external oscillator). Determine the value of the resistance according to the
maximum allowable current value of the external clock output pin. Also make sure that the waveform of the external
clock is not excessively distorted.
External clock output pin
External oscillator
OSC
Rg
V
DD
Rg
Note: Allowable current value at external clock output pin >
No.A1391-25/36
LC75886PW
Sample Application Circuit 1
1/4 duty, 1/3 bias (for use with normal panels)
(P1)
(P2)
(P3)
(P4)
P5
(Genenal-purpose
output port)
Used with the
backlight controller
or other circuit.
OSC
*13
COM1
COM2
+5V
V
V
DD
SS
*11
COM3
S54/COM4
TEST
P1/S1
P2/S2
P3/S3
P4/S4
S5
V
V
1
2
DD
DD
S53
C≥0.047μF
C
C
(S55)
(S56)
(S57)
S S
5 5
6 5
RES
*12
P5/S57
*15
From the
controller
CE
CL
DI
/
/
K K K K K K K K K
I I
5 4 3 2 1 6 5 4 3
K K
S S
2 1
*15
I
I
I
S S S S
To the controller
DO
To the controller
power supply
*14
Key matrix
(up to 30 keys)
Note: *11. Add a capacitor to the power supply line so that the power supply voltage V
rise time when power is
fall time when power drops are both at least 1ms, as the
DD
applied and the power supply voltage V
DD
LC75886PW is reset by the V
.
DET
pin is not used for system reset, it must be connected to the power supply V
*12. If the
.
RES
*13. When RC oscillator operating mode is used, the external resistor R
DD
and the external capacitor C
OSC
OSC
must be connected between the OSC pin and GND, and when external clock operating mode is selected the
current protection resistor Rg (4.7 to 47kΩ) must be connected between the OSC pin and the external clock
output pin (external oscillator). (See the section on the OSC pin peripheral circuit.)
*14. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10kΩ)
appropriate for the capacitance of the external wiring so that signal waveforms are not degraded.
*15. The pins to be connected to the controller (CE, CL, DI, DO,
) can handle 3.3V or 5V.
RES
No.A1391-26/36
LC75886PW
Sample Application Circuit 2
1/4 duty, 1/3bias (for use with large panels)
(P1)
(P2)
(P3)
(P4)
P5
(Genenal-purpose
output port)
Used with the
backlight controller
or other circuit.
10kΩ≥R≥1kΩ
C≥0.047μF
OSC
*13
COM1
COM2
+5V
V
DD
DD
DD
R
R
R
COM3
V
V
1
2
S54/COM4
*11
P1/S1
P2/S2
P3/S3
P4/S4
S5
C
C
V
SS
TEST
S53
(S55)
(S56)
(S57)
S S
5 5
6 5
RES
*12
P5/S57
*15
CE
CL
DI
From the
controller
/
/
K K
S S
2 1
K K K K K K K K K
S S S S
5 4 3 2 1 6 5 4 3
*15
I
I I I I
To the controller
DO
To the controller
power supply
*14
Key matrix
(up to 30 keys)
Note: *11. Add a capacitor to the power supply line so that the power supply voltage V
rise time when power is
fall time when power drops are both at least 1ms, as the
DD
applied and the power supply voltage V
DD
LC75886PW is reset by the V
.
DET
pin is not used for system reset, it must be connected to the power supply V
*12. If the
.
RES
*13. When RC oscillator operating mode is used, the external resistor R
DD
and the external capacitor C
OSC
OSC
must be connected between the OSC pin and GND, and when external clock operating mode is selected the
current protection resistor Rg (4.7 to 47kΩ) must be connected between the OSC pin and the external clock
output pin (external oscillator). (See the section on the OSC pin peripheral circuit.)
*14. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10kΩ)
appropriate for the capacitance of the external wiring so that signal waveforms are not degraded.
*15. The pins to be connected to the controller (CE, CL, DI, DO,
) can handle 3.3V or 5V.
RES
No.A1391-27/36
LC75886PW
Sample Application Circuit 3
1/3 duty, 1/3 bias (for use with normal panels)
(P1) (Genenal-purpose
output port)
(P2)
Used with the
backlight controller
or other circuit.
(P3)
(P4)
P5
OSC
*13
COM1
COM2
COM3
+5V
V
V
DD
SS
*11
TEST
P1/S1
P2/S2
P3/S3
P4/S4
S5
V
V
1
2
DD
S53
DD
(S54)
(S55)
(S56)
(S57)
COM4/S54
C≥0.047μF
C
C
S S
5 5
6 5
RES
*12
P5/S57
*15
CE
CL
DI
From the
controller
/
/
K K
S S
2 1
K K K K K K K K K
I
5 4 3 2 1 6 5 4 3
*15
I
I
I
I
S S S S
To the controller
DO
To the controller
power supply
*14
Key matrix
(up to 30 keys)
Note: *11. Add a capacitor to the power supply line so that the power supply voltage V
rise time when power is
fall time when power drops are both at least 1ms, as the
DD
applied and the power supply voltage V
DD
LC75886PW is reset by the V
.
DET
pin is not used for system reset, it must be connected to the power supply V
*12. If the
.
RES
*13. When RC oscillator operating mode is used, the external resistor R
DD
and the external capacitor C
OSC
OSC
must be connected between the OSC pin and GND, and when external clock operating mode is selected the
current protection resistor Rg (4.7 to 47kΩ) must be connected between the OSC pin and the external clock
output pin (external oscillator). (See the section on the OSC pin peripheral circuit.)
*14. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10kΩ)
appropriate for the capacitance of the external wiring so that signal waveforms are not degraded.
*15. The pins to be connected to the controller (CE, CL, DI, DO,
) can handle 3.3V or 5V.
RES
No.A1391-28/36
LC75886PW
Sample Application Circuit 4
1/3 duty, 1/3bias (for use with large panels)
(P1) (Genenal-purpose
output port)
(P2)
Used with the
backlight controller
or other circuit.
(P3)
(P4)
P5
10kΩ≥R≥1kΩ
C≥0.047μF
OSC
*13
COM1
COM2
COM3
+5V
V
V
V
DD
DD
DD
R
R
R
1
2
*11
P1/S1
P2/S2
P3/S3
P4/S4
S5
C
C
V
SS
TEST
S53
(S54)
(S55)
(S56)
(S57)
COM4/S54
S S
5 5
6 5
RES
*12
P5/S57
*15
CE
CL
DI
From the
controller
/
/
K K
S S
2 1
K K K K K K K K K
S S S S
5 4 3 2 1 6 5 4 3
*15
I
I I I I
To the controller
DO
To the controller
power supply
*14
Key matrix
(up to 30 keys)
Note: *11. Add a capacitor to the power supply line so that the power supply voltage V
rise time when power is
fall time when power drops are both at least 1ms, as the
DD
applied and the power supply voltage V
DD
LC75886PW is reset by the V
.
DET
pin is not used for system reset, it must be connected to the power supply V
*12. If the
.
RES
*13. When RC oscillator operating mode is used, the external resistor R
DD
and the external capacitor C
OSC
OSC
must be connected between the OSC pin and GND, and when external clock operating mode is selected the
current protection resistor Rg (4.7 to 47kΩ) must be connected between the OSC pin and the external clock
output pin (external oscillator). (See the section on the OSC pin peripheral circuit.)
*14. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10kΩ)
appropriate for the capacitance of the external wiring so that signal waveforms are not degraded.
*15. The pins to be connected to the controller (CE, CL, DI, DO,
) can handle 3.3V or 5V.
RES
Notes on Transferring Display Data from The Controller
When using the LC75886PW in 1/4 duty, applications transfer the display data (D1 to D224) in four operations, and in
1/3 duty, they transfer the display data (D1 to D171) in three operations. In either case, applications should transfer all
of the display data within 30ms to maintain the quality of displayed image.
No.A1391-29/36
LC75886PW
Notes on the Controller Key Data Read Techniques
1. Timer based key data acquisition
(1) Flowchart
CE=”L”
NO
DO=”L”
YES
Key data read
processing
(2) Timing chart
Key on
Key on
Key input
Key scan
t3
t4
t3
t3
CE
DI
t6
Key
address
t6
t6
t5
t5
t5
Key data read
DO
Key data read request
t7
t7
t7
t7
Controller
determination
(Key on)
Controller
determination
(Key on)
Controller
determination
(Key off)
Controller
determination
(Key on)
Controller
determination
(Key off)
t3 ······· Key scan execution time when the key data agreed for two key scans. (615T[s])
t4 ······· Key scan execution time when the key data did not agree for two key scans and the key scan was executed
again. (1230T[s])
t5 ······· Key address (43H) transfer time
t6 ······· Key data read time
1
1
T=
=
f
f
OSC
CK
(3) Explanation
In this technique, the controller uses a timer to determine key on/off states and read the key data. The controller
must check the DO state when CE is low every t7 period without fail. If DO is low, the controller recognizes that a
key has been pressed and executes the key data read operation.
The period t7 in this technique must satisfy the following condition.
t7>t4+t5+t6
If a key data read operation is executed when DO is high (DO does not generate a key data read request output), the
read key data (KD1 to KD30) and sleep acknowledge data (SA) will be invalid.
No.A1391-30/36
LC75886PW
2. Interrupt based key data acquistion
(1) Flowchart
CE=”L”
NO
DO=”L”
YES
Key data read
processing
Wait for
at least t8
CE=”L”
NO
DO=”H”
YES
Key OFF
(2) Timing chart
Key on
Key on
Key input
Key scan
t4
t3
t3
t6
t5
t3
CE
t6
t6
t6
Key
DI
address
t5
t5
t5
Key data read
DO
Key data read request
t8
t8
t8
t8
Controller
determination
(Key on)
Controller
determination
(Key off)
Controller
determination
(Key on)
Controller
determination
(Key on)
Controller
determination
(Key on)
Controller
determination
(Key off)
t3 ······· Key scan execution time when the key data agreed for two key scans. (615T[s])
t4 ······· Key scan execution time when the key data did not agree for two key scans and the key scan was executed
again. (1230T[s])
t5 ······· Key address (43H) transfer time
t6 ········ Key data read time
1
1
T=
=
f
f
OSC
CK
(3) Explanation
In this technique, the controller uses interrupts to determine key on/off states and read the key data.
The controller must check the DO state when CE is low. If DO is low, the controller recognizes that a key has been
pressed and executes the key data read operation. After that the next key on/off determination is performed after the
time t8 has elapsed by checking the DO state when CE is low and reading the key data. The period t8 in this
technique must satisfy the following condition.
t8>t4
If a key data read operation is executed when DO is high (DO does not generate a key data read request output), the
read key data (KD1 to KD30) and sleep acknowledge data (SA) will be invalid.
No.A1391-31/36
LC75886PW
About Data Communication Method with The Controller
1. About data communication method of 4 line type CCB format
The 4 line type CCB format is the data communication method of before. The LC75886PW must connect to the
controller as followings.
*16
*17
(INT)
DI
Rup
Note: *16. Connect the pull-up resistor Rup. Select a resistance
(between 1 to 10kΩ) appropriate for the capacitance of the
external wiring so that signal waveforms are not degraded.
*17. The (INT) pin is an input port for the key data read request
signal (a low level on DO) detection.
DO
DI
Controller
DO
CL
LC75886PW
CL
CE
CE
2. About data communication method of 3 line type CCB format
The 3 line type CCB format is the data communication method that made a common use of the data input DI in the
data output DO. The LC75886PW must connect to the controller as followings.
*16
*17
(INT)
DIO
Rup
Note: *16. Connect the pull-up resistor Rup. Select a resistance
(between 1 to 10kΩ) appropriate for the capacitance of the
external wiring so that signal waveforms are not degraded.
*17. The (INT) pin is an input port for the key data read request
signal (a low level on DO) detection.
DO
DI
Controller
LC75886PW
CL
CE
CL
CE
In this case, Applications must transfer the data communication start command before the serial data input (CCB
address “42H”, display data and control data transfer) or serial data output (CCB address “43H” transfer, key data read)
to avoid the collision of the data input signal DI and the data output signal DO.
Then applications must transfer the data communication stop command when the controller wants to detect the key data
read request signal (a low level on DO) during a movement stop of the serial data input and the serial data output.
<1> Data communication start command
(1) When CL is stopped at the low level
(2) When CL is stopped at the high level
CE
CL
CE
CL
DI/DO
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
1
DI/DO
0
0
0
0
0
0
0
0
0 0 1 1 0 1 1 1
CCB address “00H”
Command data
CCB address “00H”
Command data
<2> Data communication stop command
(1) When CL is stopped at the low level
(2) When CL is stopped at the high level
CE
CL
CE
CL
DI/DO
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
1
DI/DO
0
0
0
0
0
0
0
0
1 1 0 0 0 1 1 1
CCB address “00H”
Command data
CCB address “00H”
Command data
No.A1391-32/36
LC75886PW
Data Communication Flowchart of 4 Line Type or 3 Line Type CCB Format
1. Flowchart of the initial setting when power is turned on.
Power on
(Applications must observe that the power
supply V
rise time is at least 1ms.)
DD
Power supply stability
(Applications must wait till the level of
the power supply is stable)
Serial data input
Note: The flowchart of initial setting when power is
turned on is same regardless of the 4 line type
or 3 line type CCB format.
(Display and control data transfer)
System reset clear
(Display on, Key scanning is enabled,
General-purpose output port state
setting are enabled)
Take explanation about "system reset" into account.
2. Flowchart of the serial data input
Data communication start
command transfer
*18
Serial data input
(Display and control data transfer)
The controller
NO
wants to detect the key
data read request signal
(a low level on DO).
Note: *18. In the case of the 4 line type CCB format,
the transfers of data communication start
command and data communication stop
command are unnecessary, and, in the case
of the 3 line type CCB format, these transfers
are necessary.
YES
Data communication stop
command transfer
*18
3. Flowchart of the serial data output
The controller
NO
acknowledges the key data read
request (When the CE is low,
the DO is low)
Note: *19. In the case of the 4 line type CCB format,
the transfer of data communication start
command is unnecessary, and, in the case
of the 3 line type CCB format, the transfer
is necessary.
YES
Data communication start
command transfer
*19
*20
*20. Because the serial data output has the role
of the data communication stop command,
it is not necessary to transfer the data
communication stop command some other
time.
Serial data output
(Key data and sleep
acknowledge data read)
No.A1391-33/36
LC75886PW
Timing Chart of 4 Line Type and 3 Line Type CCB Format
1. Timing chart of 4 line type CCB format
<Example 1>
Key on
Key off
Key input
Key scan
CE
Key scan execution
*21
Key scan execution
*21
CCB address
(42H)
CCB address CCB address
(42H) (42H)
CCB address
(43H)
DI
DO
Serial data input
(Display and control data transfer)
Serial data output
(Key data read)
Key data read
request
Key data read
request
<Example 2>
Key off
Key off
Key input
Key on
Key on
Key scan
CE
Key scan execution
Key scan execution *21
*21
CCB address
(42H)
CCB address CCB address
(42H) (42H)
CCB address
(43H)
CCB address
(43H)
DI
DO
Serial data input
(Display and control
data tranfer)
Serial data output
(Key data read)
Serial data output
(Key data read)
Key data read
request
Key data read
request
<Example 3>
Key on
Key off
Key off
Key input
Key scan
CE
Key scan execution
*21
Key scan execution
*21
CCB address
(42H)
CCB address CCB address
CCB address
(43H)
CCB address
(42H)
(42H)
(43H)
DI
DO
Serial data output
(Key data read)
Serial data output
(Key data read)
Serial data input
(Display and control
data transfer)
Key data read
request
Key data read
request
Note: *21. When the key data agrees for two key scans, the key scan execution time is 615T[s].
And, when the key data does not agree for two key scans and the key scan is executed
again, the key scan execution time is 1230T[s].
1
1
T=
=
f
f
OSC
CK
No.A1391-34/36
LC75886PW
2. Timing chart of 3 line type CCB format
<Example 1>
Key on
Key off
Key input
Key scan
CE
Key scan execution
*21
Key scan execution
*21
CCB address
(42H)
CCB address CCB address
(42H) (42H)
CCB address
(43H)
DI/DO
Data
communication
start command
Serial data
output
(Key data
read)
Data communication
start command
Data communication
stop command
Serial data input
(Display and control
data transfer)
Key data read
request
Key data read
request
<Example 2>
Key on
Key on
Key off
Key off
Key input
Key scan
CE
Key scan execution *21
Key scan execution
*21
CCB address
(42H)
CCB address CCB address
CCB address
(43H)
CCB address
(43H)
(42H)
(42H)
DI/DO
Data
communication
start command
Data communication
start command
Data
communication
stop command
Serial data
output
Data
Serial data
Serial data input
(Display and control
data transfer)
communication output
start command (Key data
read)
(Key data
read)
Key data read
request
Key data read
request
<Example 3>
Key on
Key off
Key off
Key input
Key scan
CE
Key scan execution
Key scan execution
*21
*21
CCB address
(42H)
CCB address CCB address CCB address
CCB address
(43H)
(42H)
(42H)
(43H)
DI/DO
Data
communication
start command
Serial data
output
(Key data
read)
Data
communication
start command
Serial data input
(Display and control
data transfer)
Serial data
output
(Key data
read)
Key data read
request
Key data read
request
Note: *21. When the key data agrees for two key scans, the key scan execution time is 615T[s].
And, when the key data does not agree for two key scans and the key scan is executed
again, the key scan execution time is 1230T[s].
1
1
=
T=
f
f
OSC
CK
No.A1391-35/36
LC75886PW
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PS No.A1391-36/36
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