LC823425 [ONSEMI]
Low Power Consumption 1 chip Audio LSI for Portable Sound Solution;
| 型号： | LC823425 |
| 厂家： | 
ONSEMI |
| 描述： | Low Power Consumption 1 chip Audio LSI for Portable Sound Solution |
| 文件： | 总29页 (文件大小：388K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : ENA2351
LC823425
CMOS LSI
Low Power Consumption
1 chip Audio LSI
http://onsemi.com
for Portable Sound Solution
Overview
LC823425 is an audio processing solution for portable devices such as IC recorders. This product features a built-in
hardwired MP3 encoder/decoder system, enabling the industry’s lowest power consumption of 5mW and supporting
advanced functionality via a built-in digital signal processor (DSP).
Function
ARM7TDMI-STM1, AMBA® (AHB/APB) system
Internal SRAM(512kbyte), Internal ROM(128kbyte).
Boot code and built-in standard function
MultiPort Memory Controller (one CS),
External Memory Controller (two CS)
DMA controller (2ch), Interrupt controller
(external 5ch + enhancing 16ch, and internal 31ch factor)
SIO(2ch), UART(2ch),
TQFP128 14x14 / TQFP128L
I2C (1ch Single Master and Full/Standard conforming)
General-purpose port (I/O 40ch+1ch (FBGA221J is selected)).
Plain timer (1ch) and multiple timer (2ch3), Watch dog timer (1ch)
10bit A/D converter (6ch)
SD card IF(2ch) (w/o CPRM), MemoryStick IF(1ch)
USB2.0(480Mbps/12Mbps) device IF. Built-in PHY
RTC (real time clock)
MP32 hard wired encoder/decoder
DSP system
WMA3 (Microsoft WMA Decoder Profile Level3 conforming)
AAC (MPEG4 LC-AAC)
Variable speed playback (0.5-2.0)
LFBGA211 11x11 / FBGA221J
Six band equalizer (EQ3), Highband replication circuit(YY filter), Surround (+EQ2) circuit
16/24bit PCM interface, Sampling rate converter, BEEP circuit, Digital mic interface
DA converter and 16bit audio D class amplifier (LC LPF necessity in the outside)
1 ARM7TDMI-STM is the trademark of ARM Limited
2 MPEG Layer-3 audio coding technology licensed from Fraunhofer IIS and Thomson.
Supply of this product does not convey license nor imply any right to distribute content created with this product in
revenue-generating broadcast systems (terrestrial, satellite, cable and/or other distribution channels), streaming applications
(via Internet, intranets and/or networks), other content distribution systems (pay-audio or audio-on-demand applications and the
like) or on physical media (compact discs, digital versatile discs, semiconductor chips, hard drives, memory cards and the like).
Supply of this product does not convey license under the relevant intellectual property of Thomson and/or Fraunhofer
Gesellschaft nor imply any right to use this product in any finished end user or ready-to-use final product. An independent
license for such use is required. For details, please visit http://mp3licensing.com/.
3 This product contain technology of Microsoft company ownership, and you cannot distribute or use without getting license from
Microsoft Licensing company.
* I2C Bus is a trademark of Philips Corporation.
ORDERING INFORMATION
See detailed ordering and shipping information on page 29 of this data sheet.
Semiconductor Components Industries, LLC, 2014
July, 2014
70914HK 20130617-S00001, 20130425-S00003 No.A2351-1/29
LC823425
Specifications
Absolute Maximum Ratings at V =0V
SS
Item
Symbol
Condition
Ratings
Unit
V
Maximum power
supply voltage
Vdd1
VddRTC
VddXT1
0.5 to 1.8
0.5 to 2.5
AVddUSBPHY1
AVddPLL1
AVddDAMPL
AVddDAMPR
Vdd2
V
VddSD0
VddSD1
V
0.5 to 4.6
AVddADC
AVddPLL2
AVddUSBPHY2
Input voltage
V
I
0.5 to V +0.5
V
V
DD
V
USBDDP, USBDDM terminal
0.5 to AVddUSBPHY2+0.5
20 to +75
IUSB
Operating ambient
temperature
Ambient temperature of
preservation
Topr
Tstg
C
C
55 to +125
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
Recommended Operating Conditions at Ta=20C to +75C
Low voltage operation
High voltage operation
Item
Symbol
Condition
Unit
Min
Typ
1.0
Max
Min
Typ
1.2
Max
Power-supply
voltage
V
V
Vdd1
0.93
1.1
1.1
1.3
VddXT1
0.93
0.93
2.7
1.0
1.0
3.3
1.1
1.1
3.6
1.1
1.1
2.7
1.2
1.2
3.3
1.3
1.3
3.6
V
V
AVddPLL1
AVddPLL2
V
VddRTC
0.9
2.7
1.0
3.3
1.8
3.3
1.8
3.3
1.8
3.3
1.0
3.3
1.2
1.2
1.3
3.6
0.9
2.7
1.0
3.3
1.8
3.3
1.8
3.3
1.8
3.3
1.2
3.3
1.2
1.2
1.3
3.6
V
V
V
V
V
V
V
V
V
V
V
V
Vdd2
1.7
1.95
3.6
1.7
1.95
3.6
2.7
2.7
VddSD0
VddSD1
1.7
1.95
3.6
1.7
1.95
3.6
2.7
2.7
1.7
1.95
3.6
1.7
1.95
3.6
AVddADC
2.7
2.7
AVddUSBPHY1
AVddUSBPHY2
AVddDAMPL
AVddDAMPR
0.93
2.7(*2)
0.93
0.93
0
1.1
1.1
1.3
3.6
2.7(*2)
0.93
0.93
0
3.6
1.65
1.65
1.65
1.65
Input voltage range
V
V
V
IN
DD
DD
(*1) Follow the operating frequency specifications because the operating frequency ranges are specified according to the operating
voltage ranges.
(*2) When USB is used (include USB suspend state), this should be 3.0V(MIN).
(*3) At any state
-Vdd1=AVddUSBPHY1=AVddPLL1=VddXT1
-Vdd2, VddSD0, VddSD1, AVddPLL2, AVddADC, AVddUSBPHY2, and AVddDAMPL=AVddDAMPR can be supplied with
different voltages.
However, whenever Vdd1=AVddUSBPHY1=AVddPLL1=VddXT1Vdd2 is supplied, Vdd2, VddSD0, VddSD1,AVddPLL2,
AVddADC, AVddUSBPHY2, and AVddDAMPL=AVddDAMPR must be supplied.
-When only RTC operates, VddRTC can be supplied while *Vdd*=0V(exclude VddRTC) and the BACKUPB=Low input.
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
No.A2351-2/29
LC823425
Low voltage operation
High voltage operation
Item
Symbol
Fxin1
Condition
Unit
Min
0.4
Typ
Max
Min
Typ
Max
Oscillation input
frequency
ARM7TDMI-S
Surrounding of
ARM
RTC
RC
48MHz±200ppm
The same left
MHz
FxinRTC
Frc
32.768
1
The same left
The same left
kHz
MHz
2
Time to
stabilize of
oscillation
Txin1
TxinRTC
Farm
204
205
The same left
The same left
ms
ms
Internal operation
frequency
ARM7TDMI-S
ARM AHB
0
0
0
0
0
0
0
55
0
0
0
0
80
80
80
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Fahb
55
Fapb
ARM APB
55
Fdsp
DSP
110.592
73.728
36.864
18.432
110.592
The same left
Faud(*1)
Fdec
AUDIO(768fs)
MP3 Decoder
MP3 Encoder
33.8688
16.9344
16.9344
The same left
The same left
Fenc
(*1) Almost all of audio functions operate on 256*Fs (sampling frequency) clock,
while SRC(sampling rate converter) and D class amplifier operate on 384*Fs clock.
256*Fs and 384*Fs clocks are generated from 768*Fs base clock.
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
4 Reference value @Ta=25 celsius degree and Vdd1=1.0V, and depends on circumstances.
5 Reference value @Ta=25 celsius degree and VddRTC =1.0V, and depends on circumstances.
No.A2351-3/29
LC823425
Electrical Characteristics
at Vdd2=2.7V to 3.6V, VddRTC=0.9V to 1.3V, VddSD0=2.7V to 3.6V, VddSD1=2.7V to 3.6V,
Ta=20C to +75C
Item
Symbol
IH
Pin
Condition
Min
0.7Vdd2
Typ
Max
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
(1)
(2)
(3)
(4)
(5)
(6)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
0.7VddSD0
0.7VddSD1
0.75Vdd2
0.7VddRTC
0.7VddRTC
Input H level
voltage
V
V
Schmidt
Schmidt
0.3Vdd2
0.3VddSD0
0.3VddSD1
0.25Vdd2
0.2VddRTC
0.2VddRTC
Input L level
voltage
IL
Schmidt
Schmidt
Vdd20.4
VddSD00.4
VddSD10.4
I
=2mA
OH
(10)
(12)
(13)
(11)
V
V
V
V
Vdd20.4
Output H level
voltage
I
=4mA
VddSD00.4
VddSD10.4
Vdd20.4
V
OH
OH
I
I
=8mA
OH
(12)
(13)
(7)
V
V
V
V
VddSD00.4
VddSD10.4
=12mA
OH
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.3
170
170
75
I
I
=2mA
=4mA
(8)
OL
OL
(9)
V
V
(10)
(12)
(13)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(16)
(17)
(18)
V
Output L level
voltage
V
OL
V
I
I
I
=8mA
V
OL
OL
OL
V
=12mA
=0.3mA
V
V
50
50
25
10
10
10
80
80
50
17
17
17
kΩ
kΩ
kΩ
kΩ
kΩ
KΩ
Rup
Rdn
Pull-up resistor
40
Pull-down resistor
Input Leake current
40
40
(1)(2)
(3)(4)
(5)(6)
(7)(8)
(9)(10)
(11)(12)
(13)(14)
I
V =V *=V
DD SS
10
μA
10
10
IL
I
Output leakage
current
I
When Hi-Z is output
10
μA
OZ
No.A2351-4/29
LC823425
at Vdd2=1.7V to 1.95V, VddSD0=1.7V to 1.95V, VddSD1=1.7V to 1.95V,
Ta=20C to +75C
Item
Symbol
IH
Pin
Condition
Min
0.7×Vdd2
0.7×VddSD0
0.7×VddSD1
0.75×Vdd2
Typ
Max
Unit
V
V
V
V
V
V
V
V
(1)
(2)
(3)
(4)
(1)
(2)
(3)
(4)
(7)
(8)
(9)
(10)
Input H level
voltage
V
V
Schmidt
0.3×Vdd2
0.3×VddSD0
0.3×VddSD1
0.25×Vdd2
Input L level
voltage
IL
Schmidt
V
V
V
Vdd20.4
VddSD00.4
VddSD10.4
I
=1mA
OH
V
V
V
V
Vdd20.4
Output H level
voltage
(12)
(13)
(11)
I
=2mA
VddSD00.4
VddSD10.4
Vdd20.4
V
OH
OH
I
I
=4mA
=6mA
OH
(12)
(13)
(7)
V
V
V
VddSD00.4
VddSD10.4
OH
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
350
350
100
100
100
100
(8)
I
I
=1mA
=2mA
V
V
OL
OL
(9)
(10)
(12)
(13)
(11)
(12)
(13)
(15)
(16)
(17)
(16)
(17)
(18)
V
Output L level
voltage
V
V
OL
V
I
I
=4mA
=6mA
V
OL
OL
V
V
90
90
10
20
20
20
175
175
50
kΩ
kΩ
kΩ
kΩ
kΩ
KΩ
Pull-up resistor
Rup
Rdn
40
Pull-down resistor
Input Leake current
40
40
(1)(2)
(3)(4)
(5)(6)
(7)(8)
(9)(10)
(11)(12)
(13)(14)
I
V =V *=V
DD SS
10
μA
10
10
IL
I
Output leakage
current
I
When Hi-Z is output
10
μA
OZ
No.A2351-5/29
LC823425
(1) TDI, TMS, TCK, PHI, SDI0, SDO0, DIN, DOUT, MPMCDATA[15:0], MPMCADDR14, EXD[15:0]
(2) SDCMD0, SDAT00, SDAT01, SDAT02, SDAT03, SDWP0, SDCD0
(3) SDCLK1, SDCMD1, SDAT10, SDAT11, SDAT12, SDAT13, SDWP1, SDCD1
(4) TEST, BMODE[2:0], NRES, NTRST, MCLK, BCK, LRCK, EXTFIQ, EXTINT00, EXTINT01, EXTINT02, EXTINT03,
EXTINT04, SCK0, SCK1, SDI1, SDO1, TXD1, RXD1, TXD2, RXD2, SCL, SDA, TIOCA0, TIOCA1, TIOCB0, TIOCB1,
TCLKA, TCLKB
(5) VDET
(6) BACKUPB
(7) RTCK, TDO, EXTFIQ, EXTINT00, EXTINT01, EXTINT02, EXTINT03, EXTINT04, SCK0, SDI0, SDO0, SCK1, SDI1,
SDO1, SCL, SDA, TXD1, RXD1, TXD2, RXD2, TIOCA0, TIOCA1, TIOCB0, TIOCB1, BCK, LRCK, DIN, DOUT, NCS0,
NCS1, NRD, NWRENWRL, NHBNWRH, NLBEXA0, EXA[20:1], EXD[15:0]
(8) SDWP0, SDCD0
(9) SDWP1, SDCD1
(10) MCLK, MPMCCKE, MPMCCS, MPMCWE, MPMCCAS, MCMCRAS, MPMCDQM[1:0], MPMCADDR14,
MPMCADDR13, MPMCADDR[10:0], MPMCDATA[15:0], TCLKA, TCLKB
(11) MPMCCLK, PHI
(12) SDCLK0, SDCMD0, SDAT00, SDAT01, SDAT02, SDAT03
(13) SDCLK1, SDCMD1, SDAT10, SDAT11, SDAT12, SDAT13
(14) RTCINT
(15) NTRST, TDI, TMS, TCK
(16) EXTFIQ, EXTINT00, EXTINT01, EXTINT02, EXTINT03, EXTINT04, SCK0, SDI0, SDO0, SCK1, SDI1, SDO1, SCL,
SDA, TXD1, RXD1, TXD2, RXD2, TIOCA0, TIOCA1, TIOCB0, TIOCB1, TCLKA, TCLKB, MCLK, BCK, LRCK, DIN,
DOUT, MPMCADDR14, SDWP0, SDCD0, SDWP1, SDCD1, PHI
(17) SDCMD0, SDAT00, SDAT01, SDAT02, SDAT03, SDCLK1, SDCMD1, SDAT10, SDAT11, SDAT12, SDAT13
(18) EXD[15:0], MPMCDATA[15:0]
(note 1)
Because the following pins can switch the drive ability when it outputs it by the register setting
VOH and two kinds of VOL are provided for. SDCMD0, SDAT00, SDAT01, SDAT02, SDAT03, SDCLK0, SDCMD1,
SDAT10, SDAT1, SDAT12, SDAT13, SDCLK1
(note 2)
It is not included in the DC characteristic about the following pins.
VR, VRH, VRL, USBDDM, USBDDP, USBDEXT12, VCNT1, VCNT2, AN0, AN1, AN2, AN3, AN4, AN5, XIN1, XIN32K,
XOUT1, XOUT32K, LOUT, ROUT
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
No.A2351-6/29
LC823425
Package Dimensions
unit : mm
LC823425-12G1-H : TQFP128L
TQFP128 14x14 / TQFP128L
CASE 932BA
ISSUE O
No.A2351-7/29
LC823425
LC823425-13W1-E : FBGA221J
LFBGA221 11x11 / FBGA221J
CASE 566DJ
ISSUE O
No.A2351-8/29
LC823425
Pin Assignment
I/O
Terminal characteristic
3.3 V CMOS input
I
Input pin
3IC
3IS
1IC
1IS
1.0 V CMOS input
O
B
P
Output pin
Interactive pin
3.3V Schmidt input
1.0V Schmidt input
0.3mA open drain output
3ICU
3ISU
3.3 V CMOS input pull-up
3.3V Schmidt input pull-up
OD3
Power supply
pin
NC
Non Connect
3ICUD
3ISUD
3.3 V CMOS input pull-down
Pull-up both correspondences
3.3V Schmidt input pull-down
Pull-up both correspondences
3.3 V 4mA output
X
Oscillation amplifier
3.3V analogue
1.0V analogue
3.6V tolerant
3A
1A
3R
3O4
3O8
3.3 V 8mA output
3T2
3.3 V 2mA tristate output
3.3 V 4mA tristate output
3.3 V 4mA/12mA switch tristate output
3T4
3T4(12)
FBGA221J
IO
Power
supply
TQFP128L
Pin Name
I/O
Characteristic
Tolerant
Function
No.
No.
Ball
1
2
3
4
5
6
7
8
C3
A1
D3
E4
B2
E3
B1
C1
-
1
-
MPMCDATA0
BMODE0
B
I
3ICD/3T4
3IS
3R
3R
3R
3R
3R
b
b
b
b
b
SDRAM data bus bit0
Boot mode selector bit0
SDRAM data bus bit1
SDRAM data bus bit2
Boot mode selector bi1
Digital ground
MPMCDATA1
MPMCDATA2
BMODE1
B
B
I
3ICD/3T4
3ICD/3T4
3IS
-
2
-
V
P
B
B
SS
-
MPMCDATA3
MPMCDATA4
3ICD/3T4
3ICD/3T4
3R
3R
b
b
SDRAM data bus bit3
SDRAM data bus bit4
-
External FIQ
interrupt/general-purpose port
9
C2
3
EXTFIQ/GPIO2A
MPMCADDR0
I/B
3ISUD/3T2
3O4
3R
b
b
10
11
12
D2
F4
F5
-
4
-
O
P
P
SDRAM address bit0 output
Digital ground
V
SS
Vdd2
b
b
b
b
Digital IO power supply
13
14
15
E2
D1
F3
-
-
MPMCADDR1
MPMCADDR2
EXTINT00/GPIO2B
O
O
3O4
3O4
SDRAM address bit1 output
SDRAM address bit2 output
External interrupt 0-
bit0/general-purpose port
External interrupt 0-
bit1/general-purpose port
5
I/B
3ISUD/3T2
3R
3R
EXTINT01/GPIO2
C
16
17
18
G4
E1
F2
6
-
I/B
O
3ISUD/3T2
3O4
b
b
b
b
MPMCADDR3
SDRAM address bit3 output
EXTINT02/GPIO2
D
External interrupt 0-
bit2/general-purpose port
7
I/B
3ISUD/3T2
3O4
3R
19
20
21
F1
G5
G3
-
-
-
MPMCADDR4
O
P
SDRAM address bit4 output
Digital ground
V
SS
MPMCADDR5
O
3O4
b
b
SDRAM address bit5 output
External interrupt 0-
bit3/general-purpose port
22
H4
8
EXTINT03/GPIO2E
I/B
3ISUD/3T2
3R
3R
23
24
G2
G1
-
-
MPMCADDR6
MPMCADDR7
O
O
3O4
3O4
b
b
SDRAM address bit6 output
SDRAM address bit7 output
External interrupt 0-
bit4/general-purpose port
25
H3
9
EXTINT04/GPIO2F
I/B
3ISUD/3T2
b
26
27
28
29
30
31
H1
H2
H5
J5
-
-
MPMCADDR8
MPMCADDR9
Vdd2
O
O
P
3O4
3O4
b
b
b
SDRAM address bit8 output
SDRAM address bit9 output
Digital IO power supply
Digital ground
10
11
-
V
P
SS
J1
MPMCADDR10
MPMCADDR13
O
O
3O4
3O4
b
b
SDRAM address bit10 output
SDRAM address bit13 output
J4
-
No.A2351-9/29
LC823425
SD card Ch1 detecting
/general-purpose port
SD card Ch1 write-protection
/Memory Stick
INS/general-purpose port
SD card Ch1 command line
/Memory Stick
BS/general-purpose port
SD card Ch1 data bit0
/Memory Stick data
bit0/general-purpose port
SD card Ch1 data bit1
/Memory Stick data
bit1/general-purpose port
Digital IO power supply (SDI/F Ch1
exclusive use)
SD card Ch1 data bit2
/Memory Stick data
bit2/general-purpose port
SD card Ch1 data bit3
/Memory Stick data
bit3/general-purpose port
SD card Ch1 clock output
/Memory Stick clock
32
33
J2
J3
12
13
SDCD1/GPIO20
I/B
3ICUD/3T2
3R
3R
s1
s1
SDWP1/INS
/GPIO21
I/I/B
3ICUD/3T2
SDCMD1/BS
/GPIO23
B/I
/B
3ICUD
/3T4(12)
34
35
K1
K2
14
15
3R
3R
3R
s1
s1
SDAT10/DATA0
/GPIO24
B/B
/B
3ICUD
/3T4(12)
SDAT11/DATA1
/GPIO25
B/B
/B
3ICUD
/3T4(12)
36
37
38
K3
K4
L1
16
17
18
s1
s1
s1
VddSD1
P
SDAT12/DATA2
/GPIO26
B/B
/B
3ICUD
/3T4(12)
3R
3R
3R
SDAT13/DATA3
/GPIO27
B/B
/B
3ICUD
/3T4(12)
39
40
L2
L3
19
20
s1
s1
SDCLK1/SCLK
/GPIO22
O/O
/B
3ICUD
/3T4(12)
/general-purpose port
V
41
42
43
K5
L4
21
22
23
P
P
O
Digital ground
SS
Vdd1
Digital internal power supply
SD card I/FCh0 clock output
M1
SDCLK0
3T4(12)
s0
s0
3ICUD
/3T4(12)
3ICUD
/3T4(12)
3ICUD
44
45
46
47
48
49
50
51
M2
M3
N1
M4
N2
N3
P1
P2
24
25
26
27
28
29
30
31
SDCMD0
B
B
3R
3R
3R
SD card I/FCh0 command line
SD card I/FCh0 data bit0
SD card I/FCh0 data bit1
SDAT00
s0
s0
s0
s0
s0
s0
s0
SDAT01
B
/3T4(12)
Digital IO power supply (SDI/F Ch0
exclusive use)
VddSD0
P
3ICUD
/3T4(12)
3ICUD
SDAT02
B
3R
3R
3R
3R
SD card I/FCh0 data bit2
SD card I/FCh0 data bit3
SDAT03
B
/3T4(12)
SD card I/FCh0 detecting
/general-purpose port
SD card I/FCh0 write-protection
/general-purpose port
SDCD0/GPIO29
SDWP0/GPIO28
I/B
I/B
3ICUD/3T2
3ICUD/3T2
V
52
53
54
55
56
57
58
59
60
61
62
63
64
R1
T1
R3
P4
T2
T3
R4
T4
R5
T5
P3
N4
R2
32
33
34
35
36
37
38
39
40
41
42
43
44
P
P
P
P
B
B
P
P
P
O
P
P
P
Digital ground
SS
AVddUSBPHY1
AVssUSBPHY
AVssUSBPHY
USBDDM
u1
1.0V power supply for USB-PHY
Ground for USB-PHY
Ground for USB-PHY
USB D-
3A
3A
u2
u2
u2
USBDDP
USB D+
AVddUSBPHY2
AVssUSBPHY
AVssUSBPHY
USBDEXT12
AVddUSBPHY2
AVddUSBPHY1
AVssUSBPHY
3.3V power supply for USB-PHY
Ground for USB-PHY
Ground for USB-PHY
USB-PHY reference resistance
3.3V power supply for USB-PHY
1.0V power supply for USB-PHY
Ground for USB-PHY
3A
u2
u2
u1
Power supply for oscillation
amplifier
48MHz oscillation amplifier output
for system
65
P5
45
VddXT1
P
x1
x1
66
67
68
M5
N5
L5
46
47
48
XOUT1
VssXT1
XIN1
O
P
I
X
Ground for oscillation amplifier
48MHz oscillation amplifier input
for system
X
x1
69
70
71
72
73
T6
P6
R6
M6
M7
49
50
51
52
-
AVddPLL1
VCNT1
P
O
P
P
B
p1
p1
Analog power supply for PLL1
VCO control for PLL1
1A
AVssPLL1
Vdd2
Analog ground for PLL1
Digital IO power supply
SDRAM data bus bit5
b
b
MPMCDATA5
3ICD/3T4
3R
3R
MTM external clock
TCLKA/GPIO00
/MPMCADDR11
/EXTINT10
I/B
/O
/I
A/general-purpose port
/SDRAM address bit11
/external interrupt 1- bit0
74
N8
53
3ISUD/3T4
b
No.A2351-10/29
LC823425
75
76
P7
R7
-
MPMCDATA6
B
3ICD/3T4
3R
3R
b
b
SDRAM data bus bit6
MTM external clock
TCLKB/GPIO01
/MPMCADDR12
/EXTINT11
I/B
/O
/I
B/general-purpose port
/SDRAM address bit12
/external interrupt 1- bit1
54
3ISUD/3T4
77
78
T7
N7
-
-
MPMCDATA7
MPMCDATA8
B
B
3ICD/3T4
3ICD/3T4
3R
3R
b
b
SDRAM data bus bit7
SDRAM data bus bit8
System clock
output/general-purpose port
/external interrupt 1- bit6
PHI/GPIO06
/EXTINT16
O/B
/I
79
T8
55
3ICUD/3T8
3R
b
V
80
81
82
83
84
85
86
87
88
89
90
91
92
N6
P8
-
56
-
P
O
B
B
O
O
O
P
O
I
Digital ground
SS
RTCK
3O2
3ICD/3T4
3ICD/3T4
3O2
b
b
b
b
b
b
JTAG test returned clock
SDRAM data bus bit9
SDRAM data bus bit10
JTAG test data output
SDRAMCAS output
N9
MPMCDATA9
MPMCDATA10
TDO
3R
3R
R8
-
M8
T9
57
-
MPMCCAS
MPMCRAS
3O4
R9
-
3O4
SDRAMRAS output
V
M9
P9
58
-
Digital ground
SS
MPMCWE
NTRST
Vdd2
3O4
b
b
b
SDRAM write enable output
JTAG test reset input
Digital IO power supply
Digital internal power supply
SDRAM clock enable output
T10
N10
M10
R10
59
-
3ISU
3R
P
P
O
60
-
Vdd1
MPMCCKE
3O4
3O4
3IS
b
b
b
b
SDRAM data mask byte lane
selector bit0
93
94
95
P10
M11
T11
-
61
-
MPMCDQM0
NRES
O
I
3R
External reset input
SDRAM data mask byte lane
selector bit1
MPMCDQM1
O
3O4
96
97
R11
T12
N11
P11
T13
R12
M12
N12
P12
R14
-
-
MPMCCS
O
O
P
B
I
3O4
3O8
b
b
SDRAM chip selection output
SDRAM clock output
Digital ground
MPMCCLK
V
98
-
SS
99
-
MPMCDATA11
TDI
3ICD/3T4
3ICU
3R
3R
3R
3R
3R
3R
3R
b
b
b
b
b
b
b
SDRAM data bus bit11
JTAG test data input
SDRAM data bus bit12
SDRAM data bus bit13
SDRAM data bus bit14
JTAG test mode selection
SDRAM data bus bit15
100
101
102
103
104
105
62
-
MPMCDATA12
MPMCDATA13
MPMCDATA14
TMS
B
B
B
I
3ICD/3T4
3ICD/3T4
3ICD/3T4
3ICU
-
-
63
-
MPMCDATA15
B
3ICD/3T4
MPMCADDR14
/GPIO17
O
/B
SDRAM address
106
R13
-
3ICUD/3T4
3R
b
bit14/general-purpose port
External memory high byte
selection/external memory write
107
108
109
110
111
112
113
114
115
P13
P14
P15
T15
R15
R16
T16
N13
T14
-
NHBNWRH
TCK
O
I
3T2
3ICU
3T2
3R
3R
b
b
b
64
-
JTAG test clock
External memory chip selection
bit1
NCS1
O
P
P
P
I
V
65
66
67
68
69
70
Digital ground
SS
Vdd2
b
r
Digital IO power supply
Power supply for RTC
VddRTC
XIN32K
VssRTC
XOUT32K
32.768KHz oscillation amplifier
input for RTC
X
X
r
P
O
Ground for RTC
32.768KHz oscillation amplifier
output for RTC
r
RTC power supply down detect
input
116
117
118
119
120
121
M13
N14
P16
L12
N15
M14
71
72
73
74
-
VDET
I
1IC
OD3
1IS
r
r
r
RTCINT
BACKUPB
Vdd1
O
I
3R
RTC interrupt signal output
RTC operation mode (only RTC
operating or entire LSI operating)
P
O
P
Digital internal power supply
External memory chip selection
bit0
NCS0
3T2
b
V
75
Digital ground
SS
No.A2351-11/29
LC823425
122
123
K12
N16
76
-
Vdd2
NRD
P
b
b
Digital IO power supply
External memory lead
O
3T2
3IS
Test mode input (connect to digital
ground usually)
External memory low byte external
memory write/selection
124
125
L13
77
-
TEST
I
3R
3R
b
b
M15
NWRENWRL
O
3T2
126
127
128
L14
M16
K13
78
-
BMODE2
EXA1
I
3IS
3T2
3T2
b
b
b
Boot mode selector bit2
O
O
External memory address bit1
-
EXA2
External memory address bit2
I2C clock output/general-purpose
port
/external interrupt 1- bit7
SCL/GPIO07
/EXTINT17
O/B
/I
129
L15
79
3ISUD/3T2
3R
b
130
131
132
133
134
J14
L16
K14
K15
J12
-
-
EXA3
EXA4
O
O
P
3T2
3T2
b
b
External memory address bit3
External memory address bit4
Digital ground
V
80
-
SS
EXA5
EXA6
O
O
3T2
3T2
b
b
External memory address bit5
External memory address bit6
I2C data/general-purpose port
-
SDA/GPIO08
/EXTINT18
B/B
/I
135
136
137
K16
J16
J13
81
-
3ISUD/3T2
3T2
3R
3R
b
b
b
/external interrupt 1- bit8
EXA7
O
External memory address bit7
PCM master
clock/general-purpose port
82
MCLK/GPIO18
B/B
3ISUD/3T4
138
139
J15
-
-
EXA8
EXA9
O
O
3T2
3T2
b
b
External memory address bit8
External memory address bit9
H14
PCM bit clock/general-purpose
port
140
H12
83
BCK/GPIO19
EXA10
B/B
3ISUD/3T2
3T2
3R
b
b
141
142
143
144
H16
G15
H13
H15
-
O
P
P
O
External memory address bit10
Digital ground
V
84
85
-
SS
Vdd2
b
b
Digital IO power supply
External memory address bit11
EXA11
3T2
PCMLR clock/general-purpose
port
PCM data input/general-purpose
port
145
G16
86
87
LRCK/GPIO1A
B/B
3ISUD/3T2
3R
3R
b
146
147
148
G12
F16
G14
DIN/GPIO1B
EXA12
I/B
O
3ICUD/3T2
3T2
b
b
b
External memory address bit12
PCM data output/general-purpose
port
88
DOUT/GPIO1C
O/B
3ICUD/3T2
3R
V
149
150
G13
E16
-
-
P
Digital ground
SS
EXA13
O
3T2
b
b
b
b
External memory address bit13
MTMCh0A input capture and
output capture/general-purpose
port
TIOCA0/GPIO09
/EXTINT19
B/B
/I
151
152
153
D16
F12
F15
89
-
3ISUD/3T2
3T2
3R
3R
/external interrupt 1- bit9
EXA14
O
External memory address bit14
MTMCh1A input capture and
output capture/general-purpose
port
TIOCA1/GPIO0A
/EXTINT1A
B/B
/I
90
3ISUD/3T2
/external interrupt 1- bit10
154
155
156
157
158
E11
C16
F13
E15
F14
-
-
EXA15
EXA16
Vdd2
O
O
P
P
O
3T2
3T2
b
b
b
External memory address bit15
External memory address bit16
Digital IO power supply
91
92
-
V
Digital ground
SS
EXA17
3T2
b
b
External memory address bit17
UARTCh1 transmission
data/general-purpose port
/external interrupt 1- bit4
TXD1/GPIO04
/EXTINT14
O/B
/I
159
E12
93
3ISUD/3T2
3R
3R
160
161
B16
E13
-
-
EXA18
EXA19
O
O
3T2
3T2
b
b
External memory address bit18
External memory address bit19
UARTCh1 receive
data/general-purpose port
/external interrupt 1- bit5
RXD1/GPIO05
/EXTINT15
I/B
/I
162
A16
94
3ISUD/3T2
b
163
164
D15
E14
-
-
EXA20
O
O
3T2
3T2
b
b
External memory address bit20
External memory low byte
selection
NLBEXA0
3R
3R
165
166
C15
B15
95
-
Vdd1
P
B
Digital internal power supply
External memory data bus bit0
EXD0
3ICD/3T2
b
No.A2351-12/29
LC823425
V
167
168
D14
A15
-
P
Digital ground
SS
MTMCh0B input capture and
output capture/general-purpose
port
/digital mic clock output
/external interrupt 1- bit2
TIOCB0/GPIO02
/DMCKO
/EXTINT12
B/B
/O
/I
96
3ISUD/3T2
3R
b
169
170
C14
D13
-
-
EXD1
EXD2
B
B
3ICD/3T2
3ICD/3T2
3R
3R
b
b
External memory data bus bit1
External memory data bus bit2
MTMCh1B input capture and
output capture/general-purpose
port
/digital mic data input
/external interrupt 1- bit3
TIOCB1/GPIO03
/DMDIN/EXTINT13
B/B
/I/I
171
B14
97
3ISUD/3T2
3R
b
172
173
A14
C13
-
-
EXD3
EXD4
B
B
3ICD/3T2
3ICD/3T2
3R
3R
b
b
External memory data bus bit3
External memory data bus bit4
Cereal I/FCh0
clock/general-purpose port
174
175
176
B13
A13
C12
98
-
SCK0/GPIO1D
EXD5
B/B
B
3ISUD/3T2
3ICD/3T2
3R
3R
3R
b
b
b
External memory data bus bit5
Cereal I/FCh0 data
input/general-purpose port
99
SDI0/GPIO1E
I/B
3ICUD/3T2
177
178
179
180
D12
B12
D10
D8
-
EXD6
EXD7
B
B
P
P
3ICD/3T2
3ICD/3T2
3R
3R
b
b
External memory data bus bit6
External memory data bus bit7
Digital ground
-
100
-
V
SS
Vdd2
b
b
Digital IO power supply
Cereal I/FCh0 data
output/general-purpose port
181
C11
101
SDO0/GPIO1F
O/B
3ICUD/3T2
3R
182
183
D11
A12
-
-
EXD8
EXD9
B
B
3ICD/3T2
3ICD/3T2
3R
3R
b
b
External memory data bus bit8
External memory data bus bit9
Cereal I/FCh1
clock/general-purpose port
/external interrupt 1- bit13
SCK1/GPIO0D
/EXTINT1D
B/B
/I
184
185
186
187
188
B11
A11
C10
B10
A10
102
-
3ISUD/3T2
3ICD/3T2
3ISUD/3T2
3ICD/3T2
3ISUD/3T2
3R
3R
3R
3R
3R
b
b
b
b
b
EXD10
B
External memory data bus bit10
Cereal I/FCh1 data
input/general-purpose port
/external interrupt 1- bit14
SDI1/GPIO0E
/EXTINT1E
I/B
/I
103
-
EXD11
B
External memory data bus bit11
Cereal I/FCh1 data
output/general-purpose port
/external interrupt 1- bit15
SDO1/GPIO0F
/EXTINT1F
O/B
/I
104
V
189
190
E10
A9
-
-
P
B
Digital ground
SS
EXD12
3ICD/3T2
3ISUD/3T2
3ICD/3T2
3ISUD/3T2
3ICD/3T2
3R
3R
3R
3R
3R
b
b
b
b
External memory data bus bit12
UARTCh2 transmission
data/general-purpose port
/external interrupt 1- bit11
TXD2/GPIO0B
/EXTINT1B
O/B
/I
191
192
193
B9
C9
A8
105
-
EXD13
B
External memory data bus bit13
UARTCh2 receive
data/general-purpose port
/external interrupt 1- bit12
RXD2/GPIO0C
/EXTINT1C
I/B
/I
106
194
195
196
197
198
199
B8
E9
C8
D9
E8
A7
-
EXD14
Vdd2
B
P
B
P
P
O
b
b
b
External memory data bus bit14
Digital IO power supply
External memory data bus bit15
Digital ground
107
-
EXD15
3ICD/3T2
3A
3R
V
108
109
110
SS
AVssDAMPR
ROUT
Analog ground for RchDAMP
RchDAMP output
d1
d1
Analog power supply for
RchDAMP
200
E7
111
AVddDAMPR
P
201
202
203
204
205
206
207
208
209
210
D7
A6
B7
B6
C7
E6
C6
D6
D5
A5
112
113
114
115
116
117
118
119
120
-
AVddDAMPL
LOUT
P
O
P
P
O
P
P
P
P
I
d2
d2
Analog power supply for LchDAMP
LchDAMP output
3A
3A
AVssDAMPL
AVssPLL2
VCNT2
Ground for LChDAMP
Analog ground for PLL2
VCO control for PLL2
p2
p2
AVddPLL2
Analog power supply for PLL2
Digital ground
V
SS
Vdd1
Digital internal power supply
Analog power supply for ADC
ADC high reference voltage
AVddADC
VRH
a
a
3A
No.A2351-13/29
LC823425
211
212
213
214
215
216
217
218
219
220
221
B5
A4
C5
B4
A3
B3
C4
A2
E5
D4
F6
121
122
123
124
125
126
-
AN5
AN4
AN3
AN2
AN1
AN0
VR
I
I
3A
3A
3A
3A
3A
3A
3A
3A
a
a
a
a
a
a
a
a
ADC input Ch5
ADC input Ch4
I
ADC input Ch3
I
ADC input Ch2
I
ADC input Ch1
I
ADC input Ch0
O
I
ADC standard voltage
ADC [ro-rifarensu] voltage
Analog ground for ADC
Digital IO power supply
-
VRL
AVssADC
Vdd2
-
127
128
-
P
P
NC
b
No.A2351-14/29
LC823425
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
BMOD
E0
EXD1
2
EXD1
0
TIOCB
0
A
B
C
D
E
F
VRL AN1 AN4 VRH LOUT ROUT RXD2
SDO1
EXD9 EXD5 EXD3
RXD1
MPMC
DATA
AVss
DAMP
BMOD
E1
AVss
PLL2
EXD1
4
EXD1
1
TIOCB
EXA 1
8
AN0 AN2 AN5
MPMC
TXD2
SCK1 EXD7 SCK0
EXD0
1
MPMC
EXTFI
Q
VCNT EXD1 EXD1
EXA 1
6
VR
AN3 Vss
SDI1 SDO0 SDI0 EXD4 EXD1 Vdd1
DATA
DATA
2
5
3
MPMC MPMC MPMC
ADDR ADDR DATA
AVdd
DAMP
AVdd
ADC
EXA 2 TIOC
Vdd2
Vdd1
Vdd2 Vss Vss EXD8 EXD6 EXD2 Vss
0
A0
Vss
MPMC MPMC
ADDR ADDR
MPMC
DATA
AVdd AVss
DAMP DAMP
AVss AVdd
ADC PLL2
EXA 1
5
EXA 1 NLBE
EXA 1
3
Vdd2 Vss
TXD1
Vss
9
XA0
MPMC
EXTIN EXTIN
EXA 1
4
EXA 1 TIOC EXA 1
Vss Vdd2 NC
Vdd2
ADDR
T02
T00
7
A1
2
MPMC MPMC MPMC
ADDR ADDR ADDR
EXTIN
Vss
G
H
J
DIN
Vss DOUT Vss LRCK
T01
MPMC MPMC
ADDR ADDR
EXTIN EXTIN
EXA 1 EXA 1
Vdd2
Vss
BCK Vdd2 EXA9
T04
T03
1
0
MPMC
MPMC
ADDR
SDCD SDWP
EXA6 MCLK EXA3 EXA8 EXA7
ADDR
1
1
SDCM SDAT SDAT VddS
K
L
Vss
Vdd2 EXA2 Vss EXA5 SDA
BMOD
D1
10
11
D1
SDAT SDAT SDCL
12
Vdd1 XIN1
Vdd1 TEST
SCL EXA4
13
K1
E2
MPMC
DATA
MPMC
SDCL SDCM SDAT VddS XOUT
NWRE
EXA 1
NWRL
M
N
P
Vdd2
Vss
TDO Vss Vdd1 NRES
VDET Vss
DATA
K0
SDAT SDAT SDAT
01 02 03
SDCD SDWP
D0
00
D0
1
AVdd
USBP
MPMC
MPMC
DATA
MPMC
VssX
T1
TCLK
A
VssR RTCIN
Vdd2 Vss
NCS0 NRD
DATA
DATA
TMS
TC
T
AVdd AVss
USBP USBP
MPMC
MPMC
DATA
VddX VCNT
T1
MPMC MPMC
NHBN
WRH
BACK
UPB
RTCK
TCK NCS1
DATA
0
0
1
WE
DQM0
AVss AVss AVdd AVss
USBP USBP USBP USBP
MPMC
DATA
MPMC MPMC MPMC
DATA ADDR DATA
AVss TCLK
MPMC MPMC MPMC
RAS CKE CS
VddR
TC
R Vss
AVdd
Vdd2
Vss
PLL1
B
TDI
AVss USBD
MPMC
DATA
USBD USBD
AVdd
PLL1
MPMC NTRS MPMC MPMC
XOUT
XIN32
K
T
PHI
USBP
USBP EXT1
DM
DP
CAS
T
DQM1 CLK
32K
Top View
No.A2351-15/29
LC823425
Block Diagram
Top View
No.A2351-16/29
LC823425
Audio
No.A2351-17/29
LC823425
Application Circuit Example
XTAL
Peripheral circuit when oscillation operates
XIN
XOUT
R2
R1
C1
C2
Symbol
Value
XIN1/XOUT1
(48MHz)
XIN32K/XOUT32K
(32.768KHz)
R1
R2
C1
C2
1MΩ
330Ω
6pF
10MΩ
0Ω
10pF
10pF
6pF
Notes
Optimize the circuit constant for each product when you use this oscillation cell and ask to the
manufacturer of the crystal oscillator to investigate (matching investigation) because the best circuit
constant changes depending on the specification of the crystal oscillator used and the ambient
surrounding (parasitic capacitance etc. of an external substrate).
The values of parts are for reference. There is a possibility that the adjustment is needed according
to the situation of the set.
The following may be needed as the anti-noise measures of oscillation circuit.
(1) Be adjacent as much as possible, and shorten wiring between elements such as this LSI and
the crystal oscillator.
(2) GND of the oscillation circuit close to GND(VSS) of this LSI as much as possible.
(3) Do not bring the wiring pattern of the large current drive close around the oscillation circuit.
(4) Take wide pattern to avoid the effect of interference of other signals.
No.A2351-18/29
LC823425
When external clock is input
Do as follows when use the external clock signal that is generated outside of LSI by the oscillation module, etc.
XOUT
XIN
Left open
External clock
Notes
Input the signal of a full amplitude to XIN (external clock input).
“the signal of a full amplitude” means
VddXT1 = 0.93V to 1.3V, VddRTC = 0.9V to 1.3V, *Vss* = 0V
Ta =20C to +75C
Maximum voltage (V ) : 0.7*Vdd or more, and Vdd or less than Vdd.
IH
Minimum voltage (V ) : 0.3*Vdd or less, and 0V or more than 0V.
IL
(Vdd means VddXT1 in case of XIN1, and VddRTC in case of XIN32K.)
There is a possibility of influencing the signal quality when there is a long wire pattern on an circuit
board of XOUT (The terminal opens).
Therefore, recommend to cut the wire pattern on an circuit board or no wire pattern on it.
When not use the oscillation cell
Do as follows when not use the oscillation cell.
XOUT
XIN
Left open
Low or High in
Notes
Supply the voltage of recommended operating range of
VddRTC/VssRTC(XIN32K/XOUT32K) even if not use the oscillation cell.
(power supply to VddXT1/VssXT1(XIN1/XOUT1) is indispensable)
No.A2351-19/29
LC823425
PLL1 (for System)
The figure below shows the PLL1 circuit. Place the decoupling capacitor in the terminal neighborhood on the board,
and keep low noise by apart from other power supply lines.
AVssPLL1
AVddPLL1
VCNT1
C4
+
R2
C2
C3
R1
C1
AVddPLL1
AVssPLL1
Symbol
Value
100Ω
*MΩ
0.1F
0.001F
0.1F
33F
Serial number or accuracy
R1
R2
C1
C2
C3
C4
±5%
±5%
10% of volume error : ±
10% (20C to +75C) of
temperature property : ±
16CV33BS
C4 : refers to the part of mounting on the catalog of our company (CV-B S Series).
Notes
Use R2 basically by unmounting. The characteristic of PLL might be improved by mounting R2.
Place the wire pattern.
The values of parts are for reference. There is a possibility that the adjustment is needed according
to the situation of the set.
Connect with decoupling capacitor in the terminal neighborhood on the board, and keep low noise
by apart from other power supply lines.
No.A2351-20/29
LC823425
PLL2 (for Audio)
The figure below shows the PLL2 circuit. Place the decoupling capacitor in the terminal neighborhood on the board,
and keep low noise by apart from other power supply lines.
AVssPLL2
AVddPLL2
VCNT2
C4
+
R2
C2
C3
R1
C1
AVddPLL2
AVssPLL2
Symbol
R1
Value
Serial number or accuracy
100 to 220Ω
*MΩ
±5%
±5%
R2
C1
C2
C3
10% of volume error : ±
10% of temperature property : ±
(20C to +75C)
4.7F
0.01 About F
0.1F
C4
16CV33BS
33F
C4 : refers to the part of mounting on the catalog of our company (CV-B S Series).
Notes
Use R2 basically by unmounting. The characteristic of PLL might be improved by mounting R2.
Place the wire pattern.
The values of parts are for reference. There is a possibility that the adjustment is needed
according to the situation of the set.
Connect with decoupling capacitor in the terminal neighborhood on the board, and keep low noise
by apart from other power supply lines.
No.A2351-21/29
LC823425
10bit AD converter
This LSI
ADC Analog Power Supply
AVddAD
(*1)
VRH(*3)
AN5-0
VR(*2)(*3)
VRL(*3)
(*2)
AVssAD
ADC Analog Ground
(*1) It is important to get the correct ADC conversion result that the wiring resistance is accurate. Pay
attention to keeping low noize.
It is recommended that the ceramic capacitor of the high frequency type to be used as a decoupling
capacitor between AVddADC and AVssADC.
Place the capacitor close to the terminal of LSI as much as possible so that the wiring length may be
shorten as much as possible.
(*2) When the terminal VR is prepared (LC823425-13W1-E:FBGA221J is used), the ADC conversion speed
(operation clock frequency) is different depending on the value of the capacitor used. Confirm specs of
ADC.
(*3) LC823425-12G1-H:TQFP128L connects VRH and VRL with AVddADC and AVssADC in the package.
VR terminal is open in the package.
No.A2351-22/29
LC823425
USB Device
Refer to "USB20PCB design guideline" document .
No.A2351-23/29
LC823425
Example of circuit in surrounding of terminal JTAG (for ICE use and unused)
Vdd2
Vdd2
JTAG
This LSI
Connector
TCK
TCK
TDI
TDI
TMS
TMS
nTRS
nSRS
NTRS
Power on reset(*1)
(open drain output)
NRES
System reset(*2)
(open drain output)
33
RTCK
TDO
RTCK
TDO
(*1) Power-on reset is a reset signal that becomes active Low only when the power supply is turned on. The
terminal NTRST must be reset only by reset and power-on reset from JTAG.
(*2) System reset is a reset signal that becomes power-on reset and active Low demanded in addition with
the system like manual reset etc. The terminal NRES must be reset by reset and system reset from
JTAG.
Refer to the data sheet for specs for terminal NRES reset. The terminal NTRST is the same specs as the
terminal NRES.
Power-on reset (open drain output) can be realized to connect it with the ground through the capacitor as one
example.
As for the ICE unconnection, TCK, TDI, and the terminal TMS open in the state of internal pull-up ON.
The above-mentioned circuit is an example in the surrounding to correspond to both the ICE use and ICE
unused cases on the assumption of the JTAG ICE use made of YDC (Yokokawa digital computer).
Ask the manufacturer when you use other products.
No.A2351-24/29
LC823425
Example of circuit in surrounding of terminal JTAG (ICE unused)
Vdd2
This LSI
TCK
TDI
TMS
NTRS
NRES
System reset(*1)
RTCK
TDO
(*1) System reset is a reset signal that becomes power-on reset (reset signal that becomes active Low only
when the power supply is turned on) and active Low demanded in addition with the system of manual
reset etc.
TCK, TDI, and the terminal TMS open for ICE unused in the state of internal pull-up ON.
Power-on reset is at least necessary for the terminal NTRST in the same specs as the terminal NRES even
when ICE unused.
The above-mentioned circuit is an example of the assumption of the case with ICE unused, and the
simplification of the circuit in the surrounding.
No.A2351-25/29
LC823425
D class amplifier
Ron
47
220μF
μH
L
15Ω
LOUT
ROUT
Ipp(Irms)
RL
μF
1
Output wattmeter calculation
[Condition]
The DC resistance element of the coil, capacitor is small.
Maximum output amplitude =90%6 to power supply of PWM
1.2V=(AVddDAMPL, AVddDAMPR), power-supply voltage of D class amplifier
2Ω= Turning on resistance of internal transistor for D class amplifier (Ron).
15Ω= Headphone load resistance (RL)
assume the current that flows to the headphone to be Ipp
Ipp = (1200/2) × 0.9 / (15+2) = 31.7(mA)
Irms = Ipp / SQRT(2) = 22.4(mA)
Prms = Irms2 × 15 = 7.53(mW)
External power supply
D class amplifier power supply (AVddDAMPL,AVddDAMPR) must use a transient response and good power supply.
When the power supply where the transient response is bad is used and the capacity of the capacitor is small, a peculiar
pumping phenomenon to D class amplifier is generated. The power-supply voltage change when the pumping
phenomenon is generated must not exceed the recommended operating range.
6 Theoretical value of Delta-sigma circuit
No.A2351-26/29
LC823425
Power supply sequence
Background
The basis of turn on/off of the power supply is the following order (It is acceptable simultaneously).
At turning on
Vdd *(internal)
At turning off
Vdd *(IO) Vsig (external signal)
Vsig (external signal) Vdd *(IO) Vdd *(internal)
Turning on of Vdd *(outside) while Vdd *(internal) are turning off might generate the glitch on IO signals and flow of
through current.To avoid it, the above-mentioned procedure is recommended as a basis of the sequence.
Recommendation
Example 1 of sequence
After grouping power supply terminals into four , , -1, -2 groups, the following order is recommended as a
sequence according to a basic policy in this LSI (It is acceptable simultaneously).
At turning on
-1
Vsig
At turning off
Vsig
-1
(Note)
(internal circuit operation voltage)The internal logic is reset by (reset terminal input) and an
irregular state is canceled. Therefore, start up these two power supplies first of all in order of (It is
acceptable simultaneously).
-Two can be operated alone. Separately, it is assumed the RTC terminal control sequence, describes, and
refer.
No.A2351-27/29
LC823425
Example 2 of sequence
The following sequence that makes the power supply at same timing as much as possible and simplifies is possible (It
is acceptable simultaneously).
At turning on
, -1
, -1
Vsig
At turning off
Vsig
(Note)
Regarding -2, It is supposed that the signal collision with an external device cannot occur. In this case,
-2 starts up together with , -1.
Definition of power supply group
Internal power supply and analog power supplies
are entire simultaneous power supplies ON, and simultaneous power supplies OFF.
Vdd1
VddXT1
AVddPLL1
AVddUSBPHY1
External IO power supply 1
Vdd2
-1 External IO power supply2 and analog power supply
VddSD0
VddSD1
AVddUSBPHY2
AVddADC
AVddPLL2
AVddDAMPL
AVddDAMPR
-2 Internal and external IO power supply (sharing)
VddRTC
(Separately, RTC terminal control sequence is described)
No.A2351-28/29
LC823425
ORDERING INFORMATION
Device
Package
Shipping (Qty / Packing)
450 / Tray JEDEC
TQFP128L
(Pb-Free / Halogen Free)
LC823425-12G1-H
FBGA221J
(Pb-Free)
LC823425-13W1-E
840 / Tray JEDEC
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PS No.A2351-29/29
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