LC875932A(TQFP64J) [ONSEMI]
Microcontroller, 8-Bit, MROM, 12MHz, CMOS, PQFP64,;
| 型号： | LC875932A(TQFP64J) |
| 厂家： | 
ONSEMI |
| 描述： | Microcontroller, 8-Bit, MROM, 12MHz, CMOS, PQFP64, 微控制器 |
| 文件： | 总23页 (文件大小：167K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : ENA0125B
LC875932A
LC875924A
LC875916A
CMOS IC
Internal 32K/24K/16K-byte ROM and 1024-byte RAM
8-bit 1-chip Microcontroller
Overview
The SANYO LC875932A/24A/16A are 8-bit microcomputer that, centered around a CPU running at a minimum bus
cycle time of 83.3ns, integrates on a single chip a number of hardware features such as 32K/24K/16K-byte ROM,
1024-byte RAM, sophisticated 16-bit timers/counters (may be divided into 8-bit timers), a 16-bit timer/counter (may be
divided into 8-bit timers/counters or 8-bit PWMs), four 8-bit timers with a prescaler, a base timer serving as a time-of-
day clock, a high-speed clock counter, a synchronous SIO interface (with automatic block transmission/reception
capabilities), an asynchronous/synchronous SIO interface, a UART interface (full duplex), an 8-bit 11-channel AD
converter, two 12-bit PWM channels, a system clock frequency divider, ROM correction function, and a 23-source
10-vector interrupt feature.
Features
ROM
• 32768 × 8 bits (LC875932A)
• 24576 × 8 bits (LC875924A)
• 16384 × 8 bits (LC875916A)
RAM
• 1024 × 9 bits (LC875932A/24A/16A)
Minimum Bus Cycle
• 83.3ns (12MHz)
• 125ns (8MHz)
• 500ns (2MHz)
V
DD
V
DD
V
DD
=3.0 to 5.5V
=2.5 to 5.5V
=2.2 to 5.5V
Note: The bus cycle time here refers to the ROM read speed.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer
's products or
equipment.
Ver.1.04
62508HKIM 20080530-S00002 No.A0125-1/23
LC875932A/24A/16A
Minimum Instruction Cycle Time
• 250ns (12MHz)
• 375ns (8MHz)
• 1.5µs (2MHz)
V
V
V
=3.0 to 5.5V
=2.5 to 5.5V
=2.2 to 5.5V
DD
DD
DD
Ports
• Normal withstand voltage I/O ports
Ports whose I/O direction can be designated in 1-bit units 46 (P1n, P2n, P70 to P73, P80 to P86, PBn, PCn,
PWM2, PWM3, XT2)
Ports whose I/O direction can be designated in 4-bit units 8 (P0n)
• Normal withstand voltage input ports
• Dedicated oscillator ports
• Reset pins
1 (XT1)
2 (CF1, CF2)
1 (RES)
• Power pins
6 (V 1 to 3, V 1 to 3)
SS DD
Timers
• Timer 0: 16-bit timer/counter with a capture register
Mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) × 2 channels
Mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter
(with an 8-bit capture register)
Mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register)
Mode 3: 16-bit counter (with a 16-bit capture register)
• Timer 1: 16-bit timer/counter that supports PWM/toggle outputs
Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs)
+ 8-bit timer/counter with an 8-bit prescaler (with toggle outputs)
Mode 1: 8-bit PWM with an 8-bit prescaler × 2 channels
Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs)
(toggle outputs also possible from the lower-order 8 bits)
Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs)
(the lower-order 8 bits can be used as PWM)
• Timer 4: 8-bit timer with a 6-bit prescaler
• Timer 5: 8-bit timer with a 6-bit prescaler
• Timer 6: 8-bit timer with a 6-bit prescaler (with toggle outputs)
• Timer 7: 8-bit timer with a 6-bit prescaler (with toggle outputs)
• Base timer
1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler
output.
2) Interrupts programmable in 5 different time schemes
High-speed Clock Counter
• Can count clocks with a maximum clock rate of 20MHz (at a main clock of 10MHz)
• Can generate output real-time
SIO
• SIO0: 8-bit synchronous serial interface
1) LSB first/MSB first mode selectable
2)
3)
4/3 tCYC
Built-in 8-bit baudrate generator (maximum transfer clock cycle =
Automatic continuous data transmission (1 to 256 bits, specifiable in 1 bit units, suspension and resumption of
)
data transmission possible in 1 byte units)
• SIO1: 8-bit asynchronous/synchronous serial interface
Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks)
Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates)
Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks)
Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect)
No.A0125-2/23
LC875932A/24A/16A
UART
• Full duplex
• 7/8/9 bit data bits selectable
• 1 stop bit (2-bit in continuous data transmission)
• Built-in baudrate generator
AD Converter: 8 bits × 11 channels
PWM: Multifrequency 12-bit PWM × 2 channels
Remote Control Receiver Circuit (sharing pins with P73, INT3, and T0IN)
• Noise rejection function (noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC)
Watchdog Timer
• External RC watchdog timer
• Interrupt and reset signals selectable
Clock Output Function
1) Able to output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 as system clock.
2) Able to output oscillation clock of sub clock.
Interrupts
• 23 sources, 10 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests
of the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level
takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector
address takes precedence.
No.
1
Vector Address
00003H
Level
X or L
X or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
Interrupt Source
INT0
INT1
2
0000BH
00013H
3
INT2/T0L/INT4
4
0001BH
00023H
INT3/INT5/base timer0/base timer1
T0H
5
6
0002BH
00033H
T1L/T1H
7
SIO0/UART1 receive
SIO1/UART1 transmit
ADC/T6/T7
8
0003BH
00043H
9
10
0004BH
Port 0/T4/T5/PWM2, PWM3
• Priority levels X > H > L
• Of interrupts of the same level, the one with the smallest vector address takes precedence.
Subroutine Stack Levels: 512 levels (the stack is allocated in RAM)
High-speed Multiplication/Division Instructions
• 16 bits × 8 bits
• 24 bits × 16 bits
• 16 bits ÷ 8 bits
• 24 bits ÷ 16 bits
(5 tCYC execution time)
(12 tCYC execution time)
(8 tCYC execution time)
(12 tCYC execution time)
Oscillation Circuits
• RC oscillation circuit (internal): For system clock
• CF oscillation circuit:
• Crystal oscillation circuit:
For system clock, with internal Rf
For low-speed system clock, with internal Rf
No.A0125-3/23
LC875932A/24A/16A
System Clock Divider Function
• Can run on low current.
• The minimum instruction cycle selectable from 300ns, 600ns, 1.2μs, 2.4μs, 4.8μs, 9.6μs, 19.2μs, 38.4μs,
and 76.8μs (at a main clock rate of 10MHz).
Standby Function
• HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Oscillation is not halted automatically.
2) There are three ways of resetting the HALT mode.
(1) Setting the reset pin to the low level
(2) System resetting by watchdog timer
(3) Occurrence of an interrupt
• HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
1) The CF, RC, and crystal oscillators automatically stop operation.
2) There are four ways of resetting the HOLD mode.
(1) Setting the reset pin to the low level
(2) System resetting by watchdog timer
(3) Having an interrupt source established at either INT0, INT1, INT2, INT4, or INT5
* INT0 and INT1 HOLD mode reset is available only when level detection is set.
(4) Having an interrupt source established at port 0
• X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer.
1) The CF and RC oscillators automatically stop operation.
2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained.
3) There are five ways of resetting the X'tal HOLD mode.
(1) Setting the reset pin to the low level
(2) System resetting by watchdog timer
(3) Having an interrupt source established at either INT0, INT1, INT2, INT4, or INT5
* INT0 and INT1 HOLD mode reset is available only when level detection is set.
(4) Having an interrupt source established at port 0
(5) Having an interrupt source established in the base timer circuit
ROM Correction Function
• Executes the correction program on detection of a match with the program counter value.
• Correction program area size: 128 bytes
Package Form
• QIP64E (14 × 14):
• TQFP64J (7 × 7):
Lead-free type
Lead-free type
• FLGA68K (6.0 × 6.0): Lead-free type
Development Tools
• Onchip debugger: LC87F5932A+TCB87 TypeA/TypeB
No.A0125-4/23
LC875932A/24A/16A
Package Dimensions
unit : mm (typ)
Package Dimensions
unit : mm (typ)
3159A
3289
17.2
14.0
9.0
7.0
48
33
48
33
32
49
49
32
17
64
64
17
1
16
0.125
0.4
0.16
1
16
0.8
0.35
0.15
(0.5)
(1.0)
SANYO : TQFP64J(7X7)
SANYO : QIP64E(14X14)
Package Dimensions
unit : mm (typ)
3326
TOP VIEW
6.0
BOTTOM VIEW
0.3
0.5
L
K
J
H
G
F E D C B A
0.3
0.5
0.4
(0.45)
SIDE VIEW
SANYO : FLGA68K(6.0X6.0)
No.A0125-5/23
LC875932A/24A/16A
Pin Assignments
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P70/INT0/T0LCP/AN8
P71/INT1/T0HCP/AN9
P72/INT2/T0IN
P73/INT3/T0IN
RES
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PB2
PB3
PB4
PB5
PB6
XT1/AN10
PB7
LC875932A
LC875924A
LC875916A
XT2/AN11
P27/INT5/T1IN
P26/INT5/T1IN
P25/INT5/T1IN
P24/INT5/T1IN
P23/INT4/T1IN
P22/INT4/T1IN
P21/URX/INT4/T1IN
P20/UTX/INT4/T1IN
P07/T7O
V
1
SS
CF1
CF2
V
1
DD
P80/AN0
P81/AN1
P82/AN2
P10/SO0
P11/SI0/SB0
P06/T6O
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
Top view
SANYO: QIP64E (14 × 14) “Lead-free Type”
SANYO: TQFP64J (7 × 7) “Lead-free Type”
No.A0125-6/23
LC875932A/24A/16A
11
51 49 47 45 43 41 39 37 35
10 52 50 48 46 44 42 40 38 36 33 34
9
8
7
6
5
4
3
2
1
54 53
56 55
58 57
60 59
62 61
64 63
66 65
68 67
1
31 32
29 30
27 28
25 26
23 24
21 22
19 20
LC875932A
LC875924A
LC875916A
2
3
4
5
6
7
E
8
9
F
10 12 14 16 18
11 13 15 17
A
B
C
D
G
H
J
K
L
Top view
Pin Name
Pin
No.
Pin
No.
Pin
No.
Pin
No.
Pin Name
P12/SCK0
Pin Name
Pin Name
PB1
1
2
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
P06/T6O
P07/T7O
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
P70/INT0/T0LCP/AN8
P71/INT1/T0HCP/AN9
P72/INT2/T0IN
P73/INT3/T0IN
RES
P13/SO1
PB0
3
P14/SI1/SB1
P15/SCK1
P16/T1PWML
P17/T1PWMH/BUZ
PWM2
P20/UTX/INT4/T1IN
P21/URX/INT4/T1IN
P22/INT4/T1IN
P23/INT4/T1IN
P24/INT5/T1IN
P25/INT5/T1IN
P26/INT5/T1IN
P27/INT5/T1IN
PB7
V
3
3
SS
4
V
DD
5
PC7
6
PC6
XT1/AN10
XT2/AN11
7
PC5
8
PWM3
PC4
V
1
SS
9
V
V
2
PC3
CF1
CF2
V
DD
10
11
12
13
14
15
16
17
2
PC2
SS
P00
P01
P02
P03
P04
PC1
1
DD
PB6
PC0
P80/AN0
PB5
P86/AN6
P85/AN5
P84/AN4
P83/AN3
No Connect
P81/AN1
PB4
P82/AN2
PB3
P10/SO0
P05/CKO
PB2
P11/SI0/SB0
No Connect
No Connect
No Connect
Note: Pin number 17, 34, 51, 68 of NC terminals are not connected electrically. Also, A1, A11, L1, L11 are dummy
terminals for the package. These terminals need to be bonded with foot pattern for the secure bonding of
the package.
SANYO: FLGA68K (6.0 × 6.0)
“Lead-free Type”
No.A0125-7/23
LC875932A/24A/16A
System Block Diagram
Interrupt control
IR
PLA
Standby control
ROM correct
CF
RC
ROM
X’tal
PC
SIO0
Bus interface
Port 0
SIO1
ACC
B register
Timer 0
Timer 1
Timer 4
Timer 5
Timer 6
Port 1
C register
ALU
Port 2
Port 7
Port 8
ADC
PSW
RAR
INT0 to INT5
Noise filter
Timer 7
Base timer
PWM2/3
RAM
Port B
Port C
UART1
Stack pointer
Watchdog timer
Onchip debugger
(LC87F5932A)
No.A0125-8/23
LC875932A/24A/16A
Pin Description
Pin Name
I/O
Description
Option
No
V
V
V
V
V
V
1
-
-Power supply pin
+Power supply pin
• 8-bit I/O port
SS
2
3
1
SS
SS
-
No
DD
DD
DD
2
3
Port 0
I/O
Yes
• I/O specifiable in 4-bit units
• Pull-up resistors can be turned on and off in 4-bit units.
• HOLD reset input
P00 to P07
• Port 0 interrupt input
• Shared pins
P05: Clock output (system clock/can selected from sub clock)
P06: Timer 6 toggle output
P07: Timer 7 toggle output
Port 1
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 1-bit units
• Pull-up resistors can be turned on and off in 1-bit units.
• Shared pins
P10 to P17
P10: SIO0 data output
P11: SIO0 data input/bus I/O
P12: SIO0 clock I/O
P13: SIO1 data output
P14: SIO1 data input/bus I/O
P15: SIO1 clock I/O
P16: Timer 1PWML output
P17: Timer 1PWMH output/beeper output
• 8-bit I/O port
Port 2
I/O
Yes
• I/O specifiable in 1-bit units
• Pull-up resistors can be turned on and off in 1-bit units.
• Shared pins
P20 to P27
P20: UART transmit
P21: UART receive
P20 to P23: INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input
P24 to P27: INT5 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input
• Interrupt acknowledge type
Rising &
Rising
Falling
H level
L level
Falling
enable
enable
INT4
INT5
enable
enable
enable
enable
disable
disable
disable
disable
Continued on next page.
No.A0125-9/23
LC875932A/24A/16A
Continued from preceding page.
Pin Name
Port 7
I/O
I/O
Description
Option
No
• 4-bit I/O port
• I/O specifiable in 1-bit units
P70 to P73
• Pull-up resistors can be turned on and off in 1-bit units.
• Shared pins
P70: INT0 input/HOLD reset input/timer 0L capture input/watchdog timer output
P71: INT1 input/HOLD reset input/timer 0H capture input
P72: INT2 input/HOLD reset input/timer 0 event input/timer 0L capture input/
High speed clock counter input
P73: INT3 input (with noise filter)/timer 0 event input/timer 0H capture input
AD converter input port: AN8 (P70), AN9 (P71)
• Interrupt acknowledge type
Rising &
Rising
Falling
H level
L level
Falling
disable
disable
enable
enable
INT0
INT1
INT2
INT3
enable
enable
enable
enable
enable
enable
enable
enable
enable
enable
disable
disable
enable
enable
disable
disable
Port 8
I/O
• 7-bit I/O port
No
• I/O specifiable in 1-bit units
• Shared pins
P80 to P86
AD converter input port: AN0 (P80) to AN6 (P86)
• PWM2 and PWM3 output ports
• General-purpose I/O available
• 8-bit I/O port
PWM2,
PWM3
Port B
I/O
I/O
No
Yes
• I/O specifiable in 1-bit units
PB0 to PB7
• Pull-up resistors can be turned on and off in 1-bit units.
• 8-bit I/O port
Port C
I/O
Yes
• I/O specifiable in 1-bit units
PC0 to PC7
• Pull-up resistors can be turned on and off in 1-bit units.
• Shared pins (for LC87F5932A)
On-chip debugger pins: DBGP0 to DBGP2 (PC5 to PC7)
RES
XT1
Input
Input
Reset pin
No
No
• 32.768kHz crystal oscillator input pin
• Shared pins
General-purpose input port
AD converter input port : AN10
Must be connected to V 1 if not to be used.
DD
XT2
I/O
• 32.768kHz crystal oscillator output pin
• Shared pins
No
General-purpose I/O port
AD converter input port: AN11
Must be set for oscillation and kept open if not to be used.
Ceramic resonator input pin
CF1
CF2
Input
No
No
Output
Ceramic resonator output pin
No.A0125-10/23
LC875932A/24A/16A
Port Output Types
The table below lists the types of port outputs and the presence/absence of a pull-up resistor.
Data can be read into any input port even if it is in the output mode.
Option Selected
Port Name
P00 to P07
Option Type
Output Type
Pull-up Resistor
in Units of
1 bit
1
2
CMOS
Programmable (Note 1)
No
Nch-open drain
CMOS
P10 to P17
P20 to P27
1 bit
1 bit
1
Programmable
Programmable
Programmable
Programmable
Programmable
Programmable
No
2
Nch-open drain
CMOS
1
2
Nch-open drain
Nch-open drain
CMOS
P70
-
No
No
No
No
1
P71 to P73
P80 to P86
PWM2, PWM3
PB0 to PB7
-
-
-
Nch-open drain
CMOS
No
1 bit
CMOS
Programmable
Programmable
Programmable
Programmable
No
2
Nch-open drain
CMOS
PC0 to PC7
1 bit
1
2
Nch-open drain
XT1
XT2
-
-
No
Input for 32.768 kHz crystal oscillator
(Input only)
No
Output for 32.768kHz crystal oscillator
(Nch-open drain when in general-purpose
output mode)
No
Note 1: Programmable pull-up resistors for port 0 are controlled in 4-bit units (P00 to 03, P04 to 07).
*1: Connect the IC as shown below to minimize the noise input to the V 1 pin.
DD
Be sure to electrically short the V 1, V 2, and V 3 pins.
SS
SS
SS
LSI
V
1
DD
Power
supply
For backup *2
V
V
2
3
DD
DD
V
1
V
2
V
3
SS
SS
SS
*2: The internal memory is sustained by V 1. If none of V 2 and V 3 are backed up, the high level output at the
DD DD DD
ports are unstable in the HOLD backup mode, allowing through current to flow into the input buffer and thus
shortening the backup time.
Make sure that the port outputs are held at the low level in the HOLD backup mode.
No.A0125-11/23
LC875932A/24A/16A
Absolute Maximum Ratings at Ta = 25°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
Specification
typ max
Parameter
Symbol
Pin/Remarks
1, V 2, V 3
DD
Conditions
V
[V]
min
-0.3
unit
V
DD
Maximum supply
voltage
V
V
V
1=V 2=V 3
DD max
DD
DD
DD DD DD
+6.5
Input voltage
V (1)
XT1, CF1
-0.3
V
V
+0.3
I
DD
Input/output
voltage
V
(1)
Ports 0, 1, 2
Ports 7, 8
IO
-0.3
+0.3
DD
Ports B, C
PWM2, PWM3 XT2
Ports 0, 1, 2
Peak output
current
IOPH(1)
CMOS output select
Per 1 applicable pin
Per 1 applicable pin
-10
Ports B, C
IOPH(2)
IOPH(3)
IOMH(1)
PWM2, PWM3
-20
-5
P71 to P73
Per 1 applicable pin
Mean output
current
Ports 0, 1, 2
Ports B, C
CMOS output select
Per 1 applicable pin
Per 1 applicable pin
-7.5
(Note 1-1)
IOMH(2)
IOMH(3)
ΣIOAH(1)
ΣIOAH(2)
PWM2, PWM3
-15
-3
P71 to P73
P71 to P73
Per 1 applicable pin
Total output
current
Total of all applicable pins
Total of all applicable pins
-10
Port 1
-25
-25
-45
PWM2, PWM3
Ports 0, 2
ΣIOAH(3)
ΣIOAH(4)
Total of all applicable pins
Total of all applicable pins
Ports 0, 1, 2
PWM2, PWM3
Port B
ΣIOAH(5)
ΣIOAH(6)
ΣIOAH(7)
IOPL(1)
Total of all applicable pins
Total of all applicable pins
Total of all applicable pins
Per 1 applicable pin
-25
-25
-45
Port C
Ports B, C
Peak output
current
P02 to P07
Ports 1, 2
20
Ports B, C
PWM2, PWM3
P00, P01
mA
IOPL(2)
IOPL(3)
IOML(1)
Per 1 applicable pin
Per 1 applicable pin
Per 1 applicable pin
30
10
Ports 7, 8, XT2
Mean output
current
P02 to P07
Ports 1, 2
15
(Note 1-1)
Ports B, C
PWM2, PWM3
P00, P01
IOML(2)
IOML(3)
ΣIOAL(1)
Per 1 applicable pin
20
Ports 7, 8, XT2
Per 1 applicable pin
7.5
Total output
current
Port 7
Total of all applicable pins
15
P83 to P86, XT2
P80 to P82
ΣIOAL(2)
ΣIOAL(3)
ΣIOAL(4)
Total of all applicable pins
Total of all applicable pins
Total of all applicable pins
15
20
Ports 7, 8, XT2
Port 1
45
45
80
PWM2, PWM3
Ports 0, 2
ΣIOAL(5)
ΣIOAL(6)
Total of all applicable pins
Total of all applicable pins
Ports 0, 1, 2
PWM2, PWM3
Port B
ΣIOAL(7)
ΣIOAL(8)
ΣIOAL(9)
Pd max
Total of all applicable pins
Total of all applicable pins
Total of all applicable pins
Ta=-30 to +70°C
45
45
Port C
Ports B, C
80
Power dissipation
QIP64E(14 × 14)
TQFP64J(7 × 7)
FLGA68K(6.0 × 6.0)
375
170
121
mW
Operating ambient
temperature
Topr
Tstg
-30
-55
+70
°C
Storage ambient
temperature
+125
Note 1-1: The mean output current is a mean value measured over 100ms.
No.A0125-12/23
LC875932A/24A/16A
Allowable Operating Conditions at Ta = -30°C to +70°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
Specification
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
typ
max
unit
DD
Operating
V
(1)
V
1=V 2=VDD3
0.245μs ≤ tCYC ≤ 200μs
0.367μs ≤ tCYC ≤ 200μs
1.47μs ≤ tCYC ≤ 200μs
3.0
5.5
5.5
5.5
DD
DD
DD
supply voltage
2.5
2.2
Memory
VHD
V
1=V 2=V
3
DD
RAM and register contents
sustained in HOLD mode.
DD
DD
sustaining
supply voltage
High level input
voltage
2.0
5.5
V
(1)
Ports 1, 2
IH
P71 to P73
0.3V
DD
2.2 to 5.5
V
DD
P70 port input
/interrupt side
Ports 0, 8, B, C
PWM2, PWM3
+0.7
V
V
V
V
(2)
(3)
(4)
0.3V
DD
IH
IH
IH
2.2 to 5.5
V
V
DD
+0.7
Port 70 watchdog
timer side
2.2 to 5.5
0.9V
DD
DD
V
XT1, XT2, CF1
RES
2.2 to 5.5 0.75V
V
DD
DD
Low level input
voltage
(1)
Ports 1, 2
0.1V
IL
DD
4.0 to 5.5
2.2 to 4.0
V
SS
P71 to P73
+0.4
P70 port input
/interrupt side
Ports 0, 8, B, C
PWM2, PWM3
V
0.2V
SS
DD
DD
V
(2)
0.15V
IL
4.0 to 5.5
2.2 to 4.0
2.2 to 5.5
V
V
V
SS
SS
SS
+0.4
0.2V
DD
DD
V
V
(3)
(4)
Port 70 watchdog
timer side
0.8V
IL
-1.0
XT1, XT2, CF1
RES
IL
2.2 to 5.5
V
0.25V
DD
SS
Instruction cycle
time
tCYC
3.0 to 5.5
2.5 to 5.5
2.2 to 5.5
3.0 to 5.5
2.5 to 5.5
0.245
0.367
1.47
0.1
200
200
200
12
μs
(Note 2-1)
External system
clock frequency
FEXCF(1)
CF1
• CF2 pin open
• System clock frequency
division ratio=1/1
0.1
8
• External system clock duty
=50 5%
2.2 to 5.5
0.1
2
• CF2 pin open
3.0 to 5.5
2.5 to 5.5
2.2 to 5.5
0.2
0.2
0.2
24.4
16
4
• System clock frequency
division ratio=1/2
MHz
Oscillation
FmCF(1)
FmCF(2)
FmCF(3)
CF1, CF2
CF1, CF2
CF1, CF2
12MHz ceramic oscillation
See Fig. 1.
3.0 to 5.5
2.5 to 5.5
12
frequency range
(Note2-2)
8MHz ceramic oscillation
See Fig. 1.
8
4MHz ceramic oscillation
See Fig. 1.
2.2 to 5.5
2.2 to 5.5
2.2 to 5.5
4
1.0
FmRC
FsX’tal
Internal RC oscillation
0.3
2.0
XT1, XT2
32.768kHz crystal oscillation
See Fig. 2.
32.768
kHz
Note 2-1: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at
a division ratio of 1/2.
Note 2-2: See Tables 1 and 2 for the oscillation constants.
No.A0125-13/23
LC875932A/24A/16A
Electrical Characteristics at Ta = -30°C to +70°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
Specification
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
typ max
unit
DD
High level input
current
I
(1)
Ports 0, 1, 2
Ports 7, 8
Ports B, C
RES
Output disabled
Pull-up resistor off
=V
IH
V
2.2 to 5.5
1
IN DD
(Including output Tr's off leakage
PWM2, PWM3
XT1, XT2
current)
I
(2)
(3)
For input port specification
IH
2.2 to 5.5
2.2 to 5.5
1
V
=V
IN DD
I
I
CF1
V
=V
15
IH
IN DD
μA
Low level input
current
(1)
Ports 0, 1, 2
Ports 7, 8
Ports B, C
RES
Output disabled
IL
Pull-up resistor off
V
=V
2.2 to 5.5
-1
-1
IN SS
(Including output Tr's off leakage
current)
PWM2, PWM3
XT1, XT2
I
I
(2)
(3)
For input port specification
IL
2.2 to 5.5
V
V
I
=V
IN SS
CF1
=V
2.2 to 5.5
4.5 to 5.5
3.0 to 5.5
2.2 to 5.5
3.0 to 5.5
2.2 to 5.5
4.5 to 5.5
3.0 to 5.5
2.2 to 5.5
4.5 to 5.5
3.0 to 5.5
2.2 to 5.5
3.0 to 5.5
2.2 to 5.5
4.5 to 5.5
3.0 to 5.5
2.2 to 5.5
4.5 to 5.5
2.2 to 5.5
-15
-1
IL
IN SS
High level output
voltage
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
(1)
Ports 0, 1, 2
Ports B, C
=-1mA
V
OH
OH
OH
OH
OH
OH
OH
OH
OH
DD
(2)
(3)
(4)
(5)
(6)
(7)
(8)
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
=-0.4mA
V
V
V
V
V
V
V
-0.4
-0.4
-0.4
-0.4
-1.5
-0.4
-0.4
OH
DD
DD
DD
DD
DD
DD
DD
=-0.2mA
=-0.4mA
=-0.2mA
=-10mA
=-1.6mA
=-1mA
OH
OH
OH
OH
OH
OH
P71 to P73
PWM2, PWM3
V
Low level output
voltage
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
Ports 0, 1, 2
Ports B, C
=10mA
=1.6mA
=1mA
1.5
0.4
0.4
0.4
0.4
1.5
0.4
0.4
80
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
PWM2, PWM3
Ports 7, 8
XT2
=1.6mA
=1mA
P00, P01
=30mA
=5mA
=2.5mA
=0.9V
Pull-up
Rpu(1)
Rpu(2)
VHYS
Ports 0, 1, 2, 7
Ports B, C
V
15
18
35
OH
DD
kΩ
resistance
50
0.1
DD
150
RES
Hysteresis
voltage
2.2 to 5.5
V
Ports 1, 2, 7
V
Pin capacitance
CP
All pins
For pins other than that under test:
=V
V
IN SS
2.2 to 5.5
10
pF
f=1MHz
Ta=25°C
No.A0125-14/23
LC875932A/24A/16A
Serial I/O Characteristics at Ta = -30°C to +70°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
1. SIO0 Serial I/O Characteristics (Note 4-1-1)
Specification
Parameter
Symbol
Pin/Remarks
SCK0(P12)
Conditions
V
[V]
min
typ
max
unit
DD
Frequency
tSCK(1)
See Fig. 6.
2
1
1
Low level
tSCKL(1)
pulse width
High level
pulse width
tSCKH(1)
2.2 to 5.5
tCYC
tSCKHA(1)
• Continuous data
transmission/reception mode
• See Fig. 6.
4
• (Note 4-1-2)
Frequency
tSCK(2)
SCK0(P12)
• CMOS output selected
• See Fig. 6.
4/3
Low level
tSCKL(2)
1/2
1/2
pulse width
High level
pulse width
tSCK
tCYC
tSCKH(2)
2.2 to 5.5
tSCKHA(2)
• Continuous data
tSCKH(2)
+(10/3)
tCYC
transmission/reception mode
• CMOS output selected
• See Fig. 6.
tSCKH(2)
+2tCYC
Data setup time
Data hold time
tsDI(1)
thDI(1)
tdD0(1)
tdD0(2)
tdD0(3)
SI0(P11),
SB0(P11)
• Must be specified with respect
to rising edge of SIOCLK.
• See Fig. 6.
2.2 to 5.5
2.2 to 5.5
2.2 to 5.5
2.2 to 5.5
0.03
0.03
Output delay
time
SO0(P10),
SB0(P11)
• Continuous data
(1/3)tCYC
+0.05
transmission/reception mode
• (Note 4-1-3)
μs
• Synchronous 8-bit mode
• (Note 4-1-3)
1tCYC
+0.05
(Note 4-1-3)
(1/3)tCYC
+0.15
2.2 to 5.5
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock
is "H" to the first negative edge of the serial clock must be longer than tSCKHA.
Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning
of output state change in open drain output mode. See Fig. 6.
No.A0125-15/23
LC875932A/24A/16A
2. SIO1 Serial I/O Characteristics (Note 4-2-1)
Specification
typ max
Parameter
Frequency
Symbol
tSCK(3)
Pin/Remarks
SCK1(P15)
Conditions
V
[V]
min
unit
DD
See Fig. 6.
2
1
1
2
Low level
tSCKL(3)
tSCKH(3)
tSCK(4)
tSCKL(4)
tSCKH(4)
tsDI(2)
2.2 to 5.5
pulse width
High level
pulse width
Frequency
tCYC
SCK1(P15)
• CMOS output selected
• See Fig. 6.
Low level
pulse width
2.2 to 5.5
1/2
1/2
tSCK
High level
pulse width
Data setup time
SI1(P14),
SB1(P14)
• Must be specified with respect
to rising edge of SIOCLK.
• See Fig. 6.
2.2 to 5.5
2.2 to 5.5
0.03
0.03
Data hold time
thDI(2)
tdD0(4)
μs
Output delay time
SO1(P13),
SB1(P14)
• Must be specified with respect
to falling edge of SIOCLK.
• Must be specified as the time
to the beginning of output state
change in open drain output
mode.
(1/3)tCYC
+0.05
2.2 to 5.5
• See Fig. 6.
Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.
No.A0125-16/23
LC875932A/24A/16A
Pulse Input Conditions at Ta = -30°C to +70°C, V 1 = V 2 = V 3 = 0V
SS SS SS
Specification
typ max
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
unit
tCYC
μs
DD
High/low level
pulse width
tPIH(1)
INT0(P70),
• Interrupt source flag can be set.
• Event inputs for timer 0 or 1
are enabled.
tPIL(1)
INT1(P71),
INT2(P72),
2.2 to 5.5
1
2
INT4(P20 to P23),
INT5(P24 to P27)
INT3(P73) when
noise filter time
constant is 1/1
INT3(P73) when
noise filter time
constant is 1/32
INT3(P73) when
noise filter time
constant is 1/128
RES
tPIH(2)
tPIL(2)
• Interrupt source flag can be set.
• Event inputs for timer 0 are
enabled.
2.2 to 5.5
2.2 to 5.5
tPIH(3)
tPIL(3)
• Interrupt source flag can be set.
• Event inputs for timer 0 are
enabled.
64
tPIH(4)
tPIL(4)
• Interrupt source flag can be set.
• Event inputs for timer 0 are
enabled.
2.2 to 5.5
2.2 to 5.5
256
200
tPIL(5)
Resetting is enabled.
AD Converter Characteristics at Ta = -30°C to +70°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
Specification
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
typ max
unit
bit
DD
Resolution
N
AN0(P80) to
AN6(P86),
AN8(P70),
AN9(P71),
AN10(XT1),
AN11(XT2)
3.0 to 5.5
8
Absolute
accuracy
Conversion
time
ET
(Note 6-1)
3.0 to 5.5
1.5
LSB
TCAD
AD conversion time=32 × tCYC
15.68
(tCYC=
0.49μs)
23.52
97.92
(tCYC=
3.06μs)
97.92
(when ADCR2=0) (Note 6-2)
4.5 to 5.5
3.0 to 5.5
4.5 to 5.5
(tCYC=
(tCYC=
3.06μs)
97.92
0.735μs)
18.82
μs
AD conversion time=64 × tCYC
(when ADCR2=1) (Note 6-2)
(tCYC=
0.294μs)
47.04
(tCYC=
1.53μs)
97.92
3.0 to 5.5
3.0 to 5.5
(tCYC=
0.735μs)
(tCYC=
1.53μs)
Analog input
voltage range
Analog port
input current
VAIN
V
V
V
SS
DD
IAINH
IAINL
VAIN=V
DD
3.0 to 5.5
3.0 to 5.5
1
μA
VAIN=V
SS
-1
Note 6-1: The quantization error (±1/2LSB) is excluded from the absolute accuracy value.
Note 6-2: The conversion time refers to the interval from the time the instruction for starting the converter is issued
till the time the complete digital value corresponding to the analog input value is loaded in the required
register.
No.A0125-17/23
LC875932A/24A/16A
Consumption Current Characteristics at Ta = -30°C to +70°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
Specification
Pin/
Parameter
Symbol
Conditions
Remarks
V
[V]
min
typ
max
13.5
unit
DD
Normal mode
consumption
current
IDDOP(1)
V
1
• FmCF=12MHz ceramic oscillation mode
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 12MHz side
• Internal RC oscillation stopped.
• 1/1 frequency division ratio
DD
4.5 to 5.5
3.0 to 3.6
8
=V
2
3
DD
DD
=V
IDDOP(2)
IDDOP(3)
(Note 7-1)
4.5
8.5
• FmCF=8MHz ceramic oscillation mode
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 8MHz side
• Internal RC oscillation stopped.
• 1/1 frequency division ratio
4.5 to 5.5
3.0 to 3.6
2.5 to 3.0
4.5 to 5.5
3.0 to 3.6
5.5
2.9
2.3
2
9
6.8
5.3
3.2
2.3
IDDOP(4)
IDDOP(5)
IDDOP(6)
IDDOP(7)
mA
• FmCF=4MHz ceramic oscillation mode
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 4MHz side
• Internal RC oscillation stopped.
• 1/2 frequency division ratio
0.95
IDDOP(8)
IDDOP(9)
2.2 to 3.0
4.5 to 5.5
0.66
0.55
1.8
2.1
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to internal RC oscillation
• 1/2 frequency division ratio
IDDOP(10)
IDDOP(11)
IDDOP(12)
3.0 to 3.6
2.2 to 3.0
0.29
0.2
1.3
0.96
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 32.768kHz side
• Internal RC oscillation stopped.
• 1/2 frequency division ratio
4.5 to 5.5
3.0 to 3.6
2.2 to 3.0
27
11
65
38
28
IDDOP(13)
IDDOP(14)
IDDHALT(1)
µA
7.7
HALT mode
consumption
current
HALT mode
• FmCF=12MHz ceramic oscillation mode
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 12MHz side
• Internal RC oscillation stopped.
• 1/1 frequency division ratio
4.5 to 5.5
3.0 to 3.6
2.7
1.4
5.5
3
(Note 7-1)
IDDHALT(2)
IDDHALT(3)
IDDHALT(4)
IDDHALT(5)
IDDHALT(6)
IDDHALT(7)
IDDHALT(8)
HALT mode
4.5 to 5.5
3.0 to 3.6
2.5 to 3.0
4.5 to 5.5
3.0 to 3.6
2.2 to 3.0
2
1.0
0.77
1
4.2
2.5
• FmCF=8MHz ceramic oscillation mode
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 8MHz side
• Internal RC oscillation stopped.
• 1/1 frequency division ratio
mA
1.9
HALT mode
2.1
• FmCF=4MHz ceramic oscillation mode
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 4MHz side
• Internal RC oscillation stopped.
• 1/2 frequency division ratio
0.48
0.3
1.2
0.88
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors.
Continued on next page.
No.A0125-18/23
LC875932A/24A/16A
Continued from preceding page.
Specification
Pin/
Parameter
Symbol
Conditions
Remarks
V
[V]
min
typ
max
unit
mA
DD
HALT mode
consumption
current
IDDHALT(9)
V
1
HALT mode
DD
4.5 to 5.5
3.0 to 3.6
2.2 to 3.0
4.5 to 5.5
3.0 to 3.6
2.2 to 3.0
0.28
1
=V
=V
2
3
• FmCF=0Hz (oscillation stopped)
DD
DD
• FmX’tal=32.768 kHz crystal oscillation mode
• System clock set to internal RC oscillation
• 1/2 frequency division ratio
IDDHALT(10)
IDDHALT(11)
IDDHALT(12)
IDDHALT(13)
IDDHALT(14)
0.17
0.12
19
0.73
0.56
50
(Note 7-1)
HALT mode
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 32.768kHz side
• Internal RC oscillation stopped.
• 1/2 frequency division ratio
7.6
26
4.7
18
HOLD mode
consumption
current
IDDHOLD(1)
IDDHOLD(2)
IDDHOLD(3)
IDDHOLD(4)
V
V
1
HOLD mode
4.5 to 5.5
3.0 to 3.6
2.2 to 3.0
4.5 to 5.5
0.07
0.04
0.03
16
10
8
DD
µA
• CF1=V
DD
or open
(External clock mode)
6
Timer HOLD
mode
1
Timer HOLD mode
45
DD
• CF1=V
DD
or open
IDDHOLD(5)
IDDHOLD(6)
3.0 to 3.6
2.2 to 3.0
6.3
3.8
22
15
consumption
current
(External clock mode)
• FmX’tal=32.768 kHz crystal oscillation mode
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors.
UART (Full Duplex) Operating Conditions at Ta = -30°C to +70°C, V 1 = V 2 = V 3 = 0V
SS SS SS
Specification
typ max
8192/3
Parameter
Symbol
Pin/remarks
Conditions
V
[V]
min
16/3
unit
DD
2.2 to 5.5
Transfer rate
UBR
P20, P21
tCYC
Data length :
Stop bits :
Parity bits :
7, 8, and 9 bits (LSB first)
1 bit (2-bit in continuous data transmission)
None
Example of Continuous 8-bit Data Transmission Mode Processing (first transmit data=55H)
Start bit
Stop bit
End of
transmission
Start of
transmission
Transmit data (LSB first)
UBR
Example of Continuous 8-bit Data Reception Mode Processing (first receive data=55H)
Stop bit
End of
reception
Start bit
Receive data (LSB first)
Start of
reception
UBR
No.A0125-19/23
LC875932A/24A/16A
Characteristics of a Sample Main System Clock Oscillation Circuit
Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a
SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values
with which the oscillator vendor confirmed normal and stable oscillation.
Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator
Operating
Voltage
Range
[V]
Oscillation
Circuit Constant
Nominal
Vendor
Name
Stabilization Time
Oscillator Name
Remarks
Frequency
C1
C2
Rf1
Rd1
typ
max
[ms]
[pF]
[pF]
[Ω]
[Ω]
[ms]
Internal
C1, C2
12MHz
8MHz
MURATA
MURATA
CSTCE12M0G52-R0
(10)
(10)
Open
470
2.8 to 5.5
0.05
0.15
CSTCE8M00G52-R0
CSTLS8M00G53-B0
CSTCR4M00G53-R0
CSTLS4M00G53-B0
(10)
(15)
(15)
(15)
(10)
(15)
(15)
(15)
Open
Open
Open
Open
2.2k
680
2.7 to 5.5
2.5 to 5.5
2.2 to 5.5
2.2 to 5.5
0.05
0.05
0.05
0.05
0.15
0.15
0.15
0.15
Internal
C1, C2
3.3k
3.3k
Internal
C1, C2
4MHz
MURATA
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after V
goes above the operating voltage lower limit (see Figure 4).
DD
Characteristics of a Sample Subsystem Clock Oscillator Circuit
Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a SANYO-
designated oscillation characteristics evaluation board and external components with circuit constant values with which
the oscillator vendor confirmed normal and stable oscillation.
Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator
Oscillation Stabilization
Circuit Constant
Operating Voltage
Nominal
Time
Vendor Name
Oscillator Name
Range
[V]
Remarks
Frequency
C3
C4
Rf2
Rd2
typ
[s]
max
[s]
[pF]
[pF]
[Ω]
[Ω]
Applicable
CL value
=12.5pF
32.768kHz
SEIKO EPSON
MC-306
18
18
Open 560k
2.2 to 5.5
1.3
3.0
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the
instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the
oscillation to get stabilized after the HOLD mode is reset (see Figure 4).
Note : The components that are involved in oscillation should be placed as close to the IC and to one another as possible
because they are vulnerable to the influences of the circuit pattern.
XT1
XT2
CF1
CF2
Rf2
Rf1
Rd2
C4
Rd1
C2
C3
C1
X’tal
CF
Figure 1 CF Oscillator Circuit
Figure 2 XT Oscillator Circuit
0.5V
DD
Figure 3 AC Timing Measurement Point
No.A0125-20/23
LC875932A/24A/16A
V
DD
Operating V
lower limit
0V
DD
Power supply
Reset time
RES
Internal RC
oscillation
tmsCF
CF1, CF2
tmsX’tal
XT1, XT2
Operating mode
Reset
Instruction execution
Unpredictable
Reset Time and Oscillation Stabilization Time
HOLD reset signal
absent
HOLD reset signal
HOLD reset signal valid
Internal RC
oscillation
tmsCF
CF1, CF2
tmsX’tal
XT1, XT2
State
HOLD
HALT
HOLD Reset Signal and Oscillation Stabilization Time
Figure 4 Oscillation Stabilization Times
No.A0125-21/23
LC875932A/24A/16A
V
DD
R
C
Note :
RES
Determine the value of C
and R so that the
RES
RES
reset signal is present for a period of 200μs after the
supply voltage goes beyond the lower limit of the IC’s
operating voltage.
RES
RES
Figure 5 Reset Circuit
SIOCLK :
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
DATAIN :
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DO8
DATAOUT :
Data RAM
transfer period
(SIO0 only)
tSCK
tSCKH
thDI
tSCKL
SIOCLK :
DATAIN :
tsDI
tdDO
DATAOUT :
Data RAM
transfer period
(SIO0 only)
tSCKL
tSCKHA
SIOCLK :
DATAIN :
tsDI
thDI
tdDO
DATAOUT :
Figure 6 Serial I/O Output Waveforms
tPIL
tPIH
Figure 7 Pulse Input Timing Signal Waveform
No.A0125-22/23
LC875932A/24A/16A
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ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.
products described or contained herein.
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Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed
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This catalog provides information as of May, 2008. Specifications and information herein are subject
to change without notice.
No.A0125-23/23
PS
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