LC87F7CC8A(QFP80) [ONSEMI]
IC,MICROCONTROLLER,8-BIT,CMOS,QFP,80PIN,PLASTIC;
| 型号： | LC87F7CC8A(QFP80) |
| 厂家： | 
ONSEMI |
| 描述： | IC,MICROCONTROLLER,8-BIT,CMOS,QFP,80PIN,PLASTIC 微控制器 外围集成电路 |
| 文件： | 总21页 (文件大小：273K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : ENA0147
CMOS IC
FROM 128K byte, RAM 4096 byte on-chip
LC87F7CC8A
8-bit 1-chip Microcontroller
Overview
The LC877C00 series are an 8-bit single chip microcontroller with the following on-chip functional blocks. :
• CPU: operable at a minimum bus cycle time of 83.3ns
• 128K bytes Flash ROM (single 5V power supply, re-writeable on board)
• On-chip RAM: 4096 bytes
• LCD controller / driver
• 16-bit timer/counters (can be divided into 8-bit units)
• 16-bit timer / PWM (can be divided into two 8-bit timers)
• Four 8-bit timer with prescalers
• Timer for use as date/time clock
• Synchronous serial I/O port (with automatic block transmit / receive function)
• Asynchronous / synchronous serial I/O port
• 2 channel 12-bit PWM
• 12-channel × 8-bit AD converter
• High-speed clock counter
• System clock divider
• Small signal detector
• 20 source 10-vectored interrupt system
All of the above functions are fabricated on a single chip.
Features
Flash ROM
• Single 5V power supply, writeable on-board.
• Block erase in 128-byte units
• 131072 × 8 bits (LC87F7CC8A)
RAM
• 4096 × 9-bits (LC87F7CC8A)
* This production is produced and sold by SANYO under license of the Silicon Storage Technology Inc.
Specifications and information herein are subject to change without notice.
Any and all SANYO Semiconductor products described or contained herein do not have specifications
that can handle applications that require extremely high levels of reliability, such as life-support systems,
aircraft's control systems, or other applications whose failure can be reasonably expected to result in
serious physical and/or material damage. Consult with your SANYO Semiconductor representative
nearest you before usingany SANYO Semiconductor products described or contained herein in such
applications.
SANYO Semiconductor assumes no responsibility for equipment failures that result from using products
at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor
products described or contained herein.
Ver.1.42
72506HKIM B8-9264 No.A0147-1/21
LC87F7CC8A
Minimum Bus Cycle Time
• 83.3ns (12MHz)
• 100ns (10MHz)
• 250ns (4MHz)
V
DD
V
DD
V
DD
=4.5 to 5.5V
=2.8 to 5.5V
=2.2 to 5.5V
Note: The bus cycle time indicates ROM read time.
Minimum Instruction Cycle Time (tCYC)
• 250 ns (12MHz)
• 300 ns (10MHz)
• 750 ns (4MHz)
V
DD
V
DD
V
DD
=4.5 to 5.5V
=2.8 to 5.5V
=2.2 to 5.5V
Ports
• Input/output ports
Data direction programmable for each bit individually:
Data direction programmable in nibble units:
20 (P1n, P70 to P73, P8n)
8 (P0n)
(When N-channel open drain output is selected, data can be input in bit units.)
• Input ports:
• Output ports:
• LCD ports
2 (XT1, XT2)
2 (PWM2, PWM3)
Segment output:
32 (S00 to S15, S24 to S39)
4 (COM0 to COM3)
3 (V1 to V3)
Common output:
Bias terminals for LCD driver:
Other functions
Input/output ports:
Input ports:
32 (PAn, PBn, PDn, PEn)
7 (PLn)
• Oscillator pins:
• Reset pin:
2 (CF1, CF2)
1 (
RES
)
• Power supply:
6 (V 1 to 3, V 1 to 3)
SS DD
LCD Controller
• Seven display modes are available (static, 1/2, 1/3, 1/4 duty × 1/2, 1/3 bias)
• Segment output and common output can be switched to general purpose input/output ports.
Small Signal Detection (MIC signals etc)
• Counts pulses with the level which is greater than a preset value
• 2 bit counter
Timers
• Timer 0: 16-bit timer / counter with capture register
Mode 0: 2 channel 8-bit timer with programmable 8-bit prescaler and 8-bit capture register
Mode 1: 8-bit timer with 8-bit programmable prescaler and 8-bit capture register
+8-bit counter with 8-bit capture register
Mode 2: 16-bit timer with 8-bit programmable prescaler and 16-bit capture register
Mode 3: 16-bit counter with 16-bit capture register
• Timer 1: PWM / 16-bit timer/counter with toggle output function
Mode 0: 8-bit timer with 8-bit prescaler (and toggle output) +8-bit timer / counter with 8-bit prescaler
(and toggle output)
Mode 1: 2 channel 8-bit PWM with 8-bit prescaler
Mode 2: 16-bit timer/counter with 8-bit prescaler (and toggle output)
(Toggle output also possible using the lower order 8-bits)
Mode 3: 16-bit timer with 8-bit prescaler (and toggle output)
(The lower order 8 bits can be used as PWM output)
• Timer 4: 8-bit timer with 6-bit prescaler
• Timer 5: 8-bit timer with 6-bit prescaler
• Timer 6: 8-bit timer with 6-bit prescaler (and toggle output)
• Timer 7: 8-bit timer with 6-bit prescaler (and toggle output)
Continued on next page.
No.A0147-2/21
LC87F7CC8A
Continued from preceding page.
• Base Timer
1) The clock signal can be selected from any of the following :
Sub-clock (32.768kHz crystal oscillator), system clock, and prescaler output from timer 0
2) Interrupts of five different time intervals are possible.
High-speed Clock Counter
• Countable up to 20MHz clock (when using 10MHz main clock)
• Real time output
SIO
• SIO 0: 8-bit synchronous serial interface
1) LSB first/MSB first is selectable
2) Internal 8-bit baud-rate generator (fastest clock period 4/3 tCYC)
3) Consecutive automatic data communication (1 to 256 bits)
• SIO 1: 8-bit asynchronous/synchronous serial interface
Mode 0: Synchronous 8 bit serial I/O (2-wire or 3-wire, transmit clock 2 to 512 tCYC)
Mode 1: Asynchronous serial I/O (half duplex, 8 data bits, 1 stop bit, baud rate 8 to 2048 tCYC)
Mode 2: Bus mode 1 (start bit, 8 data bits, transmit clock 2 to 512 tCYC)
Mode 3: Bus mode 2 (start detection, 8 data bits, stop detection)
AD Converter: 8-bits × 12 channels
PWM: 2 Channels Multi-frequency 12-bit PWM
Remote Control Receiver Circuit (connected to P73/INT3/T0IN terminal)
• Noise rejection function (noise rejection filter’s time constant can be selected from 1/32/128 tCYC)
Watchdog Timer
• The watching time period is determined by an external RC.
• Watchdog timer can produce interrupt or system reset
Interrupts: 20 sources, 10 vectors
1) Three priority (low, high, and highest) multiple interrupts are supported. During interrupt handling, an equal
or lower priority interrupt request is postponed.
2) If interrupt requests to two or more vector addresses occur at once, the higher priority interrupt takes precedence.
In the case of equal priority levels, the vector with the lowest address takes precedence.
No.
1
Vector Address
00003H
Level
X or L
X or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
Interrupt Source
INT0
2
0000BH
00013H
INT1
3
INT2/T0L
4
0001BH
00023H
INT3/Base timer0 /Base timer1
5
T0H
6
0002BH
00033H
T1L/T1H
7
SIO0
8
0003BH
00043H
SIO1
9
ADC/MIC/T6/T7
Port 0/T4/T5/PWM2, PWM3
10
0004BH
• Priority level: X > H > L
• For equal priority levels, vector with lowest address takes precedence.
Subroutine Stack Levels: 2048 levels max
Stack is located in RAM.
No.A0147-3/21
LC87F7CC8A
High-speed Multiplication/Division Instructions
• 16 bits × 8 bits
• 24 bits × 16 bits
• 16 bits ÷ 8 bits
• 24 bits ÷ 16 bits
(5 tCYC execution time)
(12 tCYC execution time)
(8 tCYC execution time)
(12 tCYC execution time)
Oscillation Circuits
• On-chip RC oscillation for system clock use.
• CF oscillation for system clock use. (Rf built in, Rd external)
• Crystal oscillation low speed system clock use. (Rf built in, Rd external)
• On-chip frequency variable RC oscillation circuit for system clock use.
System Clock Divider Function
• Low power consumption operation is available
• Minimum instruction cycle time (300ns, 600ns, 1.2µs, 2.4µs, 4.8µs, 9.6µs, 19.2µs, 38.4µs, 76.8µs can be switched
by program (when using 10MHz main clock)
Standby Function
• HALT mode
HALT mode is used to reduce power consumption. During the HALT mode, program execution is stopped but
peripheral circuits keep operating (some parts of serial transfer operation stop).
1) Oscillation circuits are not stopped automatically.
2) Released by the system reset or interrupts.
• HOLD mode
HOLD mode is used to reduce power consumption. Program execution and peripheral circuits are stopped.
1) CF, RC, X’tal and multi-frequency RC oscillation circuits stop automatically.
2) Released by any of the following conditions.
(1) Low level input to the reset pin
(2) Specified level input to one of INT0, INT1, and INT2
(3) Port 0 interrupt
• X’tal HOLD made
X’tal HOLD mode is used to reduce power consumption. Program execution is stopped.
All peripheral circuits except the base timer are stopped.
1) CF, RC and multi-frequency RC oscillation circuits stop automatically.
2) Crystal oscillator operation is kept in its state at HOLD mode inception.
3) Released by any of the following conditions
(1) Low level input to the reset pin
(2) Specified level input to one of INT0, INT1, and INT2
(3) Port 0 interrupt
(4) Base-timer interrupt
Package Form
• QFP80 (14 × 14):
• TQFP80J (12 × 12):
Lead-free type
Lead-free type
Development Tools
• Evaluation chip:
• Emulator:
LC87EV690
EVA62S + ECB876600D + SUB877100 + POD80QFP(14 × 14) or POD80SQFP
ICE-B877300 + SUB877100 + POD80QFP(14 × 14) or POD80SQFP
• Flash ROM write adapter: W87F71256QF or W87F71256SQ
Same Package and Pin Assignment as Mask ROM Version.
1) LC877C00 series options can be set by using flash ROM data. Thus the board used for mass production can be
used for debugging and evaluation without modifications.
2) If the program for the mask ROM version is used, the usable ROM/RAM capacity is the same as the mask ROM
version.
No.A0147-4/21
LC87F7CC8A
Package Dimensions
unit : mm (typ)
Package Dimensions
unit : mm (typ)
3255
3290
17.2
14.0
12.0
14.0
60
41
60
41
61
40
61
40
21
80
21
80
1
20
0.125
20
1
0.5
0.2
0.25
0.15
0.65
(0.83)
(1.25)
SANYO : QFP80(14X14)
SANYO : TQFP80J(12X12)
Pin Assignment
COM0/PL0
COM1/PL1
COM2/PL2
COM3/PL3
PWM2
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
V
V
2
2
SS
DD
S14/PB6
S13/PB5
S12/PB4
S11/PB3
S10/PB2
S9/PB1
S8/PB0
S7/PA7
S6/PA6
S5/PA5
S4/PA4
S3/PA3
S2/PA2
S1/PA1
V
V
PWM3
P00
3
3
SS
DD
LC87F7CC8A
P01
P02
P03
P04
P05
P06
P07
P10/SO0
P11/SI0/SB0
P12/SCK0
P13/SO1
S0/PA0
P73/INT3/T0IN
P72/INT2/T0IN
P71/INT1/T0HCP/AN9
Top view
SANYO : QFP80 (14 × 14)
“Lead-free Type”
SANYO : TQFP80J (12 × 12) “Lead-free Type”
No.A0147-5/21
LC87F7CC8A
System Block Diagram
Interrupt control
Stanby control
IR
PLA
Flash ROM
CF
RC
MRC
PC
X’tal
SIO0
SIO1
Bus interface
Port 0
ACC
B register
Timer 0
(High speed clock counter)
Port 1
Port 7
C register
Timer 1
ALU
Port 8
Base Timer
LCD Controller
PWM
ADC
PSW
RAR
INT0 to 3
Noise Rejection Filter
Weak Signal
Detector
RAM
Timer 4
Timer 5
Timer 6
Timer 7
Stack pointer
Watchdog timer
No.A0147-6/21
LC87F7CC8A
Pin Description
Pin name
I/O
Description
Option
No
V
V
1, V 2,
-
• Power supply (-)
SS
SS
3
SS
V
V
1, V
2
DD
-
• Power supply (+)
• 8-bit input/output port
No
DD
DD
3
PORT0
I/O
Yes
P00 to P07
• Data direction programmable in nibble units
• Use of pull-up resistor can be specified in nibble units
• Input for HOLD release
• Input for port 0 interrupt
• Other functions
P05: clock output (system clock/can selected from sub clock)
P06: timer 6 toggle output
P07: timer 7 toggle output
PORT1
I/O
• 8-bit input/output port
Yes
P10 to P17
• Data direction programmable for each bit
• Use of pull-up resistor can be specified for each bit individually
• Other pin functions
P10 SIO0 data output
P11 SIO0 data input or bus input/output
P12 SIO0 clock input/output
P13 SIO1 data output
P14 SIO1 data input or bus input/output
P15 SIO1 clock input/output
P16: Timer 1 PWML output
P17: Timer 1 PWMH output/buzzer output
• 4-bit Input/output port
PORT7
I/O
No
P70 to P73
• Data direction can be specified for each bit
• Use of pull-up resistor can be specified for each bit individually
• Other functions
P70: INT0 input/HOLD release input/timer0L capture input/output for watchdog timer
P71: INT1 input/HOLD release input/timer0H capture input
P72: INT2 input/HOLD release input/timer 0 event input/timer0L capture input
P73: INT3 input(noise rejection filter attached)/timer 0 event input/timer0H capture input
AD input port: AN8(P70), AN9(P71)
• Interrupt detection selection
Rising and
Rising
Falling
H level
L level
falling
disable
disable
enable
enable
INT0
INT1
INT2
INT3
enable
enable
enable
enable
enable
enable
enable
enable
enable
enable
disable
disable
enable
enable
disable
disable
Continued on next page.
No.A0147-7/21
LC87F7CC8A
Continued from preceding page.
Pin name
PORT8
I/O
I/O
Description
Option
No
• 8-bit Input/output port
P80 to P87
• Input/output can be specified for each bit individually
• Other functions:
AD input port: AN0 to AN7
Small signal detector input port: MICIN(P87)
• Segment output for LCD
S0/PA0 to
S7/PA7
I/O
I/O
I/O
I/O
I/O
I/O
No
No
No
No
No
No
• Can be used as general-purpose input/output port (PA)
• Segment output for LCD
S8/PB0 to
S15/PB7
• Can be used as general-purpose input/output port (PB)
• Segment output for LCD
S24 /PD0 to
S31/PD7
S32/PE0 to
S39/PE7
• Can be used as general-purpose input/output port (PD)
• Segment output for LCD
• Can be used as general-purpose input/output port (PE)
• Common output for LCD
COM0/PL0 to
COM3/PL3
V1/PL4 to
V3/PL6
• Can be used as general-purpose input port (PL)
• LCD output bias power supply
• Can be used as general-purpose input port (PL)
PWM2 output port
PWM2
O
O
I
No
No
No
No
PWM3
RES
PWM3 output port
Reset terminal
XT1
I
• Input for 32.768kHz crystal oscillation
• Other functions:
General-purpose input port
AD input port: AN10
• When not in use, connect to V
1
DD
XT2
I/O
• Output for 32.768kHz crystal oscillation
• Other functions:
No
General-purpose input port
AD input port: AN11
• When not in use, set to oscillation mode and leave open
Input terminal for ceramic oscillator
CF1
CF2
I
No
No
O
Output terminal for ceramic oscillator
No.A0147-8/21
LC87F7CC8A
Port Output Types
Port form and pull-up resistor options are shown in the following table.
Port status can be read even when port is set to output mode.
Option Selected
Port Name
Option Type
Output Type
Pull-up Resistor
in Units of
each bit
P00 to P07
1
2
CMOS
Programmable (Note 1)
None
Nch-open drain
CMOS
P10 to P17
each bit
1
Programmable
Programmable
Programmable
Programmable
None
2
Nch-open drain
Nch-open drain
CMOS
P70
-
-
-
-
None
None
None
None
P71 to P73
P80 to P87
Nch-open drain
CMOS
S0/PA0 to S15/PB7
S24/PD7 to S39/PE7
COM0/PL0 to
Programmable
-
None
Input only
None
COM3/PL3
V1/PL4 to V3/PL6
-
-
-
-
None
None
None
None
Input only
CMOS
None
None
None
None
PWM2, PWM3
XT1
XT2
Input only
Output for 32.768kHz crystal oscillation
Note 1: Attachment of Port0 programmable pull-up resistors is controllable in nibble units (P00 to 03, P04 to 07).
*1: Connect as follows to reduce noise on V
.
DD
V
1, V 2, and V 3 must be connected together and grounded.
SS SS SS
LSI
V
1
DD
Power
supply
Back-up capacitors *2
V
V
2
3
DD
DD
V
1
V
2
V
3
SS
SS
SS
*2: The power supply for the internal memory is V 1 but it uses the V 2 as the power supply for ports.
DD DD
When the V 2 is not backed up, the port level does not become “H” even if the port latch is in the “H” level.
DD
Therefore, when the V 2 is not backed up and the port latch is “H” level, the port level is unstable in the HOLD
DD
mode, and the back up time becomes shorter because the through current runs from V
to GND in the input buffer.
DD
If V 2 is not backed up, output “L” by the program or pull the port to “L” by the external circuit in the HOLD
DD
mode so that the port level becomes “L” level and unnecessary current consumption is prevented.
No.A0147-9/21
LC87F7CC8A
Absolute Maximum Ratings at Ta = 25°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
Specification
typ max
+6.5
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
-0.3
unit
DD
Supply voltage
V
max
V
1, V 2, V
3
V
V
1=V 2=V
DD
3
3
DD
DD
DD
DD
DD
DD
Supply voltage
for LCD
VLCD
V1/PL4, V2/PL5,
V3/PL6
1=V 2=V
DD
DD
DD
-0.3
-0.3
V
DD
Input voltage
V
I
Port L
V
V
V
+0.3
DD
XT1, XT2, CF1,
• Ports 0, 1, 7, 8
RES
Input/Output
voltage
V
(1)
IO
• Ports A, B, D, E
• PWM2, PWM3
Ports 0,1
-0.3
+0.3
DD
Peak
IOPH(1)
• CMOS output selected
• Current at each pin
Current at each pin
-10
-5
output
current
IOPH(2)
IOPH(3)
Ports 71,72,73
• Ports A, B, D, E
• PWM2, PWM3
Ports 0,1
Current at each pin
-5
Average
output
IOMH(1)
• CMOS output selected
• Current at each pin
Current at each pin
-7.5
-3
current
IOMH(2)
IOMH(3)
Ports 71, 72, 73
(Note 1-1)
• Ports A, B, D, E
• PWM2, PWM3
• Ports 0, 1
Current at each pin
-3
Total
∑IOAH(1)
Total of all pins
-25
output
current
• PWM2, PWM3
Port 7
∑IOAH(2)
∑IOAH(3)
∑IOAH(4)
∑IOAH(5)
IOPL(1)
Total of all pins
-10
-25
-25
-45
Ports A, B,
Ports D, E
Ports A, B, D, E
Ports 0, 1
Total of all pins
Total of all pins
mA
Total of all pins
Peak
Current at each pin
Current at each pin
Current at each pin
20
10
output
current
IOPL(2)
Ports 7,8
IOPL(3)
• Ports A, B, D, E
• PWM2, PWM3
Ports 0, 1
10
Average
output
IOML(1)
IOML(2)
IOML(3)
Current at each pin
Current at each pin
Current at each pin
15
Ports 7, 8
7.5
current
• Ports A, B, D, E
• PWM2, PWM3
• Ports 0, 1
7.5
45
(Note 1-1)
Total
∑IOAL(1)
Total of all pins
output
current
• PWM2, PWM3
Ports 7, 8
∑IOAL(2)
∑IOAL(3)
∑IOAL(4)
∑IOAL(5)
Pd max
Total of all pins
Total of all pins
Total of all pins
Total of all pins
Ta = -20 to +70°C
15
45
Ports A, B
Ports D, E
45
Ports A, B, D, E
QFP80(14×14)
TQFP80J(12×12)
80
Maximum power
consumption
381
325
mW
Operating
temperature
range
Topr
Tstg
-20
-55
+70
°C
Storage
temperature
range
+125
Note 1-1: Average output current indicates average value for 100ms term.
No.A0147-10/21
LC87F7CC8A
Allowable Operating Range at Ta = -20°C to +70°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
Specification
Parameter
Symbol
Pin/Remarks
1=V 2=V 3
DD
Conditions
V
[V]
min
typ max
unit
DD
Operating
supply voltage
range
V
(1)
(2)
(3)
V
0.245µs≤ tCYC≤ 200µs
0.294µs≤ tCYC≤ 200µs
0.735µs≤ tCYC≤ 200µs
4.5
2.8
5.5
5.5
DD
DD
DD
DD
DD
V
V
2.2
5.5
(Note2-1)
Supply
VHD
V
1
Keep RAM and register data in
HOLD mode.
DD
voltage range
in Hold mode
Input high
voltage
2.0
DD
5.5
V
V
(1)
• Ports 0, 8
Output disable
Output disable
0.3V
IH
2.2 to 5.5
2.2 to 5.5
V
V
DD
• Ports A, B, D, E, L
• Port 1
+0.7
(2)
IH
• Ports 71, 72, 73
• P70
0.3V
DD
DD
+0.7
port input/interrupt
P87 small signal input
V
V
(3)
(4)
Output disable
Output disable
2.2 to 5.5
2.2 to 5.5
2.2 to 5.5
4.0 to 5.5
2.2 to 4.0
4.0 to 5.5
0.75V
V
V
IH
DD
DD
DD
DD
Port 70
IH
V
0.9V
DD
Watchdog timer
V
V
(5)
XT1, XT2, CF1,
• Ports 0, 8
RES
0.75V
V
IH
DD
Input low
voltage
(1)
Output disable
Output disable
0.15V
IL
DD
V
V
V
SS
SS
SS
• Ports A, B, D, E, L
+0.4
V
V
(2)
(3)
0.2V
IL
DD
DD
• Port 1
0.1V
IL
• Ports 71, 72, 73
• P70 port
+0.4
V
V
V
V
(4)
(5)
(6)
(7)
IL
IL
IL
IL
2.2 to 4.0
2.2 to 5.5
2.2 to 5.5
V
0.2V
DD
SS
SS
input/interrupt
Port 87 small signal
Input
Output disable
Output disable
V
0.25V
0.8V
DD
DD
Port 70
V
V
SS
Watchdog timer
-1.0
XT1, XT2, CF1,
RES
2.8 to 5.5
4.5 to 5.5
2.8 to 5.5
2.2 to 5.5
4.5 to 5.5
2.8 to 5.5
2.2 to 5.5
4.5 to 5.5
2.8 to 5.5
2.2 to 5.5
0.25V
DD
SS
Operation
cycle time
(Note 2-2)
tCYC
0.245
0.294
0.735
0.1
200
µs
200
200
12
External
FEXCF(1)
CF1
• CF2 open
system clock
frequency
• system clock divider :1/1
0.1
10
• external clock DUTY = 50 ± 5%
0.1
4
MHz
• CF2 open
0.2
24.4
20
• system clock divider :1/2
0.2
0.2
8
Oscillation
frequency
range
FmCF(1)
FmCF(2)
FmCF(3)
CF1, CF2
12MHz ceramic resonator
oscillation
4.5 to 5.5
2.8 to 5.5
2.2 to 5.5
12
See Fig. 1.
(Note 2-3)
10MHz ceramic resonator
oscillation
10
4
See Fig. 1.
MHz
4MHz ceramic resonator
oscillation
See Fig. 1.
FmRC
RC oscillation
2.2 to 5.5
2.2 to 5.5
0.3
1.0
16
2.0
FmMRC
Frequency variable RC
oscillation source oscillation
32.768kHz crystal resonator
oscillation
FsX’tal
XT1, XT2
2.2 to 5.5
32.768
kHz
See Fig. 2.
Note 2-1: V
DD
must be held greater than or equal to 3.0V in the flash ROM onboard programming mode.
Note 2-2: Oscillation frequency and Operation cycle time (tCYC) rerationship: 1/1divide-3/FmCF, 1/2divide-6/FmCF
Note 2-3: The parts value of oscillation circuit is shown in Table 1 and Table 2.
No.A0147-11/21
LC87F7CC8A
Electrical Characteristics at Ta = -20°C to +70°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
Specification
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
typ max
unit
DD
High level input
current
I
(1)
• Ports 0, 1, 7, 8
• Ports A, B, D,
E, L
• Output disabled
IH
• Pull-up resister OFF.
• V =V
IN DD
2.2 to 5.5
1
• PWM2, PWM3
(including OFF state leak current
of the output Tr.)
I
I
(2)
(3)
V
=V
RES
2.2 to 5.5
2.2 to 5.5
2.2 to 5.5
4.5 to 5.5
1
1
IH
IN DD
XT1, XT2
When configured as an
IH
input port. V =V
IN DD
I
I
(4)
(5)
CF1
V
=V
15
20
IH
IN DD
P87/AN7/MICIN
small signal input
• Ports 0, 1, 7, 8
• Ports A, B, D,
E, L
V
=V
+0.5V
IH
IN BIS
5
10
(V
: Bias voltage)
BIS
Low level input
current
I
(1)
• Output disabled
IL
µA
• Pull-up resister OFF.
• V =V
IN SS
2.2 to 5.5
-1
• PWM2, PWM3
(including OFF state leak current
of the output Tr.)
I
I
(2)
(3)
V
=V
RES
2.2 to 5.5
2.2 to 5.5
2.2 to 5.5
-1
-1
IL
IN SS
XT1,XT2
When configured as an
IL
input port. V =V
IN SS
I
I
(4)
(5)
CF1
V
=V
-15
-20
IL
IN SS
P87/AN7/MICIN
small signal input
V
=V
-0.5V
IL
IN BIS
(V
: Bias voltage)
BIS
4.5 to 5.5
-10
-5
High level output
voltage
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
(1)
Ports 0, 1: CMOS
output option
I
=-1.0mA
=-0.4mA
=-0.2mA
=-0.4mA
=-0.2mA
=-1.0mA
=-0.4mA
=-0.2mA
4.5 to 5.5
3.0 to 5.5
2.2 to 5.5
3.0 to 5.5
2.2 to 5.5
4.5 to 5.5
3.0 to 5.5
2.2 to 5.5
4.5 to 5.5
3.0 to 5.5
2.2 to 5.5
3.0 to 5.5
2.2 to 5.5
3.0 to 5.5
2.2 to 5.5
V
-1
-0.4
-0.4
-0.4
-0.4
-1
OH
OH
OH
OH
OH
OH
OH
OH
OH
DD
(2)
(3)
(4)
(5)
(6)
(7)
(8)
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
V
V
V
V
OH
OH
OH
OH
OH
OH
OH
DD
DD
DD
Port 7
DD
V
• Ports A, B, D, E,
• PWM2, PWM3
DD
V
V
-0.4
DD
-0.4
DD
Low level output
voltage
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Ports 0, 1
Ports 7, 8
=10mA
=1.6mA
=1.0mA
=1.6mA
=1.0mA
=1.6mA
=1.0mA
1.5
0.4
0.4
0.4
0.4
0.4
0.4
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
V
• Ports A, B, D, E,
• PWM2, PWM3
LCD output voltage
regulation
VODLS
S0 to S15,
S24 to S39
=0mA
O
VLCD, 2/3VLCD, 1/3VLCD
level output
2.2 to 5.5
2.2 to 5.5
0
0
±0.2
±0.2
See Fig. 8.
VODLC
COM0 to COM3
I =0mA
O
VLCD, 2/3VLCD, 1/2VLCD
1/3VLCD level output
See Fig. 8.
LCD bias resistor
RLCD(1)
RLCD(2)
Resistance per
one bias resistor
• Resistance per
one bias resistor
• 1/2R mode
See Fig. 8.
2.2 to 5.5
2.2 to 5.5
60
30
kΩ
See Fig. 8.
Continued on next page.
No.A0147-12/21
LC87F7CC8A
Continued from preceding page.
Specification
typ max
Parameter
Symbol
Rpu
Pin/Remarks
Conditions
=0.9V
V
[V]
min
unit
DD
Resistance of
• Ports 0, 1, 7
V
OH
4.5 to 5.5
2.2 to 4.5
15
18
35
50
80
DD
kΩ
pull-up MOS Tr.
• Ports A, B, D, E
150
Hysterisis voltage
Pin capacitance
Input sensitivity
VHYS(1)
VHYS(2)
CP
• Ports 1, 7
2.2 to 5.5
2.2 to 5.5
0.1V
0.1V
DD
•
RES
V
Port 87 small
signal input
All pins
DD
• All Other Terminals Connected
To V
.
SS
2.2 to 5.5
2.2 to 5.5
10
pF
• f=1MHz
• Ta=25°C
Vsen
Port 87 small
signal input
0.12V
Vp-p
DD
Serial I/O Characteristics at Ta = -20°C to +70°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
1. SIO0 Serial I/O Characteristics (Note 4-1-1)
Specification
Parameter
Symbol
Pin/Remarks
SCK0(P12)
Conditions
V
[V]
min
typ
max
unit
DD
Frequency
tSCK(1)
See Fig. 6.
2
1
1
Low level
tSCKL(1)
pulse width
High level
pulse width
tSCKH(1)
2.2 to 5.5
tCYC
tSCKHA(1)
• Continuous data
transmission/reception mode
• See Fig. 6.
4
• (Note 4-1-2)
Frequency
tSCK(2)
SCK0(P12)
• CMOS output selected
• See Fig. 6.
4/3
Low level
tSCKL(2)
1/2
1/2
pulse width
High level
pulse width
tSCK
tCYC
tSCKH(2)
2.2 to 5.5
tSCKHA(2)
• Continuous data
tSCKH(2)
transmission/reception mode
• CMOS output selected
• See Fig. 6.
tSCKH(2)
+2tCYC
+(10/3)
tCYC
Data setup time
Data hold time
tsDI(1)
thDI(1)
tdD0(1)
tdD0(2)
tdD0(3)
SB0(P11),
SI0(P11)
• Must be specified with respect
to rising edge of SIOCLK.
• See Fig. 6.
2.2 to 5.5
2.2 to 5.5
2.2 to 5.5
2.2 to 5.5
0.03
0.03
Output delay
time
SO0(P10),
SB0(P11)
• Continuous data
(1/3)tCYC
+0.05
transmission/reception mode
• (Note 4-1-3)
µs
• Synchronous 8-bit mode
• (Note 4-1-3)
1tCYC
+0.05
(Note 4-1-3)
(1/3)tCYC
+0.15
2.2 to 5.5
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock
is "H" to the first negative edge of the serial clock must be longer than tSCKHA.
Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning
of output state change in open drain output mode. See Fig. 6.
No.A0147-13/21
LC87F7CC8A
2. SIO1 Serial I/O Characteristics (Note 4-2-1)
Specification
typ max
Parameter
Frequency
Symbol
tSCK(3)
Pin/Remarks
SCK1(P15)
Conditions
V
[V]
min
unit
DD
See Fig. 6.
2
1
1
2
Low level
tSCKL(3)
tSCKH(3)
tSCK(4)
tSCKL(4)
tSCKH(4)
tsDI(2)
2.2 to 5.5
pulse width
High level
pulse width
Frequency
tCYC
SCK1(P15)
• CMOS output selected
• See Fig. 6.
Low level
pulse width
2.2 to 5.5
1/2
1/2
tSCK
High level
pulse width
Data setup time
SB1(P14),
SI1(P14)
• Must be specified with respect
to rising edge of SIOCLK.
• See Fig. 6.
2.2 to 5.5
2.2 to 5.5
0.03
0.03
Data hold time
thDI(2)
tdD0(4)
µs
Output delay time
SO1(P13),
SB1(P14)
• Must be specified with respect
to falling edge of SIOCLK.
• Must be specified as the
time to the beginning of
output state change in
open drain output mode.
• See Fig. 6.
(1/3)tCYC
+0.05
2.2 to 5.5
Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.
No.A0147-14/21
LC87F7CC8A
Pulse Input Conditions at Ta = -20°C to +70°C, V 1 = V 2 = V 3 = 0V
SS SS SS
Specification
typ max
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
unit
tCYC
µs
DD
High/low level
pulse width
tPIH(1)
INT0(P70),
• Condition that interrupt is accepted
• Condition that event input to
timer 0 is accepted
tPIL(1)
INT1(P71),
INT2(P72)
2.2 to 5.5
1
2
INT4(P30 to P33)
INT5(P34 to P35)
INT3(P73)
tPIH(2)
tPIL(2)
• Condition that interrupt is accepted
• Condition that event input to
timer 0 is accepted
(Noise rejection
ratio is 1/1.)
2.2 to 5.5
2.2 to 5.5
2.2 to 5.5
tPIH(3)
tPIL(3)
INT3(P73)
• Condition that interrupt is accepted
• Condition that event input to
timer 0 is accepted
(Noise rejection
ratio is 1/32.)
INT3(P73)
64
tPIH(4)
tPIL(4)
• Condition that interrupt is accepted
• Condition that event input to
timer 0 is accepted
(Noise rejection
ratio is 1/128.)
MICIN(P87)
256
tPIL(5)
tPIL(5)
tPIL(6)
• Condition that signal is accepted to
small signal detection counter.
• Condition that reset is accepted
2.2 to 5.5
2.2 to 5.5
1
RES
200
AD Converter Characteristics at Ta = -20°C to +70°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
Specification
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
typ max
unit
bit
DD
Resolution
N
AN0(P80) to
AN7(P87),
AN8(P70),
AN9(P71),
AN10(XT1),
AN11(XT2)
3.0 to 5.5
8
Absolute
precision
Conversion
time
ET
(Note 6-1)
3.0 to 5.5
±1.5
LSB
TCAD
AD conversion time=32 × tCYC
15.62
97.92
(tCYC=
3.06µs)
97.92
(ADCR2=0) (Note 6-2)
4.5 to 5.5
3.0 to 5.5
4.5 to 5.5
(tCYC=
0.488µs)
23.52
µs
(tCYC=
0.735µs)
18.82
(tCYC=
3.06µs)
97.92
AD conversion time=64 × tCYC
(ADCR2=1) (Note 6-2)
(tCYC=
0.294µs)
47.04
(tCYC=
1.53µs)
97.92
3.0 to 5.5
3.0 to 5.5
(tCYC=
0.735µs)
(tCYC=
1.53µs)
Analog input
voltage range
Analog port
input current
VAIN
V
V
V
SS
DD
IAINH
IAINL
VAIN=V
DD
3.0 to 5.5
3.0 to 5.5
1
µA
VAIN=V
SS
-1
Note 6-1: Absolute precision does not include quantizing error (±1/2 LSB).
Note 6-2: Conversion time means time from executing AD conversion instruction to loading complete digital value
to register.
No.A0147-15/21
LC87F7CC8A
Consumption Current Characteristics at Ta = -20°C to +70°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
Specification
Pin/
Parameter
Symbol
Conditions
Remarks
V
[V]
min
typ max
unit
DD
Current
IDDOP(1)
V
1
• FmCF=12MHz ceramic resonator oscillation
• FsX’tal=32.768kHz crystal oscillation
• System clock: CF 12MHz oscillation
• Frequency variable RC oscillation stopped
• Internal RC oscillation stopped.
• Divider: 1/1
DD
consumption
during normal
operation
=V
2
3
DD
DD
=V
4.5 to 5.5
7.2
20
(Note 7-1)
IDDOP(2)
IDDOP(3)
• FmCF=10MHz ceramic resonator oscillation
• FsX’tal=32.768kHz crystal oscillation
• System clock: CF 10MHz oscillation
• Frequency variable RC oscillation stopped
• Internal RC oscillation stopped.
• Divider: 1/1
4.5 to 5.5
3.0 to 3.6
2.8 to 3.0
4.5 to 5.5
3.0 to 3.6
2.2 to 3.0
6.6
3.8
2.5
2.5
1.4
0.9
16.5
9.6
7.4
6.3
3.5
2.7
IDDOP(4)
IDDOP(5)
• FmCF=4MHz ceramic resonator oscillation
• FsX’tal=32.768kHz crystal oscillation
• System clock: CF 4MHz oscillation
• Internal RC oscillation stopped.
• Frequency variable RC oscillation stopped
• Divider:1/1
mA
IDDOP(6)
IDDOP(7)
IDDOP(8)
IDDOP(9)
IDDOP(10)
IDDOP(11)
• FmCF=0Hz (No oscillation)
4.5 to 5.5
3.0 to 3.6
2.2 to 3.0
0.75
0.4
3.1
1.7
• FsX’tal=32.768kHz crystal oscillation
• Frequency variable RC oscillation stopped
• System clock: RC oscillation
• Divider:1/2
0.28
1.35
•FmCF=0Hz (No oscillation)
4.5 to 5.5
3.0 to 3.6
2.2 to 3.0
4.5 to 5.5
3.0 to 3.6
2.2 to 3.0
1.3
0.7
0.5
35
5.4
3.1
2.4
115
65
•FsX’tal=32.768kHz crystal oscillation
•Internal RC oscillation stopped.
•System clock: 1MHz with frequency variable
RC oscillation
IDDOP(12)
IDDOP(13)
IDDOP(14)
•Divider:1/2
• FmCF=0Hz (No oscillation)
• FsX’tal=32.768kHz crystal oscillation
• System clock: 32.768kHz
IDDOP(15)
µA
18
• Internal RC oscillation stopped.
• Frequency variable RC oscillation stopped
• Divider:1/2
IDDOP(16)
12
46
Current
IDDHALT(1)
HALT mode
consumption
during HALT
mode
• FmCF=12MHz ceramic resonator oscillation
• FsX’tal=32.768kHz crystal oscillation
• System clock: CF 12MHz oscillation
• Internal RC oscillation stopped.
• Frequency variable RC oscillation stopped
• Divider: 1/1
4.5 to 5.5
3
7.8
(Note 7-1)
IDDHALT(2)
IDDHALT(3)
HALT mode
4.5 to 5.5
3.0 to 3.6
2.8 to 3.0
4.5 to 5.5
3.0 to 3.6
2.2 to 3.0
2.6
1.4
1
5.9
3.3
• FmCF=10MHz ceramic resonator oscillation
• FsX’tal=32.768kHz crystal oscillation
• System clock: CF 10MHz oscillation
• Internal RC oscillation stopped.
• Frequency variable RC oscillation stopped
• Divider: 1/1
mA
IDDHALT(4)
IDDHALT(5)
2.5
HALT mode
1.15
0.6
0.4
2.65
1.5
• FmCF=4MHz ceramic resonator oscillation
• FsX’tal=32.768kHz crystal oscillation
• System clock: CF 4MHz oscillation
• Internal RC oscillation stopped.
• Frequency variable RC oscillation stopped
• Divider: 1/1
IDDHALT(6)
IDDHALT(7)
1.1
Note 7-1: The currents through the output transistors and the pull-up MOS transistors are ignored.
Continued on next page.
No.A0147-16/21
LC87F7CC8A
Continued from preceding page.
Specification
Pin/
Parameter
Symbol
Conditions
Remarks
V
[V]
min
typ
max
1.3
unit
DD
Current
IDDHALT(8)
V
1
HALT mode
DD
4.5 to 5.5
3.0 to 3.6
2.2 to 3.0
4.5 to 5.5
3.0 to 3.6
0.37
consumption
during HALT
mode
=V
=V
2
3
• FmCF=0Hz (Oscillation stop)
• FsX’tal=32.768kHz crystal oscillation
• System clock: RC oscillation
• Frequency variable RC oscillation stopped
• Divider: 1/2
DD
DD
IDDHALT(9)
IDDHALT(10)
IDDHALT(11)
IDDHALT(12)
IDDHALT(13)
0.2
0.13
1
0.75
0.54
3.5
2
(Note 7-1)
mA
HALT mode
• FmCF=0Hz (No oscillation)
• FsX’tal=32.768kHz crystal oscillation
• Internal RC oscillation stopped.
• System clock: 1MHz with frequency variable
RC oscillation
0.55
2.2 to 3.0
0.37
1.5
• Divider :1/2
IDDHALT(14)
IDDHALT(15)
IDDHALT(16)
HALT mode
4.5 to 5.5
3.0 to 3.6
18.5
10
68
38
• FmCF=0Hz (Oscillation stop)
• FsX’tal=32.768kHz crystal oscillation
• System clock: 32.768kHz
• Internal RC oscillation stopped.
• Frequency variable RC oscillation stopped
• Divider: 1/2
2.2 to 3.0
6.5
26
Current
IDDHOLD(1)
IDDHOLD(2)
IDDHOLD(3)
V
1
HOLD mode
4.5 to 5.5
3.0 to 3.6
0.05
0.03
20
12
DD
consumption
during HOLD
mode
• CF1=V or open
DD
µA
(when using external clock)
Date/time clock HOLD mode
2.2 to 3.0
4.5 to 5.5
0.02
16
8
Current
IDDHOLD(4)
IDDHOLD(5)
IDDHOLD(6)
58
consumption
during
• CF1=V or open
DD
(when using external clock)
3.0 to 3.6
2.2 to 3.0
8.5
5
32
20
Date/time clock
HOLD mode
• FmX’tal=32.768kHz crystal oscillation
Note 7-1: The currents through the output transistors and the pull-up MOS transistors are ignored.
F-ROM Write Characteristics at Ta = +10°C to +55°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
Specification
Pin/
Parameter
Symbol
Conditions
Remarks
V
[V]
min
typ max
unit
mA
DD
On-board
IDDFW(1)
V
1
• 128-byte writing
DD
3.0 to 5.5
25
40
writing current
Writing time
• Including erase time current
• 128-byte writing
tFW(1)
• Including data erase time
• Excluding time to fetch 128 byte data
3.0 to 5.5
22.5
45
ms
No.A0147-17/21
LC87F7CC8A
Characteristics of a Sample Main System Clock Oscillation Circuit
The characteristics in the table bellow is based on the following conditions:
(1) Use the standard evaluation board SANYO has provided.
(2) Use the peripheral parts with indicated value externally.
(3) The peripheral parts value is a recommended value of oscillator manufacturer
Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator
Operating
Voltage
Range
[V]
Oscillation
Circuit Constant
Nominal
Vendor
Name
Stabilization Time
Oscillator Name
Remarks
Frequency
C1
C2
Rf1
Rd1
typ
max
[ms]
[pF]
[pF]
[Ω]
[Ω]
[ms]
Internal
C1, C2
12MHz
10MHz
MURATA
MURATA
CSTCE12M0G52-R0
(10)
(10)
Open
470
4.5 to 5.5
0.05
0.15
CSTCE10M0G52-R0
CSTLS10M0G53-B0
CSTCR4M00G53-R0
CSTLS4M00G53-B0
(10)
(15)
(15)
(15)
(10)
(15)
(15)
(15)
Open
Open
Open
Open
1.0k
680
2.8 to 5.5
2.8 to 5.5
2.2 to 5.5
2.2 to 5.5
0.05
0.05
0.05
0.05
0.15
0.15
0.15
0.15
Internal
C1, C2
3.3k
3.3k
Internal
C1, C2
4MHz
MURATA
The oscillation stabilizing time is a period until the oscillation becomes stable after V
minimum operating voltage (See Fig. 4).
becomes higher than
DD
Characteristics of a Sample Subsystem Clock Oscillator Circuit
The characteristics in the table bellow is based on the following conditions:
(1) Use the standard evaluation board SANYO has provided.
(2) Use the peripheral parts with indicated value externally.
(3) The peripheral parts value is a recommended value of oscillator manufacturer
Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator
Operating
Voltage
Range
[V]
Oscillation
Circuit Constant
Nominal
Oscillator
Name
Stabilization Time
Vendor Name
Remarks
Frequency
C3
C4
Rf2
Rd2
typ
[s]
max
[s]
[pF]
[pF]
[Ω]
[Ω]
Applicable
CL value
=12.5pF
32.768kHz
SEIKO EPSON
MC-306
18
18
Open
560k
2.2 to 5.5
1.3
3.0
The oscillation stabilizing time is a period until the oscillation becomes stable after executing the instruction which
starts the sub-clock oscillation or after releasing the HOLD mode (See Fig. 4).
Note : Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to
the oscillation pins as possible with the shortest possible pattern length.
XT1
XT2
CF1
CF2
Rf2
Rf1
Rd2
C4
Rd1
C2
C3
C1
X’tal
CF
Figure 1 Ceramic Oscillator Circuit
Figure 2 Crystal Oscillator Circuit
0.5V
DD
Figure 3 AC Timing Measurement Point
No.A0147-18/21
LC87F7CC8A
V
V
DD
DD
limit
Power
RES
0V
Reset time
Internal RC
Resonator
tmsCF
CF1, CF2
tmsX’tal
XT1, XT2
Operating mode
Reset
Instruction execution mode
Unfixed
Reset Time and Oscillation Stabilization Time
Without HOLD
release
HOLD release
HOLD release signal VALID
Internal RC
Resonator
tmsCF
CF1, CF2
tmsX’tal
XT1, XT2
Operation mode
HOLD
HALT
HOLD Reset Signal and Oscillation Stabilization Time
Figure 4 Oscillation Stabilization Times
No.A0147-19/21
LC87F7CC8A
V
DD
R
C
Note :
RES
Determine the value of C
and R so that the
RES
RES
reset signal is present for a period of 200µs after the
supply voltage goes beyond the lower limit of the IC’s
operating voltage.
RES
RES
Figure 5 Reset Circuit
SIOCLK :
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
DATAIN :
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DO8
DATAOUT :
Data RAM
transmission period
(only SIO0)
tSCK
tSCKH
thDI
tSCKL
SIOCLK :
DATAIN :
tsDI
tdDO
DATAOUT :
Data RAM
transmission period
(only SIO0)
tSCKL
tSCKHA
SIOCLK :
DATAIN :
tsDI
thDI
tdDO
DATAOUT :
Figure 6 Serial I/O Wave form
tPIL
tPIH
Figure 7 Pulse Input Timing Signal Waveform
No.A0147-20/21
LC87F7CC8A
V
DD
SW : ON/OFF (programmable)
RLCD
RLCD
RLCD
RLCD
SW : ON (VLCD=V
)
DD
VLCD
RLCD
RLCD
2/3VLCD
1/2VLCD
RLCD
RLCD
1/3VLCD
RLCD
RLCD
GND
Figure 8 LCD bias resistor
Specifications of any and all SANYO Semiconductor products described or contained herein stipulate the
performance, characteristics, and functions of the described products in the independent state, and are
not guarantees of the performance, characteristics, and functions of the described products as mounted
in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an
independent device, the customer should always evaluate and test devices mounted in the customer's
products or equipment.
SANYO Semiconductor Co., Ltd. strives to supply high-quality high-reliability products. However, any
and all semiconductor products fail with some probability. It is possible that these probabilistic failures
could give rise to accidents or events that could endanger human lives, that could give rise to smoke or
fire, or that could cause damage to other property. When designing equipment, adopt safety measures
so that these kinds of accidents or events cannot occur. Such measures include but are not limited to
protective circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO Semiconductor products (including technical data,services) described
or contained herein are controlled under any of applicable local export control laws and regulations, such
products must not be exported without obtaining the export license from the authorities concerned in
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No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
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otherwise, without the prior written permission of SANYO Semiconductor Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification"
for the SANYO Semiconductor product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO Semiconductor believes information herein is accurate and
reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual
property rights or other rights of third parties.
This catalog provides information as of July, 2006. Specifications and information herein are subject
to change without notice.
No.A0147-21/21
PS
相关型号：
LC87F7J32AU-QIP-E
8-bit LCD Driver Microcontroller with 32K-byte Flash ROM and 1024-byte RAM, PQFP64 14x14 / QIP64E, 300-FTRAY
ONSEMI
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