LC87F7DC8A_10 [SANYO]
FROM 128K byte, RAM 4K byte on-chip 8-bit 1-chip Microcontroller; 从128K字节, RAM 4K字节的片上8位单芯片微控制器型号: | LC87F7DC8A_10 |
厂家: | SANYO SEMICON DEVICE |
描述: | FROM 128K byte, RAM 4K byte on-chip 8-bit 1-chip Microcontroller |
文件: | 总26页 (文件大小:166K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Ordering number : ENA1156A
CMOS IC
FROM 128K byte, RAM 4K byte on-chip
LC87F7DC8A
8-bit 1-chip Microcontroller
Overview
The SANYO LC87F7DC8A is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle
time of 83.3ns, integrates on a single chip a number of hardware features such as 128K-byte flash ROM (onboard
programmable), 4K-byte RAM, an on-chip debugger, a LCD controller/driver, sophisticated 16-bit timer/counter (may
be divided into 8-bit timers), a 16-bit timer/counter (may be divided into 8-bit timers/counters or 8-bit PWMs), four 8-bit
timers with a prescaler, a 16-bit timer with a prescaler (may be divided into 8-bit timers), a base timer serving as a time-
of-day clock, a day and time counter, a synchronous SIO interface (with automatic block transmission/reception
capabilities), an asynchronous/synchronous SIO interface, two UART ports (full duplex), an 12-bit 15-channel AD
converter, two 12-bit PWM channels, a high-speed clock counter, a system clock frequency divider, a small signal
detector, two remote control receive functions, and a 31-source 10-vector interrupt feature.
Features
Flash ROM
• Capable of on-board-programming with wide range, 3.0 to 5.5V, of voltage source.
• Block-erasable in 2-byte units
• 131072 × 8 bits
RAM
• 4096 × 9 bits
Minimum Bus Cycle Time
• 83.3ns (12MHz)
• 125ns (8MHz)
• 250ns (4MHz)
V
DD
V
DD
V
DD
=3.0 to 5.5V
=2.5 to 5.5V
=2.2 to 5.5V
Note: The bus cycle time here refers to the ROM read speed.
* This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by
SANYO Semiconductor Co., Ltd.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer
's products or
equipment.
Ver.0.10
22410HKIM 20100217-S00003 No.A1156-1/26
LC87F7DC8A
Minimum Instruction Cycle Time (tCYC)
• 250ns (12MHz)
• 375ns (8MHz)
• 750ns (4MHz)
V
V
V
=3.0 to 5.5V
=2.5 to 5.5V
=2.2 to 5.5V
DD
DD
DD
Ports
• Normal withstand voltage I/O ports
Ports whose I/O direction can be designated in 1 bit units 29 (P0n, P1n, P70 to P73, P8n, XT2)
• Normal withstand voltage input port
• LCD ports
1 (XT1)
Segment output
54 (S00 to S53)
4 (COM0 to COM3)
3 (V1 to V3)
Common output
Bias terminals for LCD driver
Other functions
Input/output ports
Input ports
54 (P3n, PAn, PBn, PCn, PDn, PEn, PFn,)
7 (PLn)
• Dedicated oscillator ports
• Reset pin
• Power pins
2 (CF1, CF2)
1 (
RES
)
6 (V 1 to V 3, V 1 to V 3)
SS SS DD DD
LCD Controller
1) Seven display modes are available (static, 1/2, 1/3, 1/4 duty × 1/2, 1/3 bias)
2) Segment output and common output can be switched to general-purpose input/output ports
Small Signal Detection (MIC signals etc)
1) Counts pulses with the level which is greater than a preset value
2) 2-bit counter
Timers
• Timer 0: 16-bit timer/counter with two capture registers.
Mode 0: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) × 2 channels
Mode 1: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers)
+ 8-bit counter (with two 8-bit capture registers)
Mode 2: 16-bit timer with an 8-bit programmable prescaler (with two 16-bit capture registers)
Mode 3: 16-bit counter (with two 16-bit capture registers)
• Timer 1: 16-bit timer/counter that supports PWM/toggle outputs
Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs)
+ 8-bit timer/counter with an 8-bit prescaler (with toggle outputs)
Mode 1: 8-bit PWM with an 8-bit prescaler × 2 channels
Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs)
(toggle outputs also possible from the lower-order 8 bits)
Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs)
(The lower-order 8 bits can be used as PWM.)
• Timer 4: 8-bit timer with a 6-bit prescaler
• Timer 5: 8-bit timer with a 6-bit prescaler
• Timer 6: 8-bit timer with a 6-bit prescaler (with toggle output)
• Timer 7: 8-bit timer with a 6-bit prescaler (with toggle output)
• Timer 8: 16-bit timer
Mode 0: 8-bit timer with an 8-bit prescaler × 2 channels
Mode 1: 16-bit timer with an 8-bit prescaler
• Base timer
1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock,
and timer 0 prescaler output.
2) Interrupts programmable in 5 different time schemes
• Day and time counter
1) Using with a base timer, it can be used as 65000 day + minute + second counter.
No.A1156-2/26
LC87F7DC8A
High-speed Clock Counter
1) Can count clocks with a maximum clock rate of 20MHz (at a main clock of 10MHz).
2) Can generate output real-time.
SIO
• SIO0: 8-bit synchronous serial interface
1) LSB first/MSB first mode selectable
2) Built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tCYC)
3) Automatic continuous data transmission (1 to 256 bits specifiable in 1-bit units, suspension and resumption of
data transmission possible in 1-byte units)
• SIO1: 8-bit asynchronous/synchronous serial interface
Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks)
Mode 1: Asynchronous serial I/O (half-duplex, 8-data bits, 1-stop bit, 8 to 2048 tCYC baudrates)
Mode 2: Bus mode 1 (start bit, 8-data bits, 2 to 512 tCYC transfer clocks)
Mode 3: Bus mode 2 (start detect, 8-data bits, stop detect)
UART1
• Full duplex
• 7/8/9 bit data bits selectable
• 1 stop bit (2-bit in continuous data transmission)
• Built-in baudrate generator
UART2
• Full duplex
• 7/8/9 bit data bits selectable
• 1 stop bit (2-bit in continuous data transmission)
• Built-in baudrate generator
AD Converter: 12 bits × 15 channels
PWM: Multi frequency 12-bit PWM × 2 channels
Remote Control Receiver Circuit1
1) Noise rejection function
(Units of noise rejection filter: about 120μs, when selecting a 32.768kHz crystal oscillator as a clock.)
2) Supporting reception formats with a guide-pulse of half-clock/clock/none.
3) Determines a end of reception by detecting a no-signal periods (No carrier).
(Supports same reception format with a different bit length.)
4) X’tal HOLD mode release function
Remote Control Receiver Circuit2
1) Noise rejection function
(Units of noise rejection filter: about 120μs, when selecting a 32.768kHz crystal oscillator as a clock.)
2) Supporting reception formats with a guide-pulse of half-clock/clock/none.
3) Determines a end of reception by detecting a no-signal periods (No carrier).
(Supports same reception format with a different bit length.)
4) X’tal HOLD mode release function
Watchdog Timer
• External RC watchdog timer
• Interrupt and reset signals selectable
Clock Output Function
1) Able to output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 as system clock.
2) Able to output oscillation clock of sub clock.
No.A1156-3/26
LC87F7DC8A
Interrupts
• 31 sources, 10 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of
the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level
takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector
address takes precedence.
No.
1
Vector Address
00003H
Level
X or L
X or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
Interrupt Source
INT0
INT1
2
0000BH
00013H
3
INT2/T0L/INT4/remote control receiver1
INT3/base timer/INT5/remote control receiver2
T0H/INT6
4
0001BH
00023H
5
6
0002BH
00033H
T1L/T1H/INT7
7
SIO0/UART1 receive/UART2 receive/T8L/T8H
SIO1/UART1 transmit/UART2 transmit
ADC/MIC/T6/T7/PWM4/PWM5
Port 0/T4/T5
8
0003BH
00043H
9
10
0004BH
• Priority levels X > H > L
• Of interrupts of the same level, the one with the smallest vector address takes precedence.
• IFLG (List of interrupt source flag function)
1) Shows a list of interrupt source flags that caused a branching to a particular vector address
(shown in the diagram above).
Subroutine Stack Levels: 2048 levels (The stack is allocated in RAM.)
High-speed Multiplication/Division Instructions
• 16 bits × 8 bits
• 24 bits × 16 bits
• 16 bits ÷ 8 bits
• 24 bits ÷ 16 bits
(5 tCYC execution time)
(12 tCYC execution time)
(8 tCYC execution time)
(12 tCYC execution time)
Oscillation Circuits
• RC oscillation circuit (internal):
• CF oscillation circuit:
• Crystal oscillation circuit:
For system clock
For system clock, with internal Rf
For low-speed system clock, with internal Rf
• Frequency variable RC oscillation circuit (internal): For system clock
1) Adjustable in 4% (typ.) step from a selected center frequency.
2) Measures oscillation clock using a input signal from XT1 as a reference.
System Clock Divider Function
• Can run on low current.
• The minimum instruction cycle selectable from 300ns, 600ns, 1.2μs, 2.4μs, 4.8μs, 9.6μs, 19.2μs, 38.4μs,
and 76.8μs (at a main clock rate of 10MHz).
Standby Function
• HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
(Some parts of the serial transfer function stops operation.)
1) Oscillation is not halted automatically.
2) Canceled by a system reset or occurrence of an interrupt
Continued on next page.
No.A1156-4/26
LC87F7DC8A
Continued from preceding page.
• HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
1) The CF, RC, X’tal, and frequency variable RC oscillators automatically stop operation.
2) There are three ways of resetting the HOLD mode.
(1) Setting the reset pin to the low level
(2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level
(3) Having an interrupt source established at port 0
• X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer
and the remote control receiver circuit.
1) The CF, RC, and frequency variable RC oscillators automatically stop operation.
2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained.
3) There are five ways of resetting the X'tal HOLD mode.
(1) Setting the reset pin to the low level
(2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level
(3) Having an interrupt source established at port 0
(4) Having an interrupt source established in the base timer circuit
(5) Having an interrupt source established in the remote control receiver circuit
On-chip Debugger
• Supports software debugging with the IC mounted on the target board.
Package Form
• QIP100E(14×20): Lead-free type
• TQFP100(14×14): Lead-free type/Halogen-free type
Development Tools
• On-chip debugger: TCB87-TypeB + LC87F7DC8A
Flash ROM Programming Boards
Package
Programming boards
QIP100E(14×20)
TQFP100(14×14)
W87FQ100
W87FSQ100
Flash ROM Programmer
Maker
Model
Supported version
(Note 2)
Device
AF9708
AF9709/AF9709B/AF9709C
(Including product of Ando
Electric Co., Ltd)
Single
Gang
LC87F7DC8A
Flash Support Group, Inc.
(FSG)
AF9723/AF9723B(Main body)
(Including product of Ando
Electric Co., Ltd)
(Note 2)
(Note 2)
LC87F7DC8A
AF9833(Unit)
(Including product of Ando
Electric Co., Ltd)
Flash Support Group, Inc.
AF9101/AF9103(Main body)
(FSG)
(FSG)
+
Onboard
(Note 2)
LC87F7DC8A
LC87F7DC8A
Single/Gang
SIB87(interface driver)
(SANYO)
SANYO (Note 1)
SKK/SKK Type B
Application Version
After 1.04
Single/Gang
(SANYO FWS)
SANYO
Chip Data Version
After 2.16
Onboard
SKK-DBG Type B
(SANYO FWS)
Single/Gang
Note 1: With the FSG onboard programmer (AF9101/AF9103) and the serial interface driver provided by SANYO,
PC-less standalone onboard programming is possible
Note 2: Depending on programming conditions, it is necessary to use a dedicated programming device and a program.
Please contact SANYO or FSG if you have any questions or difficulties regarding this matter.
No.A1156-5/26
LC87F7DC8A
Package Dimensions
unit : mm (typ)
3151A
23.2
20.0
80
51
81
50
31
100
1
30
0.65
0.3
0.15
(0.58)
SANYO : QIP100E(14X20)
Package Dimensions
unit : mm (typ)
3274
16.0
14.0
75
51
50
76
100
26
1
25
0.125
0.5
0.2
(1.0)
SANYO : TQFP100(14X14)
No.A1156-6/26
LC87F7DC8A
Pin Assignments
V2/PL5/AN13/DBGP1
V1/PL4/AN12/DBGP0
COM0/PL0
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
S20/PC4
S19/PC3
S18/PC2
S17/PC1
S16/PC0
S15/PB7
S14/PB6
S13/PB5
S12/PB4
S11/PB3
S10/PB2
S9/PB1
S8/PB0
S7/PA7
S6/PA6
S5/PA5
S4/PA4
S3/PA3
S2/PA2
S1/PA1
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
COM1/PL1
COM2/PL2
COM3/PL3
P30/INT4/T1IN/INT6/T0LCP1/PWM4/S48
P31/INT4/T1IN/PWM5/S49
V
V
3
3
SS
DD
LC87F7DC8A
P32/INT4/T1IN/UTX1/S50
P33/INT4/T1IN/URX1/S51
P34/INT5/T1IN/INT7/T0HCP1/UTX2/S52
P35/INT5/T1IN/URX2/S53
P00/DGBP0
P01/DGBP1
P02/DGBP2
P03/INT6
P04/INT7
P05/CKO
Top view
SANYO: QIP100E(14×20) “Lead-free Type”
No.A1156-7/26
LC87F7DC8A
S47/PF7
V3/PL6/AN14/DBGP2
V2/PL5/AN13/DBGP1
V1/PL4/AN12/DBGP0
COM0/PL0
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
S23/PC7
S22/PC6
S21/PC5
S20/PC4
S19/PC3
S18/PC2
S17/PC1
S16/PC0
S15/PB7
S14/PB6
S13/PB5
S12/PB4
S11/PB3
S10/PB2
S9/PB1
S8/PB0
S7/PA7
S6/PA6
S5/PA5
S4/PA4
S3/PA3
S2/PA2
S1/PA1
COM1/PL1
COM2/PL2
COM3/PL3
P30/INT4/T1IN/INT6/T0LCP1/PWM4/S48
P31/INT4/T1IN/PWM5/S49
V
V
3
3
SS
DD
LC87F7DC8A
P32/INT4/T1IN/UTX1/S50
P33/INT4/T1IN/URX1/S51
P34/INT5/T1IN/INT7/T0HCP1/S52
P35/INT5/T1IN/S52
P00/DGBP0
P01/DGBP1
P02/T8LO/DGBP2
P03/T8HO
P04
P05/CKO
P06/T6O
P07/T7O
S0/PA0
P73/INT3/T0IN/RMIN
P10/SO0
Top view
SANYO: TQFP100(14×14) “Lead-free type/Halogen-free type”
No.A1156-8/26
LC87F7DC8A
System Block Diagram
Interrupt control
IR
PLA
Standby control
CF
Flash ROM
RC
VMRC
PC
X’tal
ACC
B register
C register
ALU
SIO0
SIO1
Bus interface
Port 0
Timer 0
(High speed clock counter)
PSW
RAR
Port 1
Timer 1
Base timer
Port 3
Port 7
RAM
LCD Controller
Port 8
INT0 to 7
Noise Rejection Filter
ADC
Stack pointer
Watchdog timer
On-chip debugger
Small signal
detector
Timer 4
Timer 5
UART1
PWM4/5
Timer 6
UART2
Timer 7
Timer 8
Remote control
receiver circuit 1
Remote control
receiver circuit 2
Day and time
counter
No.A1156-9/26
LC87F7DC8A
Pin Description
Pin Name
I/O
Description
Option
No
V
V
V
V
V
V
1
-
- power supply pin
+ power supply pin
SS
2
3
1
SS
SS
-
No
DD
DD
DD
2
3
Port 0
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 1-bit units
P00 to P07
• Pull-up resistors can be turned on and off in 1-bit units.
• Input for HOLD release
• Input for port 0 interrupt
• Shared pins
P03: INT6 input
P04: INT7 input
P05: Clock output (system clock/can selected from sub clock)
P06: Timer 6 toggle output
P07: Timer 7 toggle output
On chip debugger pins: DBGP0 to DBGP2(P00 to P02)
Port 1
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 1-bit units
• Pull-up resistors can be turned on and off in 1-bit units.
• Shared pins
P10 to P17
P10: SIO0 data output
P11: SIO0 data input/bus I/O
P12: SIO0 clock I/O
P13: SIO1 data output
P14: SIO1 data input/bus I/O
P15: SIO1 clock I/O
P16: Timer 1PWML output
P17: Timer 1PWMH output/beeper output
Port 3
I/O
• 6-bit I/O port
Yes
• Segment output for LCD
P30 to P35
• I/O specifiable in 1-bit units
• Pull-up resistors can be turned on and off in 1-bit units.
• Shared pins
P30 to P33: INT4 input/HOLD release input/timer 1 event input/timer 0L capture input/
timer 0H capture input
P34 to P35: INT5 input/HOLD release input/timer 1 event input/timer 0L capture input/
timer 0H capture input
P30: PWM4 output/INT6 input/timer 0L capture 1 input
P31: PWM5 output
P32: UART1 transmit
P33: UART1 receive
P34: UART2 transmit/INT7 input/timer 0H capture 1 input
P35: UART2 receive
Interrupt acknowledge type
Rising &
Rising
Falling
H level
L level
Falling
enable
enable
enable
enable
INT4
INT5
INT6
INT7
enable
enable
enable
enable
enable
enable
enable
enable
disable
disable
disable
disable
disable
disable
disable
disable
Continued on next page.
No.A1156-10/26
LC87F7DC8A
Continued from preceding page.
Pin Name
Port 7
I/O
I/O
Description
Option
No
• 4-bit I/O port
• I/O specifiable in 1-bit units
P70 to P73
• Pull-up resistors can be turned on and off in 1-bit units.
• Shared pins
P70: INT0 input/HOLD release input/timer 0L capture input/watchdog timer output
P71: INT1 input/HOLD release input/timer 0H capture input
P72: INT2 input/HOLD release input/timer 0 event input/timer 0L capture input/
high speed clock counter input
P73: INT3 input (with noise filter)/timer 0 event input/timer 0H capture input/
remote control receiver input
AD converter input ports: AN8 (P70), AN9 (P71)
Interrupt acknowledge type
Rising &
Rising
Falling
H level
L level
Falling
disable
disable
enable
enable
INT0
INT1
INT2
INT3
enable
enable
enable
enable
enable
enable
enable
enable
enable
enable
disable
disable
enable
enable
disable
disable
Port 8
I/O
• 8-bit I/O port
No
• I/O specifiable in 1-bit units
• Shared pins
P80 to P87
AD converter input ports: AN0 to AN7
Small signal detector input port: MICIN (P87)
• Segment output for LCD
S0/PA0 to
S7/PA7
I/O
I/O
I/O
I/O
I/O
I/O
No
No
No
No
No
No
• Can be used as general-purpose I/O port (PA)
• Segment output for LCD
S8/PB0 to
S15/PB7
• Can be used as general-purpose I/O port (PB)
• Segment output for LCD
S16/PC0 to
S23/PC7
S24/PD0 to
S31/PD7
S32/PE0 to
S39/PE7
• Can be used as general-purpose I/O port (PC)
• Segment output for LCD
• Can be used as general-purpose I/O port (PD)
• Segment output for LCD
• Can be used as general-purpose I/O port (PE)
• Segment output for LCD
S40/PF0 to
S47/PF7
• Can be used as general-purpose I/O port (PF)
PF6: INT6 input
PF7: INT7 input
COM0/PL0 to
COM3/PL3
V1/PL4 to
V3/PL6
I/O
I/O
• Common output for LCD
No
No
• Can be used as general-purpose input port (PL)
• LCD output bias power supply
• Can be used as general-purpose input port (PL)
• Shared pins
AD converter input ports: AN12 (V1) to AN14 (V3)
On-chip debugger pins: DBGP0 (V1) to DBGP2 (V3)
Reset pin
RES
XT1
Input
Input
No
No
• 32.768kHz crystal oscillator input pin
• Shared pins
General-purpose input port
AD converter input port: AN10
Must be connected to V 1 if not to be used.
DD
XT2
I/O
• 32.768kHz crystal oscillator output pin
• Shared pins
No
General-purpose I/O port
AD converter input port: AN11
Must be set for oscillation and kept open if not to be used.
Ceramic resonator input pin
CF1
CF2
Input
No
No
Output
Ceramic resonator output pin
No.A1156-11/26
LC87F7DC8A
Port Output Types
The table below lists the types of port outputs and the presence/absence of a pull-up resistor.
Data can be read into any input port even if it is in the output mode.
Option Selected
Port Name
Option Type
Output Type
Pull-up Resistor
Programmable
in Units of
each bit
P00 to P07
1
2
CMOS
Nch-open drain
CMOS
Programmable
Programmable
Programmable
Programmable
Programmable
Programmable
Programmable
No
P10 to P17
P30 to P35
each bit
each bit
1
2
Nch-open drain
CMOS
1
2
Nch-open drain
Nch-open drain
CMOS
P70
-
-
-
-
-
No
No
No
No
No
P71 to P73
P80 to P87
S0/PA0 to S47/PF7
Nch-open drain
CMOS
Programmable
No
COM0/PL0 to
COM3/PL3
Input only
V1/PL4 to V3/PL6
-
-
-
No
No
No
Input only
Input only
No
No
No
XT1
XT2
Output for 32.768kHz crystal oscillator
(Nch-open drain when in general-purpose
output mode)
User Option List
Mask Version
*1
Option Selected in
Option Name
Option Type
Flash Version
Units of
Specified item
CMOS
P00 to P07
{
{
{
{
{
{
{
each bit
each bit
each bit
-
Nch-open drain
CMOS
Port output form
P10 to P17
P30 to P35
-
Nch-open drain
CMOS
Nch-open drain
00000H
Program start
address
×
*2
1FF00H
*1: Mask option selection - No change possible after the mask is completed.
*2: Program start address of the mask version is 00000h.
LSI
V
1
DD
Power
supply
For backup *2
V
V
2
3
DD
DD
V
1
V
2
V
3
SS
SS
SS
*1 Connect the IC as shown below to minimize the noise input to the V 1 pin.
DD
Be sure to electrically short the V 1, V 2, and V 3 pins.
SS SS SS
*2 The internal memory is sustained by V 1. If none of V 2 and V 3 are backed up, the high level output at the
DD DD DD
ports are unstable in the HOLD backup mode, allowing through current to flow into the input buffer and thus
shortening the backup time.
Make sure that the port outputs are held at the low level in the HOLD backup mode.
No.A1156-12/26
LC87F7DC8A
Absolute Maximum Ratings at Ta = 25°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
Specification
typ max
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
-0.3
unit
DD
Maximum supply
voltage
V
max
V
1, V 2, V
3
V
V
1=V 2=V
DD
3
3
DD
DD
DD
DD
DD
DD
DD
+6.5
supply voltage for
LCD
VLCD
V1/PL4, V2/PL5,
V3/PL6
1=V 2=V
DD
DD
-0.3
-0.3
V
DD
Input voltage
V (1)
I
Port L
V
V
V
+0.3
DD
XT1, CF1,
RES
Input/output
voltage
V
(1)
Ports 0, 1, 3, 7, 8
Ports A, B, C
Ports D, E, F
XT2
IO
-0.3
-10
+0.3
DD
Peak output
current
IOPH(1)
IOPH(2)
Ports 0, 1, 32 to 35
• CMOS output selected
• Current at each pin
• CMOS output selected
• Current at each pin
Current at each pin
Ports 30, 31
-20
-5
IOPH(3)
IOPH(4)
Ports 71 to 73
Ports A, B, C
Current at each pin
-5
Ports D, E, F
Mean output
current
IOMH(1)
IOMH(2)
Ports 0, 1, 32 to 35
• CMOS output selected
• Current at each pin
• CMOS output selected
• Current at each pin
Current at each pin
-7.5
(Note 1-1)
Ports 30, 31
-15
-3
IOMH(3)
IOMH(4)
Ports 71 to 73
Ports A, B, C
Current at each pin
-3
Ports D, E, F
Total output
current
ΣIOAH(1)
ΣIOAH(2)
ΣIOAH(3)
ΣIOAH(4)
ΣIOAH(5)
ΣIOAH(6)
ΣIOAH(7)
Ports 0, 1, 32 to 35
Total of all pins
Total of all pins
Total of all pins
Total of all pins
Total of all pins
Total of all pins
Total of all pins
-25
-25
-45
-5
Ports 30, 31
Ports 0, 1, 3
Ports 71 to 73
Ports A, B, C
Ports D, E, F
-25
-25
Ports A, B, C
-45
Ports D, E, F
mA
Peak output
current
IOPL(1)
IOPL(2)
IOPL(3)
Ports 0, 1, 32 to 35
Current at each pin
Current at each pin
Current at each pin
20
30
Ports 30, 31
Ports 7, 8
10
10
XT2
IOPL(4)
Ports A, B, C
Ports D, E, F
Ports 0, 1, 32 to 35
Current at each pin
Mean output
current
IOML(1)
IOML(2)
IOML(3)
Current at each pin
Current at each pin
Current at each pin
15
20
Ports 30, 31
(Note 1-1)
Ports 7, 8
7.5
7.5
XT2
IOML(4)
Ports A, B, C
Ports D, E, F
Ports 0, 1, 32 to 35
Current at each pin
Total output
current
ΣIOAL(1)
ΣIOAL(2)
ΣIOAL(3)
ΣIOAL(4)
Total of all pins
Total of all pins
Total of all pins
Total of all pins
45
45
80
Ports 30, 31
Ports 0, 1, 3
Ports 7, 8
XT2
20
ΣIOAL(5)
ΣIOAL(6)
ΣIOAL(7)
Ports A, B, C
Total of all pins
Total of all pins
Total of all pins
45
45
Ports D, E, F
Ports A, B, C
Ports D, E, F
80
Maximum power
dissipation
Pd max
QIP100E(14×20)
Ta=-40 to +85°C
Ta=-40 to +85°C
mW
TQFP100(14×14)
Note 1-1: The mean output current is a mean value measured over 100ms.
Continued on next page.
No.A1156-13/26
LC87F7DC8A
Continued from preceding page.
Specification
typ max
Parameter
Symbol
Topr
Pin/Remarks
Conditions
V
[V]
min
-40
unit
DD
Operating ambient
temperature
+85
°C
Storage ambient
temperature
Tstg
-55
+125
Allowable Operating Range at Ta = -40°C to +85°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
Specification
Parameter
Symbol
Pin/Remarks
1=V 2=V 3
DD
Conditions
V
[V]
min
typ max
unit
DD
Operating
V
V
V
(1)
V
0.237μs ≤ tCYC ≤ 200μs
0.356μs ≤ tCYC ≤ 200μs
0.712μs ≤ tCYC ≤ 200μs
3.0
2.5
2.2
5.5
5.5
5.5
DD
DD
DD
supply voltage
(Note 2-1)
(2)
DD
(3)
DD
Memory
VHD
V
1
RAM and register contents
sustained in HOLD mode.
DD
sustaining
supply voltage
High level input
voltage
2.0
5.5
V
(1)
Ports 0, 3, 8
Output disabled
IH
0.3V
DD
Ports A, B, C, D, E, F
Port L
2.2 to 5.5
2.2 to 5.5
V
DD
+0.7
V
(2)
Port 1
• Output disabled
IH
Ports 71 to 73
P70 port input/
interrupt side
P71 interrupt side
• When INT1VTSL=0 (P71 only)
0.3V
DD
V
DD
+0.7
V
V
V
(3)
(4)
(5)
(6)
• Output disabled
• When INT1VTSL=1
Output disabled
IH
IH
IH
IH
2.2 to 5.5
2.2 to 5.5
0.85V
V
V
DD
DD
DD
P87 small signal
input side
0.75V
0.9V
DD
V
P70 watchdog timer
side
Output disabled
Output disabled
2.2 to 5.5
2.2 to 5.5
4.0 to 5.5
2.2 to 4.0
4.0 to 5.5
V
V
DD
DD
V
V
XT1,XT2,CF1,
Ports 0, 3, 8
RES
0.75V
DD
SS
SS
SS
DD
Low level input
voltage
(1)
0.15V
IL
DD
+0.4
V
V
V
Ports A, B, C, D, E, F
Port L
0.2V
DD
V
(2)
Port 1
• Output disabled
0.1V
IL
DD
Ports 71 to 73
P70 port input/
interrupt side
P71 interrupt side
• When INT1VTSL=0 (P71 only)
+0.4
2.2 to 4.0
2.2 to 5.5
2.2 to 5.5
2.2 to 5.5
V
V
V
0.2V
DD
SS
SS
SS
V
V
V
V
(3)
(4)
(5)
(6)
• Output disabled
• When INT1VTSL=1
Output disabled
IL
IL
IL
IL
0.45V
DD
DD
P87 small signal
input side
0.25V
0.8V
P70 watchdog timer
side
Output disabled
DD
-1.0
V
V
SS
XT1,XT2,CF1,
RES
2.2 to 5.5
3.0 to 5.5
2.5 to 5.5
2.2 to 5.5
3.0 to 5.5
2.5 to 5.5
0.25V
DD
SS
Instruction cycle
time
tCYC
0.237
0.356
0.712
0.1
200
μs
200
200
12
(Note 2-2)
External system
clock frequency
FEXCF(1)
CF1
• CF2 pin open
• System clock frequency
division ratio=1/1
0.1
8
• External system clock
duty=50±5%
2.2 to 5.5
0.1
4
MHz
• CF2 pin open
3.0 to 5.5
2.5 to 5.5
2.2 to 5.5
0.2
0.2
0.2
24.4
16
8
• System clock frequency
division ratio=1/2
Note 2-1: V
DD
must be held greater than or equal to 3.0V in the flash ROM onboard programming mode.
Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at
a division ratio of 1/2.
Continued on next page.
No.A1156-14/26
LC87F7DC8A
Continued from preceding page.
Specification
typ max
Parameter
Symbol
Pin/Remarks
CF1, CF2
Conditions
V
[V]
min
unit
DD
Oscillation
FmCF(1)
• 12MHz ceramic oscillation
• See Fig. 1.
3.0 to 5.5
2.5 to 5.5
12
frequency
range
FmCF(2)
FmCF(3)
CF1, CF2
CF1, CF2
• 8MHz ceramic oscillation
• See Fig. 1.
8
(Note 2-3)
• 4MHz ceramic oscillation
• See Fig. 1.
2.2 to 5.5
2.2 to 5.5
4
FmRC
Internal RC oscillation
0.3
1.0
2.0
FmVMRC(1)
• Frequency variable RC
source oscillation
• When
MHz
2.2 to 5.5
10
VMRAJ2 to 0=4,
VMFAJ2 to 0=0,
VMSL4M=0
FmVMRC(2)
• Frequency variable RC
source oscillation
• When
2.2 to 5.5
4
VMRAJ2 to 0=4,
VMFAJ2 to 0=0,
VMSL4M=1
FsX’tal
XT1, XT2
• 32.768kHz crystal oscillation
• See Fig. 2.
2.2 to 5.5
2.2 to 5.5
32.768
10
kHz
Frequency
variable RC
oscillation
usable range
Frequency
variable RC
oscillation
adjustment
range
OpVMRC(1)
OpVMRC(2)
When VMSL4M=0
8
12
When VMSL4M=1
MHz
2.2 to 5.5
2.2 to 5.5
2.2 to 5.5
3.5
4
24
4
4.5
VmADJ(1)
VmADJ(2)
Each step of VMRAJn
(Wide range)
8
1
64
8
%
Each step of VMFAJn
(Small range)
Note 2-3: See Tables 1 and 2 for the oscillation constants.
Electrical Characteristics at Ta = -40°C to +85°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
Specification
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
typ max
unit
DD
High level input
current
I
(1)
Ports 0, 1, 3, 7, 8
Ports A, B, C
Ports D, E, F
Port L
• Output disabled
• Pull-up resistor off
• V =V (Including output Tr's
IH
2.2 to 5.5
1
IN DD
off leakage current)
I
I
(2)
(3)
V
=V
RES
2.2 to 5.5
2.2 to 5.5
1
1
IH
IN DD
XT1, XT2
• For input port specification
IH
• V =V
IN DD
I
I
(4)
(5)
CF1
V
=V
IN DD
2.2 to 5.5
4.5 to 5.5
2.2 to 4.5
15
15
10
IH
P87 small signal
input side
V =VBIS+0.5V
IN
4.2
8.5
IH
(VBIS: Bias voltage)
1.5
5.5
µA
Low level input
current
I
(1)
Ports 0, 1, 3, 7, 8
Ports A, B, C
Ports D, E, F
Port L
• Output disabled
IL
• Pull-up resistor off
2.2 to 5.5
-1
• V =V
(Including output Tr's
off leakage current)
IN SS
I
I
(2)
(3)
V
=V
RES
2.2 to 5.5
2.2 to 5.5
-1
-1
IL
IN SS
XT1, XT2
• For input port specification
IL
• V =V
IN SS
I
I
(4)
(5)
CF1
V
=V
IN SS
2.2 to 5.5
4.5 to 5.5
2.2 to 4.5
-15
-15
-10
IL
P87 small signal
input side
V
=VBIS-0.5V
IN
-8.5
-5.5
-4.2
-1.5
IL
(VBIS : Bias voltage)
Continued on next page.
No.A1156-15/26
LC87F7DC8A
Continued from preceding page.
Specification
typ max
Parameter
Symbol
Pin/Remarks
Ports 0, 1,
Conditions
=-1mA
OH
V
[V]
min
unit
DD
High level output
voltage
V
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
I
I
I
I
I
I
I
I
I
I
I
I
I
I
4.5 to 5.5
3.0 to 5.5
2.2 to 5.5
4.5 to 5.5
3.0 to 5.5
2.2 to 5.5
3.0 to 5.5
2.2 to 5.5
4.5 to 5.5
3.0 to 5.5
2.2 to 5.5
4.5 to 5.5
3.0 to 5.5
V
-1
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
DD
32 to 35
V
V
V
V
V
V
V
V
V
V
V
V
V
=-0.4mA
=-0.2mA
=-10mA
=-1.6mA
=-1mA
V
V
V
V
V
V
V
-0.4
-0.4
-1.5
-0.4
-0.4
-0.4
-0.4
-1
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
DD
DD
DD
DD
DD
DD
DD
Ports 30, 31
Ports 71 to 73
=-0.4mA
=-0.2mA
=-1mA
Ports A, B, C
Ports D, E, F
V
DD
=-0.4mA
=-0.2mA
V
-0.4
DD
DD
V
-0.4
Low level output
voltage
(1)
(2)
(3)
Ports 0, 1,
=10mA
=1.6mA
=1mA
1.5
0.4
OL
OL
OL
OL
OL
OL
32 to 35
Ports 30,31
(PWM function
output mode)
Ports 30, 31
(Port function
output mode)
2.2 to 5.5
0.4
V
V
V
V
V
V
V
V
(4)
(5)
(6)
(7)
(8)
(9)
(10)
I
I
I
I
I
I
I
=30mA
=5mA
4.5 to 5.5
3.0 to 5.5
2.2 to 5.5
3.0 to 5.5
2.2 to 5.5
3.0 to 5.5
2.2 to 5.5
1.5
0.4
0.4
0.4
0.4
0.4
0.4
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
=2.5mA
=1.6mA
=1mA
Ports 7, 8
XT2
Ports A, B, C
Ports D, E, F
=1.6mA
=1mA
LCD output voltage
regulation
VODLS
S0 to S53
• I =0mA
O
• VLCD, 2/3VLCD,1/3VLCD
2.2 to 5.5
2.2 to 5.5
0
0
±0.2
±0.2
level output
• See Fig. 8.
VODLC
COM0 to COM3
• I =0mA
O
• VLCD, 2/3VLCD,1/2VLCD,
1/3VLCD level output
• See Fig. 8.
LCD bias resistor
RLCD(1)
RLCD(2)
Resistance per
one bias resister
Resistance per
one bias resister
1/2 mode
See Fig. 8.
2.2 to 5.5
2.2 to 5.5
60
See Fig. 8.
30
kΩ
Resistance of
Rpu(1)
Rpu(2)
Ports 0, 1, 3, 7
Ports A, B, C
Ports D, E, F
Ports 1, 7
V
=0.9V
4.5 to 5.5
2.2 to 5.5
15
18
35
50
80
OH
DD
pull-up MOS Tr.
150
Hysterisis voltage
Pin capacitance
Input sensitivity
VHYS(1)
VHYS(2)
CP
2.2 to 5.5
2.2 to 5.5
0.1V
0.1V
DD
DD
RES
V
P87 small signal
input side
All pins
• For pins other than that
under test: V =V
IN SS
2.2 to 5.5
2.2 to 5.5
10
pF
• f=1MHz
• Ta=25°C
Vsen
P87 small signal
input side
0.12V
Vp-p
DD
No.A1156-16/26
LC87F7DC8A
Serial I/O Characteristics at Ta = -40°C to +85°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
1. SIO0 Serial I/O Characteristics (Note 4-1-1)
Specification
Parameter
Frequency
Symbol
tSCK(1)
Pin/Remarks
SCK0(P12)
Conditions
See Fig. 6.
V
[V]
min
typ
max
unit
DD
2
1
1
Low level
tSCKL(1)
tSCKH(1)
tSCKHA(1)
pulse width
High level
pulse width
2.2 to 5.5
tCYC
• Continuous data
transmission/reception mode
• See Fig. 6.
4
• (Note 4-1-2)
Frequency
tSCK(2)
SCK0(P12)
• CMOS output selected
• See Fig. 6.
4/3
Low level
tSCKL(2)
tSCKH(2)
tSCKHA(2)
1/2
1/2
pulse width
High level
pulse width
tSCK
tCYC
2.2 to 5.5
• Continuous data
transmission/reception mode
• CMOS output selected
• See Fig. 6.
tSCKH(2)
+(10/3)
tCYC
tSCKH(2)
+2tCYC
Data setup time
Data hold time
tsDI(1)
thDI(1)
tdD0(1)
tdD0(2)
tdD0(3)
SB0(P11),
SI0(P11)
• Must be specified with
respect to rising edge of
SIOCLK.
2.2 to 5.5
2.2 to 5.5
2.2 to 5.5
2.2 to 5.5
0.03
0.03
• See Fig. 6.
Output delay
time
SO0(P10),
SB0(P11)
• Continuous data
(1/3)tCYC
+0.05
transmission/reception mode
• (Note 4-1-3)
μs
• Synchronous 8-bit mode
• (Note 4-1-3)
1tCYC
+0.05
(Note 4-1-3)
(1/3)tCYC
+0.05
2.2 to 5.5
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock
is "H" to the first negative edge of the serial clock must be longer than tSCKHA.
Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning
of output state change in open drain output mode. See Fig. 6.
No.A1156-17/26
LC87F7DC8A
2. SIO1 Serial I/O Characteristics (Note 4-2-1)
Specification
Parameter
Frequency
Symbol
tSCK(3)
Pin/Remarks
SCK1(P15)
Conditions
See Fig. 6.
V
[V]
min
typ
max
unit
DD
2
1
1
2
Low level
tSCKL(3)
tSCKH(3)
tSCK(4)
tSCKL(4)
tSCKH(4)
tsDI(2)
2.2 to 5.5
pulse width
High level
pulse width
Frequency
tCYC
SCK1(P15)
• CMOS output selected
• See Fig. 6.
Low level
pulse width
2.2 to 5.5
1/2
1/2
tSCK
High level
pulse width
Data setup time
SB1(P14),
SI1(P14)
• Must be specified with
respect to rising edge of
SIOCLK.
2.2 to 5.5
2.2 to 5.5
0.03
0.03
• See Fig. 6.
Data hold time
thDI(2)
tdD0(4)
Output delay time
SO1(P13),
SB1(P14)
• Must be specified with
respect to falling edge of
SIOCLK.
μs
• Must be specified as the
time to the beginning of output
state change in open drain
output mode.
(1/3)tCYC
+0.05
2.2 to 5.5
• See Fig. 6.
Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.
Pulse Input Conditions at Ta = -40°C to +85°C, V 1 = V 2 = V 3 = 0V
SS SS SS
Specification
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
typ
max
unit
DD
High/low level
pulse width
tPIH(1)
INT0(P70),
• Interrupt source flag can be set.
• Event inputs for timer 0 or 1
are enabled.
tPIL(1)
INT1(P71),
INT2(P72),
INT4(P30 to P33),
INT5(P34 to P35),
INT6(P30),
2.2 to 5.5
1
INT7(P34)
tPIH(2)
tPIL(2)
INT3(P73) when
noise filter time
constant is 1/1
INT3(P73) when
noise filter time
constant is 1/32
INT3(P73) when
noise filter time
constant is 1/128
MICIN(P87)
• Interrupt source flag can be set.
• Event inputs for timer 0 are
enabled.
2.2 to 5.5
2.2 to 5.5
2
tCYC
tPIH(3)
tPIL(3)
• Interrupt source flag can be set.
• Event inputs for timer 0 are
enabled.
64
tPIH(4)
tPIL(4)
• Interrupt source flag can be set.
• Event inputs for timer 0 are
enabled.
2.2 to 5.5
2.2 to 5.5
256
1
tPIH(5)
tPIL(5)
tPIH(6)
tPIL(6)
tPIL(7)
Condition that signal is accepted to
small signal detection counter.
Condition that signal is accepted to
remote control receiver circuit.
Resetting is enabled.
RMIN(P73)
RES
RMCK
2.2 to 5.5
2.2 to 5.5
4
(Note5-1)
200
μs
Note 5-1: RMCK is an unit for the base clock (40tCYC/50tCYC/Sub-Clock) of remote control receiver circuit.
No.A1156-18/26
LC87F7DC8A
AD Converter Characteristics at V 1 = V 2 = V 3 =0V
SS SS SS
<12bits AD Converter Mode at Ta =-xx to +xx°C> To be determined after evaluation
Specification
typ max
12
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
unit
bit
DD
Resolution
N
AN0(P80) to
AN7(P87),
AN8(P70),
AN9(P71),
AN10(XT1),
AN11(XT2)
Absolute
accuracy
ET
(Note 6-1)
(Note 6-1)
LSB
Ta =-10 to +50°C
• See Conversion time calculation
formulas.
Conversion
time
tCAD
(Note 6-2)
Ta =-10 to +50°C
• See Conversion time calculation
formulas.
μs
(Note 6-2)
Analog input
voltage range
Analog port
input current
VAIN
V
SS
V
V
DD
IAINH
IAINL
VAIN=V
DD
1
μA
VAIN=V
SS
-1
<8bits AD Converter Mode at Ta =-30 to +70°C>
Specification
typ max
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
unit
bit
DD
Resolution
N
AN0(P80) to
3.0 to 5.5
3.0 to 5.5
8
AN7(P87),
AN8(P70),
AN9(P71),
AN10(XT1),
AN11(XT2)
Absolute
accuracy
Conversion
time
ET
(Note 6-1)
1.5
LSB
TCAD
• See Conversion time calculation
formulas.
4.0 to 5.5
3.0 to 5.5
μs
(Note 6-2)
Analog input
voltage range
Analog port
input current
VAIN
3.0 to 5.5
V
V
V
SS
DD
IAINH
IAINL
VAIN=V
DD
3.0 to 5.5
3.0 to 5.5
1
μA
VAIN=V
SS
-1
<Conversion time calculation formulas>
12bits AD Converter Mode: TCAD(Conversion time)=((52/(division ratio)) + 2) × (1/3) ×tCYC
8bits AD Converter Mode: TCAD(Conversion time)=((32/(division ratio)) + 2) × (1/3) ×tCYC
<Recommended Operating Conditions>
AD conversion time
External
oscillation
Operating supply
voltage range
AD division
ratio
System division ratio
(SYSDIV)
Cycle time
tCYC [ns]
(tCAD) [μs]
FmCF [MHz]
V
[V]
(ADDIV)
12bit AD
8bit AD
21.5
DD
4.0 to 5.5
3.0 to 5.5
1/1
1/1
250
250
1/8
TBD
TBD
12
1/16
42.8
Note 6-1: The quantization error (±1/2LSB) must be excluded from the absolute accuracy. The absolute accuracy must
be measured in the microcontroller's state in which no I/O operations occur at the pins adjacent to the analog
input channel.
Note 6-2: The conversion time refers to the period from the time an instruction for starting a conversion process till the
time the conversion results register(s) are loaded with a complete digital conversion value corresponding to
the analog input value.
The conversion time is 2 times the normal-time conversion time when:
• The first AD conversion is performed in the 12-bit AD conversion mode after a system reset.
• The first AD conversion is performed after the AD conversion mode is switched from 8-bit to 12-bit
conversion mode.
No.A1156-19/26
LC87F7DC8A
Consumption Current Characteristics at Ta = -40°C to +85°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
Specification
Pin/
Parameter
Symbol
Conditions
Remarks
V
[V]
min
typ max
unit
DD
Normal mode
consumption
current
IDDOP(1)
V
1
• FmCF=12MHz ceramic oscillation mode
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 12MHz side
DD
=V
2
3
4.5 to 5.5
3.0 to 3.6
7.4
19.9
10.9
DD
DD
=V
(Note 7-1)
• Internal RC oscillation stopped.
IDDOP(2)
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
4.8
IDDOP(3)
IDDOP(4)
IDDOP(5)
IDDOP(6)
IDDOP(7)
IDDOP(8)
• FmCF=8MHz ceramic oscillation mode
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 8MHz side
4.5 to 5.5
3.0 to 3.6
2.5 to 3.0
4.5 to 5.5
3.0 to 3.6
2.2 to 3.0
5.9
3.9
3
14.9
8.8
6.8
8.5
5.3
4.4
• Internal RC oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
• FmCF=4MHz ceramic oscillation mode
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 4MHz side
3.4
2.4
2.0
• Internal RC oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
mA
IDDOP(9)
IDDOP(10)
IDDOP(11)
IDDOP(12)
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to internal RC oscillation
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
4.5 to 5.5
3.0 to 3.6
2.2 to 3.0
0.6
0.4
0.3
3.1
1.7
1.35
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
• Internal RC oscillation stopped.
• System clock set to 10MHz with
frequency variable RC oscillation
• 1/1 frequency division ratio
4.5 to 5.5
3.0 to 3.6
6.5
4.2
20.0
12.0
IDDOP(13)
IDDOP(14)
IDDOP(15)
IDDOP(16)
IDDOP(17)
IDDOP(18)
IDDOP(19)
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
• Internal RC oscillation stopped.
• System clock set to 4MHz with
4.5 to 5.5
3.0 to 3.6
2.2 to 3.0
4.5 to 5.5
3.0 to 3.6
2.2 to 3.0
3.1
2.0
11.5
6.6
frequency variable RC oscillation
• 1/1 frequency division ratio
1.6
3.5
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 32.768kHz side
• Internal RC oscillation stopped.
44.4
26.1
13.0
128.7
56.9
43.3
μA
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors.
Continued on next page.
No.A1156-20/26
LC87F7DC8A
Continued from preceding page.
Specification
typ max
Pin/
Parameter
Symbol
Conditions
Remarks
V
[V]
min
unit
DD
HALT mode
consumption
current
IDDHALT(1)
V
1
• HALT mode
DD
=V
=V
2
3
• FmCF=12MHz ceramic oscillation mode
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 12MHz side
• Internal RC oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
DD
DD
4.5 to 5.5
3.0 to 3.6
3.2
8.5
(Note 7-1)
IDDHALT(2)
1.9
4.4
IDDHALT(3)
IDDHALT(4)
• HALT mode
4.5 to 5.5
3.0 to 3.6
2.5 to 3.0
4.5 to 5.5
3.0 to 3.6
2.2 to 3.0
2.3
1.4
1.0
1.4
0.8
0.6
6.2
3.1
2.5
3.9
1.8
1.3
• FmCF=8MHz ceramic oscillation mode
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 8MHz side
• Internal RC oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
IDDHALT(5)
IDDHALT(6)
• HALT mode
• FmCF=4MHz ceramic oscillation mode
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 4MHz side
• Internal RC oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
IDDHALT(7)
IDDHALT(8)
mA
IDDHALT(9)
IDDHALT(10)
IDDHALT(11)
IDDHALT(12)
• HALT mode
4.5 to 5.5
3.0 to 3.6
2.2 to 3.0
0.3
0.18
0.14
1.3
0.75
0.54
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to internal RC oscillation
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
• HALT mode
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
• Internal RC oscillation stopped.
• System clock set to 10MHz with
frequency variable RC oscillation
• 1/1 frequency division ratio
4.5 to 5.5
3.0 to 3.6
2.7
1.7
7.1
4.6
IDDHALT(13)
IDDHALT(14)
IDDHALT(15)
• HALT mode
4.5 to 5.5
3.0 to 3.6
2.2 to 3.0
4.5 to 5.5
1.3
0.8
3.5
1.75
1.2
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
• Internal RC oscillation stopped.
• System clock set to 4MHz with
frequency variable RC oscillation
• 1/1 frequency division ratio
IDDHALT(16)
IDDHALT(17)
0.6
• HALT mode
19.0
100.3
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 32.768kHz side
• Internal RC oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
IDDHALT(18)
IDDHALT(19)
3.0 to 3.6
2.2 to 3.0
7.9
4.9
38.0
26.0
μA
HOLD mode
consumption
current
IDDHOLD(1)
IDDHOLD(2)
IDDHOLD(3)
IDDHOLD(4)
IDDHOLD(5)
IDDHOLD(6)
V
1
• HOLD mode
4.5 to 5.5
3.0 to 3.6
2.2 to 3.0
4.5 to 5.5
3.0 to 3.6
0.14
0.03
0.01
15.5
6.3
32.5
12.0
14.0
58.0
32.0
DD
• CF1=V
DD
or open (External clock mode)
Timer HOLD
mode
• Timer HOLD mode
• CF1=V or open (External clock mode)
DD
• FmX’tal=32.768kHz crystal oscillation mode
consumption
current
2.2 to 3.0
3.6
20.0
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors.
No.A1156-21/26
LC87F7DC8A
F-ROM Write Characteristics at Ta = +10°C to +55°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
Specification
Pin/Rem
Parameter
Symbol
Conditions
arks
V
[V]
min
typ max
unit
mA
DD
Onboard
IDDFW(1)
V
1
DD
• 128-byte programming
programming
current
• Erasing current included
3.0 to 5.5
3.0 to 5.5
25
40
Programming
time
tFW(1)
• 128-byte programming
• Erasing current included
• Time for setting up 128-byte data is
excluded.
22.5
45
ms
UART (Full Duplex) Operating Conditions at Ta = -40 to +85°C, V 1 = V 2 = V 3 = 0V
SS
SS
Specification
SS
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
16/3
typ
max
unit
DD
Transfer ate
UBR
UTX(P32),
URX(P33)
2.2 to 5.5
8192/3
tCYC
Data length: 7/8/9 bits (LSB first)
Stop bits:
1 bit (2-bit in continuous data transmission)
Parity bits: None
Example of 8-bit Data Transmission Mode Processing (Transmit Data=55H)
Start bit
Stop bit
End of
transmission
Start of
transmission
Transmit data (LSB first)
UBR
Example of 8-bit Data Reception Mode Processing (Receive Data=55H)
Stop bit
Start bit
End of
reception
Start of
reception
Receive data (LSB first)
UBR
No.A1156-22/26
LC87F7DC8A
Characteristics of a Sample Main System Clock Oscillation Circuit
Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a
SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values
with which the oscillator vendor confirmed normal and stable oscillation.
Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator
Operating
Voltage
Range
[V]
Oscillation
Circuit Constant
Nominal
Vendor
Name
Stabilization Time
Oscillator Name
Remarks
Frequency
C1
C2
Rf1
Rd1
typ
max
[ms]
[pF]
[pF]
[Ω]
[Ω]
[ms]
Values shown in
parentheses are
capacitance included
in the oscillator
12MHz
8MHz
4MHz
MURATA
MURATA
MURATA
CSTCE12M0G52-R0
(10)
(10)
Open
Values shown in
parentheses are
capacitance included
in the oscillator
CSTCE8M00G52-R0
CSTLS8M00G52-R0
CSTCR4M00F53-R0
CSTLS4M0053-B0
(10)
(15)
(15)
(15)
(10)
(15)
(15)
(15)
Open
Open
Open
Open
Values shown in
parentheses are
capacitance included
in the oscillator
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after V
goes above the operating voltage lower limit (see Figure 4).
DD
Characteristics of a Sample Subsystem Clock Oscillator Circuit
Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a SANYO-
designated oscillation characteristics evaluation board and external components with circuit constant values with which
the oscillator vendor confirmed normal and stable oscillation.
Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator
Oscillation
Circuit Constant
Operating
Voltage Range
[V]
Nominal
Oscillator
Name
Stabilization Time
Vendor Name
Remarks
Frequency
C3
C4
Rf2
Rd2
typ
[s]
max
[s]
[pF]
[pF]
[Ω]
[Ω]
EPSON
32.768kHz
MC-306
TOYOCOM
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the
instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the
oscillation to get stabilized after the HOLD mode is reset (see Figure 4).
Note: The components that are involved in oscillation should be placed as close to the IC and to one another as possible
because they are vulnerable to the influences of the circuit pattern.
XT1
XT2
CF1
CF2
Rf2
Rf1
Rd2
C4
Rd1
C2
C3
C1
X’tal
CF
Figure 1 CF Oscillator Circuit
Figure 2 XT Oscillator Circuit
No.A1156-23/26
LC87F7DC8A
0.5V
DD
Figure 3 AC Timing Measurement Point
V
DD
Operating V
lower limit
0V
DD
Power supply
Reset time
RES
Internal RC
oscillation
tmsCF
CF1, CF2
tmsX’tal
XT1, XT2
Operating mode
Reset
Instruction execution
Unpredictable
Reset Time and Oscillation Stabilization Time
HOLD reset signal VALID
HOLD reset signal
HOLD reset signal
absent
Internal RC
oscillation
tmsCF
CF1, CF2
tmsX’tal
XT1, XT2
State
HOLD
HALT
HOLD Reset Signal and Oscillation Stabilization Time
Figure 4 Oscillation Stabilization Times
No.A1156-24/26
LC87F7DC8A
V
DD
R
C
Note:
RES
Determine the value of C
and R so that the
RES
RES
reset signal is present for a period of 200μs after the
supply voltage goes beyond the lower limit of the IC's
operating voltage.
RES
RES
Figure 5 Reset Circuit
SIOCLK:
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
DATAIN:
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DO8
DATAOUT:
Data RAM
transfer period
(SIO0 only)
tSCK
tSCKH
thDI
tSCKL
SIOCLK:
DATAIN:
tsDI
tdDO
DATAOUT:
Data RAM
transfer period
(SIO0 only)
tSCKL
tSCKHA
SIOCLK:
DATAIN:
tsDI
thDI
tdDO
DATAOUT:
Figure 6 Serial I/O Waveforms
tPIL
tPIH
Figure 7 Pulse Input Timing Signal Waveform
No.A1156-25/26
LC87F7DC8A
V
DD
SW : ON/OFF (programmable)
RLCD
RLCD
RLCD
RLCD
SW: ON (VLCD=V
)
DD
VLCD
RLCD
RLCD
2/3VLCD
1/2VLCD
RLCD
RLCD
1/3VLCD
RLCD
RLCD
GND
Figure 8 LCD Bias Resistor
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using
products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.
products described or contained herein.
SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all
semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or
malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise
to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt
safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not
limited to protective circuits and error prevention circuits for safe design, redundant design, and structural
design.
In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are
controlled under any of applicable local export control laws and regulations, such products may require the
export license from the authorities concerned in accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise,
without the prior written consent of SANYO Semiconductor Co.,Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the
SANYO Semiconductor Co.,Ltd. product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed
for volume production.
Upon using the technical information or products described herein, neither warranty nor license shall be granted
with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third
party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's
intellectual property rights which has resulted from the use of the technical information and products mentioned
above.
This catalog provides information as of February, 2010. Specifications and information herein are subject
to change without notice.
No.A1156-26/26
PS
相关型号:
LC87F7J32AU-QIP-E
8-bit LCD Driver Microcontroller with 32K-byte Flash ROM and 1024-byte RAM, PQFP64 14x14 / QIP64E, 300-FTRAY
ONSEMI
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