LC87F7NJ2AVUEJ-2H [ONSEMI]
8-bit LCD Driver Microcontroller with 192K-byte Flash ROM and 8K-byte RAM;
| 型号： | LC87F7NJ2AVUEJ-2H |
| 厂家： | 
ONSEMI |
| 描述： | 8-bit LCD Driver Microcontroller with 192K-byte Flash ROM and 8K-byte RAM CD 微控制器 外围集成电路 |
| 文件： | 总28页 (文件大小：423K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LC87F7NJ2A
CMOS LSI
8-bit Microcontroller
www.onsemi.com
with LCD Controller Driver
192K-byte Flash ROM / 8K-byte RAM / 100-pin
Features
LCD Driver 4COM × 54SEG
Infrared Remote Control Receiver Circuit × 2
Full duplex UART × 2
Performance
Minimum Bus Cycle Time
56ns (CF=18MHz)
QIP100E(14X20)
Minimum Instruction Cycle Time (Tcyc)
167ns (CF=18MHz)
Operating Supply Voltage
2.7V to 3.6V
Operating Ambient Temperature
40°C to +85°C
Function Descriptions
1) Ports
I/O Ports
29
LCD Common Ports
LCD Segment Ports
Bias Power Source For LCD
4
TQFP100(14X14)
[ Under Development ]
54 (I/O port combined use)
3
6
Power Pins (V 1, V 1)
SS DD
2) Timer × 8
Timer 0 : 16-bit timer/counter with capture registers
Timer 1 : 16-bit timer that supports PWM/toggle outputs
Timer 4 : 8-bit timer with a 6-bit prescaler
Timer 5 : 8-bit timer with a 6-bit prescaler
Timer 6 : 8-bit timer with a 6-bit prescaler (with toggle output)
Timer 7 : 8-bit timer with a 6-bit prescaler (with toggle output)
Timer 8 : 16-bit timer with an 8-bit prescaler
S20/PC4
S19/PC3
S18/PC2
S17/PC1
S16/PC0
S15/PB7
S14/PB6
S13/PB5
S12/PB4
S11/PB3
S10/PB2
S9/PB1
S8/PB0
S7/PA7
S6/PA6
S5/PA5
S4/PA4
S3/PA3
S2/PA2
S1/PA1
V2/PL5/AN13/DBGP1
V1/PL4/AN12/DBGP0
COM0/PL0
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
COM1/PL1
COM2/PL2
COM3/PL3
P30/INT4/T1IN/INT6/T0LCP1/PWM4/S48
P31/INT4/T1IN/PWM5/S49
VSS3
Base timer
VDD3
3) Full duplex UART × 2
4) Infrared Remote Control Receiver Circuit × 2
P32/INT4/T1IN/UTX1/S50
P33/INT4/T1IN/URX1/S51
P34/INT5/T1IN/INT7/T0HCP1/UTX2/S52
P35/INT5/T1IN/URX2/S53
P00/DGBP0
P01/DGBP1
P02 /DGBP2
P03/INT6
P04/INT7
P05/CKO
Application
AV apparatus
Household appliance mounted with LCD panel
* This product is licensed from Silicon Storage Technology, Inc. (USA).
Pin Assignment : QIP100E(14x20)
[ Top view ]
ORDERING INFORMATION
See detailed ordering and shipping information on page 28 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
November 2014 - Rev. 1
1
Publication Order Number :
LC87F7NJ2A/D
LC87F7NJ2A
Function Details
Ports
Normal withstand voltage I/O ports
Ports whose I/O direction can be designated in 1 bit units : 29 (P0n, P1n, P70 to P73, P8n, XT2)
Normal withstand voltage input port
LCD ports
: 1 (XT1)
Segment output
Common output
Bias power sources for LCD driver
Other functions
: 54 (S00 to S53)
: 4 (COM0 to COM3)
: 3 (V1 to V3)
Input/output ports
Input ports
: 54 (P3n, PAn, PBn, PCn, PDn, PEn, PFn)
: 7 (PLn)
Dedicated oscillator ports
Reset pins
: 2 (CF1, CF2)
: 1 (
RES
)
Power pins
: 6 (V 1 to V 3, V 1 to V 3)
SS SS DD DD
LCD Controller
1) Seven display modes are available (static, 1/2, 1/3, 1/4 duty 1/2, 1/3 bias)
2) Segment output and common output can be switched to general-purpose input/output ports
Small Signal Detection (MIC signals etc.)
1) Counts pulses with a level which is greater than a preset value
2) 2-bit counter
Timers
Timer 0 : 16-bit timer/counter with two capture registers.
Mode 0 : 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) 2 channels
Mode 1 : 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) + 8-bit counter
(with two 8-bit capture registers)
Mode 2 : 16-bit timer with an 8-bit programmable prescaler (with two 16-bit capture registers)
Mode 3 : 16-bit counter (with two 16-bit capture registers)
Timer1 : 16-bit counter timer that supports PWM/toggle outputs
Mode 0 : 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer counter with an 8-bit prescaler
(with toggle outputs)
Mode 1 : 8-bit PWM with an 8-bit prescaler 2 channels
Mode 2 : 16-bit counter timer with an 8-bit prescaler (with toggle outputs)
(toggle outputs also possible from the lower-order 8 bits)
Mode 3 : 16-bit timer with an 8-bit prescaler (with toggle outputs) (The lower-order 8 bits can be used as PWM.)
Timer4 : 8-bit timer with a 6-bit prescaler
Timer5 : 8-bit timer with a 6-bit prescaler
Timer6 : 8-bit timer with a 6-bit prescaler (with toggle output)
Timer7 : 8-bit timer with a 6-bit prescaler (with toggle output)
Timer8 : 16-bit timer
Mode 0 : 8-bit timer with an 8-bit prescaler 2 channels
Mode 1 : 16-bit timer with an 8-bit prescaler
Base Timer
1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler
output.
2) Interrupts programmable in 5 different time schemes
Day and time counter
1) Used with a base timer, the day and time counter can be used as a 65000 day + minute + second counter.
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LC87F7NJ2A
High-speed Clock Counter
1) Can count clocks with a maximum clock rate of 20MHz (at a main clock of 10MHz).
2) Can generate output real-time.
Serial Interfaces
SIO0 : 8-bit synchronous serial interface
1) LSB first/MSB first made selectable
2) Built-in 8-bit baudrate generator (maximum transfer clock cycle 4/3tCYC)
3) Automatic continuous data transmission (1 to 256 bits specifiable in 1-bit units, suspension and resumption of
data transmission possible in 1-byte units)
SIO1 : 8-bit asynchronous/synchronous serial interface
Mode 0 : Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks)
Mode 1 : Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates)
Mode 2 : Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks)
Mode 3 : Bus mode 2 (start detect, 8 data bits, stop detect)
UART1
Full duplex
7/8/9 bit data bits selectable
1 stop bit (2 bits in continuous data transmission)
Built-in baudrate generator
UART2
Full duplex
7/8/9 bit data bits selectable
1 stop bit (2 bits in continuous data transmission)
Built-in baudrate generator
AD Converter :12 bits 15 channels
PWM :Multi frequency 12-bit PWM 2 channels
Infrared Remote Control Receiver Circuit1
1) Noise reduction function (Time constant of noise reduction filter : approx. 120s, when selecting a 32.768kHz
crystal oscillator as a reference clock)
2) Supporting reception formats with a guide-pulse of half-clock/clock/none.
3) Determines a end of reception by detecting a no-signal periods (No carrier).
(Supports same reception format with a different bit length.)
4) X’tal HOLD mode cancellation function
Infrared Remote Control Receiver Circuit2
1) Noise reduction function
(Time constant of noise reduction filter: approx. 120μs, when selecting a 32.768kHz crystal oscillator as a
reference clock.)
2) Supporting reception formats with a guide-pulse of half-clock/clock/none.
3) Determines a end of reception by detecting a no-signal periods (No carrier).
(Supports same reception format with a different bit length.)
4) X’tal HOLD mode cancellation function
Watchdog Timer
1) External RC watchdog timer
2) Interrupt and reset signals selectable
Clock Output Function
1) Can output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, or 1/64 as a system clock.
2) Can output the source oscillation clock for the sub clock.
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LC87F7NJ2A
Interrupt Source Flags
31 sources, 10 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests
of the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest
level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest
vector address takes precedence.
No.
1
Vector Address
00003H
Level
X or L
X or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
Interrupt Source
INT0
INT1
2
0000BH
00013H
3
INT2/T0L/INT4/remote control receiver1
INT3/base timer/INT5/ remote control receiver2
T0H/INT6
4
0001BH
00023H
5
6
0002BH
00033H
T1L/T1H/INT7
7
SIO0/UART1 receive/ UART2 receive/T8L/T8H
SIO1/UART1 transmit/ UART2 transmit
ADC/MIC/T6/T7/PWM4/PWM5
Port 0/T4/T5
8
0003BH
00043H
9
10
0004BH
Priority levels X > H > L
Of interrupts of the same level, the one with the smallest vector address takes precedence.
IFLG (List of interrupt source flag function)
1) Shows a list of interrupt source flags that caused a branching to a particular vector address.
Subroutine Stack Levels
2048 levels maximum (The stack is allocated in RAM.)
High-speed Multiplication/Division Instructions
16 bits 8 bits
24 bits 16 bits
16 bits 8 bits
24 bits 16 bits
(5 tCYC execution time)
(12 tCYC execution time)
(8 tCYC execution time)
(12 tCYC execution time)
Oscillation Circuits
RC oscillation circuit (internal) : For system clock
CF oscillation circuit : For system clock, with internal Rf and external Rd
Crystal oscillation circuit : For low-speed system clock, with internal Rf and external Rd
Multifrequency RC oscillation circuit (internal) : For system clock
1) Adjustable in ±4 (typ) increments from the selected center frequency.
2) Measures the frequency of the source oscillation clock using the input signal from XT1 as the reference.
System Clock Divider Function
Can run on low current.
The minimum instruction cycle selectable from 300ns, 600ns, 1.2s, 2.4s, 4.8s, 9.6s, 19.2s, 38.4s, and
76.8s (at a main clock rate of 10MHz).
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LC87F7NJ2A
Standby Function
HALT mode : Halts instruction execution while allowing the peripheral circuits to continue operation
(Some parts of the serial transfer function stop operation) .
1) Oscillation is not stopped automatically.
2) Canceled by a system reset or occurrence of an interrupt
HOLD mode : Suspends instruction execution and the operation of the peripheral circuits.
1) The CF, RC, X’tal, and multifrequency RC oscillators automatically stop operation.
2) There are three ways of resetting the HOLD mode.
(1) Setting the reset pin to the low level
(2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level
(3) Having an interrupt source established at port 0
X'tal HOLD mode : Suspends instruction execution and the operation of the peripheral circuits except the base
timer and infrared remote controller circuit.
1) The CF, RC, and multifrequency RC oscillators automatically stop operation.
2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained.
3) There are five ways of resetting the X'tal HOLD mode.
(1) Setting the reset pin to the low level
(2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level
(3) Having an interrupt source established at port 0
(4) Having an interrupt source established in the base timer circuit
(5) Having an interrupt source established in the infrared remote control receiver circuit
On-chip Debugger Function
Supports software debugging with the IC mounted on the target board.
Package Form
QIP100E(1420)
QFP100(14
: Pb-Free / Halogen Free type
: Pb-Free / Halogen Free type [Under Development]
Development Tools
On-chip Debugger : TCB87 TypeB +LC87F7Nxx A or TCB87 TypeC (3Lines Cable) +LC87F7NxxA
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LC87F7NJ2A
Flash ROM Programming boards
Package
Programming Boards
QIP100E(1420)
TQFP100(1414)
W87FQ100
W87FSQ100
Flash ROM Programmer
Model
Supported Version
(Note 2)
Device
Maker
LC87F7NP6A
LC87F7NJ2A
LC87F7NC8A
Single
AF9709C
Programmer
AF9723/AF9723B(main unit)
(including models manufactured by
Ando Electric Co., Ltd.)
AF9833(unit)
Flash Support Group, Inc
(FSG)
(Note 2)
(Note 2)
LC87F7NP6A
LC87F7NJ2A
LC87F7NC8A
Gang
Programmer
(including models manufactured by
Ando Electric Co., Ltd.)
AF9101/AF9103(main unit)
(manufactured by FSG)
SIB87 Type C
Flash Support Group, Inc
(FSG)
In-circuit
LC87F7NP6A
LC87F7NJ2A
LC87F7NC8A
Single/Gang
Programmer
(Note 2)
+Our company
(Note 1)
(Interface Driver)
(Our company model)
SKK Type B / Type C
(SanyoFWS)
Single/Gang
Programmer
In-circuit
Application Version
1.08or later
LC87F7NP6A
LC87F7NJ2A
LC87F7NC8A
Our company
Chip Data Version
2.44 later
SKK-DBG Type B /Type C
(SanyoFWS)
Single/Gang
Programmer
Contact information about the AF series :
Flash Support Group Company (TOA ELECTRONICS, Inc.)
Phone : 81-53-428-8380
E-mail : sales@j-fsg.co.jp
Note1 : On-board-programmer from FSG (AF9101/AF9103) and serial interface driver from our company (SIB87)
together can give a PC-less, standalone on-board-programming capabilities.
Note2 : It needs a special programming devices and applications depending on the use of programming environment.
Please ask FSG or our company for the information.
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LC87F7NJ2A
Package Dimensions
unit : mm
PQFP100 14x20 / QIP100E
CASE 122BV
ISSUE A
23.2 0.2
20.0 0.1
1 2
0.15
0.65
0.3 0.05
0.13
(0.58)
0 to 10
0.10
SOLDERING FOOTPRINT*
22.30
GENERIC
MARKING DIAGRAM*
(Unit: mm)
XXXXXXXXX
YMDDD
XXXXX = Specific Device Code
Y = Year
M = Month
0.65
0.43
DDD = Additional Traceability Data
NOTE: The measurements are not to guarantee but for reference only.
*This information is generic. Please refer to
device data sheet for actual part marking.
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
may or may not be present.
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LC87F7NJ2A
Package Dimensions
unit : mm
*Package TQFP100(1414) type is Under Development.
TQFP100 14x14 / TQFP100
CASE 932AY
ISSUE A
16.0 0.2
14.0 0.1
1
2
0.125
0.5
0.2
0.10
(1.0)
0 to 10
0.10
SOLDERING FOOTPRINT*
GENERIC
MARKING DIAGRAM*
15.40
XXXXXXXX
YMDDD
(Unit: mm)
XXXXX = Specific Device Code
Y = Year
M = Month
DDD = Additional Traceability Data
*This information is generic. Please refer to
device data sheet for actual part marking.
may or may not be present.
0.50
0.28
NOTE: The measurements are not to guarantee but for reference only.
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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LC87F7NJ2A
Pin Assignment
QIP100E(1420), Pb-Free/Halogen Free type
S20/PC4
S19/PC3
S18/PC2
S17/PC1
S16/PC0
S15/PB7
S14/PB6
S13/PB5
S12/PB4
S11/PB3
S10/PB2
S9/PB1
S8/PB0
S7/PA7
S6/PA6
S5/PA5
S4/PA4
S3/PA3
S2/PA2
S1/PA1
V2/PL5/AN13/DBGP1
V1/PL4/AN12/DBGP0
COM0/PL0
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
COM1/PL1
COM2/PL2
COM3/PL3
P30/INT4/T1IN/INT6/T0LCP1/PWM4/S48
P31/INT4/T1IN/PWM5/S49
VSS3
VDD3
P32/INT4/T1IN/UTX1/S50
P33/INT4/T1IN/URX1/S51
P34/INT5/T1IN/INT7/T0HCP1/UTX2/S52
P35/INT5/T1IN/URX2/S53
P00/DGBP0
P01/DGBP1
P02 /DGBP2
P03/INT6
P04/INT7
P05/CKO
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LC87F7NJ2A
TQFIP100(1414), Pb-Free/Halogen Free type [Under Development]
S47/PF7
V3/PL6/AN14/DBGP2
V2/PL5/AN13/DBGP1
V1/PL4/AN12/DBGP0
COM0/PL0
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
S23/PC7
S22/PC6
S21/PC5
S20/PC4
S19/PC3
S18/PC2
S17/PC1
S16/PC0
S15/PB7
S14/PB6
S13/PB5
S12/PB4
S11/PB3
S10/PB2
S9/PB1
S8/PB0
S7/PA7
S6/PA6
S5/PA5
S4/PA4
S3/PA3
S2/PA2
S1/PA1
COM1/PL1
COM2/PL2
COM3/PL3
P30/INT4/T1IN/INT6/T0LCP1/PWM4/S48
P31/INT4/T1IN/PWM5/S49
V
V
3
3
SS
DD
P32/INT4/T1IN/UTX1/S50
P33/INT4/T1IN/URX1/S51
P34/INT5/T1IN/INT7/T0HCP1/S52
P35/INT5/T1IN/S52
P00/DGBP0
P01/DGBP1
P02/T8LO/DGBP2
P03/T8HO
P04
P05/CKO
P06/T6O
P07/T7O
S0/PA0
P73/INT3/T0IN/RMIN
P10/SO0
Top view
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LC87F7NJ2A
System Block Diagram
Interrupt control
IR
PLA
Standby control
CF
Flash ROM
RC
VMRC
PC
X’tal
ACC
B register
C register
ALU
SIO0
SIO1
Bus interface
Port 0
Timer 0
(High speed clock counter)
PSW
RAR
Port 1
Timer 1
Base timer
Port 3
Port 7
RAM
LCD Controller
Port 8
INT0 to 7
Noise Rejection Filter
ADC
Stack pointer
Watchdog timer
On-chip debugger
Small signal
detector
Timer 4
Timer 5
UART1
PWM4/5
Timer 6
UART2
Timer 7
Timer 8
Remote control
receiver circuit 1
Remote control
receiver circuit 2
Day and time
counter
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LC87F7NJ2A
Pin Description
Pin Name
I/O
-
Description
Option
No
V
V
V
V
V
V
1
2
3
1
power supply pin
SS
SS
SS
-
+ power supply pin
No
DD
DD
DD
2
3
Port 0
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 1-bit units
P00 to P07
• Pull-up resistors can be turned on and off in 1-bit units.
• Input for HOLD release
• Input for port 0 interrupt
• Shared pins
P03: INT6 input
P04: INT7 input
P05: Clock output (system clock/can selected from sub clock)
P06: Timer 6 toggle output
P07: Timer 7 toggle output
On chip debugger pins: DBGP0 to DBGP2(P00 to P02)
• 8-bit I/O port
Port 1
I/O
Yes
• I/O specifiable in 1-bit units
P10 to P17
• Pull-up resistors can be turned on and off in 1-bit units.
• Shared pins
P10: SIO0 data output
P11: SIO0 data input/bus I/O
P12: SIO0 clock I/O
P13: SIO1 data output
P14: SIO1 data input/bus I/O
P15: SIO1 clock I/O
P16: Timer 1PWML output
P17: Timer 1PWMH output/beeper output
• 6-bit I/O port
Port 3
I/O
Yes
• Segment output for LCD
P30 to P35
• I/O specifiable in 1-bit units
• Pull-up resistors can be turned on and off in 1-bit units.
• Shared pins
P30 to P33: INT4 input/HOLD release input/timer 1 event input/timer 0L capture input/
timer 0H capture input
P34 to P35: INT5 input/HOLD release input/timer 1 event input/timer 0L capture input/
timer 0H capture input
P30: PWM4 output/INT6 input/timer 0L capture 1 input
P31: PWM5 output
P32: UART1 transmit
P33: UART1 receive
P34: UART2 transmit/INT7 input/timer 0H capture 1 input
P35: UART2 receive
Interrupt acknowledge type
Rising &
Rising
Falling
H level
L level
Falling
enable
enable
enable
enable
INT4
INT5
INT6
INT7
enable
enable
enable
enable
enable
enable
enable
enable
disable
disable
disable
disable
disable
disable
disable
disable
Continued on next page.
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LC87F7NJ2A
Continued from preceding page.
Pin Name
Port 7
I/O
I/O
Description
Option
No
• 4-bit I/O port
• I/O specifiable in 1-bit units
P70 to P73
• Pull-up resistors can be turned on and off in 1-bit units.
• Shared pins
P70: INT0 input/HOLD release input/timer 0L capture input/watchdog timer output
P71: INT1 input/HOLD release input/timer 0H capture input
P72: INT2 input/HOLD release input/timer 0 event input/timer 0L capture input/
high speed clock counter input
P73: INT3 input (with noise filter)/timer 0 event input/timer 0H capture input/
remote control receiver input
AD converter input ports: AN8 (P70), AN9 (P71)
Interrupt acknowledge type
Rising &
Rising
Falling
H level
L level
Falling
disable
disable
enable
enable
INT0
INT1
INT2
INT3
enable
enable
enable
enable
enable
enable
enable
enable
enable
enable
disable
disable
enable
enable
disable
disable
Port 8
I/O
• 8-bit I/O port
No
• I/O specifiable in 1-bit units
• Shared pins
P80 to P87
AD converter input ports: AN0 to AN7
Small signal detector input port: MICIN (P87)
• Segment output for LCD
S0/PA0 to
S7/PA7
I/O
I/O
I/O
I/O
I/O
I/O
No
No
No
No
No
No
• Can be used as general-purpose I/O port (PA)
• Segment output for LCD
S8/PB0 to
S15/PB7
• Can be used as general-purpose I/O port (PB)
• Segment output for LCD
S16/PC0 to
S23/PC7
S24/PD0 to
S31/PD7
S32/PE0 to
S39/PE7
• Can be used as general-purpose I/O port (PC)
• Segment output for LCD
• Can be used as general-purpose I/O port (PD)
• Segment output for LCD
• Can be used as general-purpose I/O port (PE)
• Segment output for LCD
S40/PF0 to
S47/PF7
• Can be used as general-purpose I/O port (PF)
PF6: INT6 input
PF7: INT7 input
COM0/PL0 to
COM3/PL3
V1/PL4 to
V3/PL6
I/O
I/O
• Common output for LCD
No
No
• Can be used as general-purpose input port (PL)
• LCD output bias power supply
• Can be used as general-purpose input port (PL)
• Shared pins
AD converter input ports: AN12 (V1) to AN14 (V3)
On-chip debugger pins: DBGP0 (V1) to DBGP2 (V3)
RES
XT1
Input
Input
No
No
Reset pin
• 32.768kHz crystal oscillator input pin
• Shared pins
General-purpose input port
Must be connected to V 1 if not to be used.
DD
AD converter input port: AN10
• 32.768kHz crystal oscillator output pin
• Shared pins
XT2
I/O
No
General-purpose I/O port
Must be set for oscillation and kept open if not to be used.
AD converter input port: AN11
Ceramic resonator input pin
CF1
CF2
Input
No
No
Output
Ceramic resonator output pin
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13
LC87F7NJ2A
Port Output Types
The table below lists the types of port outputs and the presence/absence of a pull-up resistor.
Data can be read into any input port even if it is in the output mode
Option Selected
Port Name
Option Type
Output Type
Pull-up Resistor
in Units of
each bit
P00 to P07
1
2
CMOS
Programmable (Note)
Programmable
Programmable
Programmable
Programmable
Programmable
Programmable
Programmable
No
Nch-open drain
CMOS
P10 to P17
P30 to P35
each bit
each bit
1
2
Nch-open drain
CMOS
1
2
Nch-open drain
Nch-open drain
CMOS
P70
-
-
-
-
-
No
No
No
No
No
P71 to P73
P80 to P87
S0/PA0 to S47/PF7
Nch-open drain
CMOS
Programmable
COM0/PL0 to
COM3/PL3
Input only
No
V1/PL4 to V3/PL6
-
-
-
No
No
No
Input only
Input only
No
No
XT1
XT2
Output for 32.768kHz crystal oscillator
(Nch-open drain when in general-purpose
output mode)
No
User Option List
Mask Version
*1
Option Selected in
Option Name
Option Type
Flash Version
Units of
Specified Item
CMOS
P00 to P07
each bit
each bit
each bit
-
Nch-open drain
CMOS
Port output form
P10 to P17
P30 to P35
-
Nch-open drain
CMOS
Nch-open drain
00000H
Program start
address
*2
1FF00H
*1: Mask option selection - No change possible after the mask is completed.
*2: Program start address of the mask version is 00000H.
LSI
V
1
DD
Power
supply
For backup *2
V
V
2
3
DD
DD
V
1 V
2
SS
V
3
SS
SS
*1: Connect the IC as shown below to minimize the noise input to the V 1 pin.
DD
Be sure to electrically short the V 1, V 2, and V 3 pins.
SS SS SS
*2: The internal memory is sustained by V 1. If none of V 2 and V 3 are backed up, the high level output at
DD DD DD
the ports are unstable in the HOLD backup mode, allowing through current to flow into the input buffer and thus
shortening the backup time.
Make sure that the port outputs are held at the low level in the HOLD backup mode.
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14
LC87F7NJ2A
Absolute Maximum Ratings at Ta = 25°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
Specification
typ max
+4.6
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
0.3
unit
DD
Maximum supply voltage
V
max
V
1, V 2, V
3
V
V
1=V 2=V
DD
3
3
DD
DD
DD
DD
DD
DD
supply voltage for
LCD
VLCD
V1/PL4, V2/PL5,
V3/PL6
1=V 2=V
DD
DD
DD
0.3
0.3
V
DD
Input voltage
V (1)
I
Port L
V
V
+0.3
+0.1
DD
DD
RES
3
XT1, CF1,
V 2, V
DD
V
V (2)
I
V
DD
SS
Input/output voltage
V
(1)
IO
Ports 0, 1, 3, 7, 8
Ports A, B, C, D, E, F,
XT2
0.3
V
+0.3
DD
Peak output
current
IOPH(1)
IOPH(2)
Ports 0, 1, 32 to 35
• CMOS output selected
• Current at each pin
• CMOS output selected
• Current at each pin
Current at each pin
10
20
Ports 30, 31
IOPH(3)
IOPH(4)
IOMH(1)
Ports 71 to 73
5
5
Ports A, B, C, D, E, F
Ports 0, 1, 32 to 35
Current at each pin
Mean output
current
• CMOS output selected
• Current at each pin
• CMOS output selected
• Current at each pin
Current at each pin
7.5
15
(Note 1-1)
IOMH(2)
Ports 30, 31
IOMH(3)
IOMH(4)
IOAH(1)
IOAH(2)
IOAH(3)
IOAH(4)
IOAH(5)
IOAH(6)
IOAH(7)
IOPL(1)
Ports 71 to 73
3
3
Ports A, B, C, D, E, F
Ports 0, 1, 32 to 35
Ports 30, 31
Current at each pin
Total of all pins
Total of all pins
Total of all pins
Total of all pins
Total of all pins
Total of all pins
Total of all pins
Current at each pin
Current at each pin
Current at each pin
Total output
current
25
25
45
5
Ports 0, 1, 3
Ports 71 to 73
Ports A, B, C
25
25
45
Ports D, E, F
Ports A, B, C, D, E, F
Ports 0, 1, 32 to 35
Ports 30, 31
mA
Peak output
current
20
30
IOPL(2)
IOPL(3)
Ports 7, 8
10
XT2
IOPL(4)
IOML(1)
IOML(2)
IOML(3)
Ports A, B, C, D, E, F
Current at each pin
Current at each pin
Current at each pin
Current at each pin
10
15
20
Mean output
current
Ports 0, 1, 32 to 35
Ports 30, 31
(Note 1-1)
Ports 7, 8
7.5
XT2
IOML(4)
OAL(1)
IOAL(2)
IOAL(3)
IOAL(4)
Ports A, B, C, D, E, F
Current at each pin
Total of all pins
Total of all pins
Total of all pins
Total of all pins
7.5
45
45
80
Total output
current
Ports 0,1,32 to 35
Ports 30, 31
Ports 0, 1, 3
Ports 7, 8
XT2
20
IOAL(5)
IOAL(6)
IOAL(7)
Pd max
Ports A, B, C
Total of all pins
Total of all pins
Total of all pins
Ta=40 to +85C
Ta=40 to +85C
45
45
Ports D, E, F
Ports A, B, C, D, E, F
QIP100E(1420)
TQFP100(1414)
80
Maximum power
dissipation
215
mW
under
+85
Operating ambient
temperature
Topr
Tstg
40
55
C
Storage ambient
temperature
+125
Note 1-1: The mean output current is a mean value measured over 100ms.
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
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15
LC87F7NJ2A
Allowable Operating Range at Ta = 40°C to +85°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
Specification
typ max
Parameter
Symbol
Pin/Remarks
1=V 2=V 3
DD
Conditions
V
[V]
min
unit
DD
Operating
V
(1)
V
0.167stCYC200s
0.356stCYC200s
2.7
2.5
3.6
3.6
DD
DD
DD
supply voltage
(Note 2-1)
Memory
VHD
V
1
RAM and register contents
sustained in HOLD mode.
DD
sustaining
2.0
3.6
supply voltage
High level input
voltage
V
V
(1)
Ports 0, 3, 8
Output disabled
IH
0.3V
V
V
DD
DD
Ports A, B, C, D, E, F
Port L
2.5 to 3.6
2.5 to 3.6
+0.7
(2)
Port 1
• Output disabled
• When INT1VTSL=0
(P71 only)
IH
Ports 71 to 73
P70 port input/
interrupt side
P71 interrupt side
0.3V
DD
DD
+0.7
V
V
V
V
V
(3)
(4)
(5)
(6)
• Output disabled
• When INT1VTSL=1
Output disabled
IH
IH
IH
IH
2.5 to 3.6
2.5 to 3.6
2.5 to 3.6
2.5 to 3.6
0.85V
V
V
DD
DD
DD
P87 small signal
input side
0.75V
0.9V
DD
P70 watchdog timer
side
Output disabled
V
V
V
DD
DD
RES
XT1, XT2, CF1,
DD
0.75V
DD
Low level input
voltage
(1)
Ports 0, 3, 8
Output disabled
IL
Ports A, B, C, D, E, F
Port L
2.5 to 3.6
2.5 to 3.6
V
V
0.2V
SS
DD
V
(2)
Port 1
• Output disabled
• When INT1VTSL=0
(P71 only)
IL
Ports 71 to 73
P70 port input/
interrupt side
P71 interrupt side
0.2V
SS
DD
DD
V
V
V
V
(3)
(4)
(5)
(6)
• Output disabled
• When INT1VTSL=1
Output disabled
IL
IL
IL
IL
2.5 to 3.6
2.5 to 3.6
2.5 to 3.6
2.5 to 3.6
V
V
V
V
0.45V
SS
SS
SS
SS
P87 small signal
input side
0.25V
0.8V
DD
DD
P70 watchdog timer
side
Output disabled
-1.0
RES
XT1, XT2, CF1,
0.25V
DD
Instruction cycle
time
tCYC
2.7 to 3.6
2.5 to 3.6
0.167
0.356
200
200
s
(Note 2-2)
External system
clock frequency
FEXCF(1)
CF1
• CF2 pin open
• System clock frequency
division ratio=1/1
2.5 to 3.6
0.1
18
36
• External system clock
duty=50±5%
MHz
• CF2 pin open
• System clock frequency
division ratio=1/2
2.5 to 3.6
0.2
Note 2-1: V
DD
must be held greater than or equal to 3.0V in the flash ROM onboard programming mode.
Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a
division ratio of 1/2.
Continued on next page.
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16
LC87F7NJ2A
Continued from preceding page.
Specification
typ max
Parameter
Symbol
Pin/Remarks
CF1, CF2
Conditions
V
[V]
min
unit
DD
Oscillation
FmCF(1)
• 18MHz ceramic oscillation
• See Fig. 1.
2.7 to 3.6
18
frequency range
(Note 2-3)
FmCF(2)
CF1, CF2
• 8MHz ceramic oscillation
• See Fig. 1.
2.5 to 3.6
2.5 to 3.6
8
FmRC
Internal RC oscillation
0.3
1.0
2.0
FmVMRC(1)
• Frequency variable RC
source oscillation
• When
2.5 to 3.6
10
MHz
VMRAJ2 to 0=4,
VMFAJ2 to 0=0,
VMSL4M=0
FmVMRC(2)
• Frequency variable RC
source oscillation
• When
2.5 to 3.6
4
VMRAJ2 to 0=4,
VMFAJ2 to 0=0,
VMSL4M=1
FsX’tal
XT1, XT2
• 32.768kHz crystal oscillation
• See Fig. 2.
2.5 to 3.6
2.5 to 3.6
32.768
10
kHz
Frequency
variable RC
oscillation
usable range
Frequency
variable RC
oscillation
adjustment
range
OpVMRC(1)
OpVMRC(2)
When VMSL4M=0
8
12
When VMSL4M=1
MHz
2.5 to 3.6
2.5 to 3.6
2.5 to 3.6
3.5
4
24
4
4.5
VmADJ(1)
VmADJ(2)
Each step of VMRAJn
(Wide range)
8
1
64
8
Each step of VMFAJn
(Small range)
Note 2-3: See Tables 1 and 2 for the oscillation constants.
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
Electrical Characteristics at Ta = 40°C to +85°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
Specification
typ max
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
unit
DD
High level input
current
I
(1)
IH
Ports 0, 1, 3, 7, 8
• Output disabled
• Pull-up resistor off
• V =V (Including output Tr's
Ports A, B, C, D, E,
2.5 to 3.6
1
F
IN DD
off leakage current)
Port L
RES
I
I
(2)
IH
V
=V
2.5 to 3.6
2.5 to 3.6
2.5 to 3.6
2.5 to 3.6
1
1
IN DD
(3)
IH
XT1, XT2
• For input port specification
• V =V
IN DD
I
I
(4)
IH
CF1
V =V
IN DD
15
10
(5)
IH
P87 small signal
input side
V =VBIS+0.5V
IN
1.5
5.5
(VBIS: Bias voltage)
A
Low level input
current
I
(1)
IL
Ports 0, 1, 3, 7, 8
Ports A, B, C, D, E,
F
• Output disabled
• Pull-up resistor off
2.5 to 3.6
1
• V =V
(Including output Tr's
off leakage current)
IN SS
Port L
RES
I
I
(2)
IL
V
=V
2.5 to 3.6
2.5 to 3.6
2.5 to 3.6
2.5 to 3.6
1
1
IN SS
(3)
IL
XT1, XT2
• For input port specification
• V =V
IN SS
I
I
(4)
IL
CF1
V
=V
IN SS
15
10
(5)
IL
P87 small signal
input side
V =VBIS0.5V
IN
5.5
1.5
(VBIS: Bias voltage)
Continued on next page.
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17
LC87F7NJ2A
Continued from preceding page.
Specification
typ max
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
unit
DD
High level output
voltage
V
(1)
(2)
(3)
(4)
Ports 0, 1, 32 to 35
Ports 30, 31
I
I
I
I
=0.4mA
2.5 to 3.6
2.5 to 3.6
2.5 to 3.6
V
V
V
0.4
OH
OH
OH
OH
OH
DD
DD
DD
V
V
V
=1.6mA
=0.4mA
=0.4mA
0.4
0.4
OH
OH
OH
Ports 71 to 73
Ports A, B, C
Ports D, E, F
Ports 0, 1, 32 to 35
Ports 30, 31
(PWM function
output mode)
Ports 30, 31
(Port function
output mode)
Ports 7, 8
2.5 to 3.6
V
0.4
DD
Low level output
voltage
V
(1)
I
=1.6mA
OL
OL
2.5 to 3.6
0.4
0.4
V
(2)
I
=5mA
OL
OL
2.5 to 3.6
V
V
V
(3)
(4)
I
I
=1.6mA
=1.6mA
OL
OL
2.5 to 3.6
2.5 to 3.6
0.4
0.4
XT2
Ports A, B, C
Ports D, E, F
S0 to S53
OL
OL
LCD output voltage
regulation
VODLS
• I =0mA
O
• VLCD, 2/3VLCD, 1/3VLCD
2.5 to 3.6
2.5 to 3.6
0
0
±0.2
±0.2
level output
• See Fig. 8.
VODLC
COM0 to COM3
• IO=0mA
• VLCD, 2/3VLCD, 1/2VLCD,
1/3VLCD level output
• See Fig. 8.
LCD bias resistor
RLCD(1)
RLCD(2)
Resistance per
one bias resister
Resistance per
one bias resister
1/2R mode
See Fig. 8.
2.5 to 3.6
2.5 to 3.6
60
See Fig. 8.
30
50
k
Resistance of
Rpu(1)
Ports 0, 1, 3, 7
Ports A, B, C, D, E,
F
V
=0.9V
OH
DD
pull-up MOS Tr.
2.5 to 3.6
18
50
Hysterisis voltage
Pin capacitance
VHYS(1)
VHYS(2)
CP
Ports 1, 7
RES
2.5 to 3.6
2.5 to 3.6
0.1V
0.1V
DD
DD
V
P87 small signal
input side
All pins
• For pins other than that under
test:
V
=V
2.5 to 3.6
2.5 to 3.6
10
pF
IN SS
• f=1MHz
• Ta=25C
Input sensitivity
Vsen
P87 small signal
input side
0.12V
Vpp
DD
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
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18
LC87F7NJ2A
Serial I/O Characteristics at Ta = 40°C to +85°C, V 1 = V 2 = V 3 = 0V, 0.190μs tCYC 200μs
SS SS SS
SIO0 Serial I/O Characteristics (Note 4-1-1) at V
= 2.7 V to 3.6V 0.190μs tCYC 200μs
DD
Specification
typ max
Parameter
Frequency
Symbol
tSCK(1)
Pin/Remarks
SCK0(P12)
Conditions
V
[V]
min
unit
DD
See Fig. 6.
2
1
1
Low level
tSCKL(1)
tSCKH(1)
tSCKHA(1)
pulse width
High level
pulse width
2.5 to 3.6
tCYC
• Continuous data
transmission/reception mode
• See Fig. 6.
4
(Note 4-1-2)
Frequency
tSCK(2)
SCK0(P12)
• CMOS output selected
• See Fig. 6.
4/3
Low level
tSCKL(2)
tSCKH(2)
tSCKHA(2)
1/2
1/2
pulse width
High level
pulse width
tSCK
tCYC
2.5 to 3.6
• Continuous data
transmission/reception mode
• CMOS output selected
• See Fig. 6.
tSCKH(2)
+(10/3)
tCYC
tSCKH(2)
+2tCYC
Data setup time
Data hold time
tsDI(1)
thDI(1)
tdD0(1)
tdD0(2)
tdD0(3)
SB0(P11),
SI0(P11)
• Must be specified with
respect to rising edge of
SIOCLK.
0.03
0.03
2.5 to 3.6
• See Fig. 6.
Output
SO0(P10),
SB0(P11)
• Continuous data
transmission/reception mode
(Note 4-1-3)
(1/3)tCYC
+0.05
delay time
s
• Synchronous 8-bit mode
(Note 4-1-3)
1tCYC
+0.05
2.5 to 3.6
(Note 4-1-3)
(1/3)tCYC
+0.05
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock is
"H" to the first negative edge of the serial clock must be longer than tSCKHA.
Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of
output state change in open drain output mode. See Fig. 6.
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19
LC87F7NJ2A
SIO1 Serial I/O Characteristics (Note 4-2-1)
Specification
Parameter
Frequency
Symbol
tSCK(3)
Pin/Remarks
SCK1(P15)
Conditions
See Fig. 6.
V
[V]
min
typ
max
unit
DD
2
1
1
2
Low level
tSCKL(3)
tSCKH(3)
tSCK(4)
tSCKL(4)
tSCKH(4)
tsDI(2)
2.5 to 3.6
pulse width
High level
pulse width
Frequency
tCYC
SCK1(P15)
• CMOS output selected
• See Fig. 6.
Low level
pulse width
2.5 to 3.6
1/2
1/2
tSCK
High level
pulse width
Data setup time
SB1(P14),
SI1(P14)
• Must be specified with
respect to rising edge of
SIOCLK.
2.5 to 3.6
2.5 to 3.6
0.03
0.03
• See Fig. 6.
Data hold time
thDI(2)
tdD0(4)
Output delay time
SO1(P13),
SB1(P14)
• Must be specified with
respect to falling edge of
SIOCLK.
s
• Must be specified as the
time to the beginning of
output state change in
open drain output mode.
• See Fig. 6.
(1/3)tCYC
+0.05
2.5 to 3.6
Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.
Pulse Input Conditions at Ta = 40°C to +85°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
Specification
typ max
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
unit
DD
High/low
level pulse
width
tPIH(1)
tPIL(1)
INT0(P70),
• Interrupt source flag can be set.
• Event inputs for timer 0 or 1 are
enabled.
INT1(P71),
INT2(P72),
INT4(P30 to P33),
INT5(P34 to P35),
INT6(P30),
2.5 to 3.6
1
INT7(P34)
tPIH(2)
tPIL(2)
tPIH(3)
tPIL(3)
tPIH(4)
tPIL(4)
tPIH(5)
tPIL(5)
tPIH(6)
tPIL(6)
tPIL(7)
INT3(P73) when noise filter
time constant is 1/1
INT3(P73) when noise filter
time constant is 1/32
INT3(P73) when noise filter
time constant is 1/128
MICIN(P87)
• Interrupt source flag can be set.
• Event inputs for timer 0 are enabled.
• Interrupt source flag can be set.
• Event inputs for timer 0 are enabled.
• Interrupt source flag can be set.
• Event inputs for timer 0 are enabled.
Condition that signal is accepted to
small signal detection counter.
Condition that signal is accepted to
remote control receiver circuit.
Resetting is enabled.
tCYC
2.5 to 3.6
2.5 to 3.6
2.5 to 3.6
2.5 to 3.6
2
64
256
1
RMIN(P73)
RES
RMCK
2.5 to 3.6
2.5 to 3.6
4
(Note 5-1)
200
s
Note 5-1: RMCK is an unit for the base clock (40tCYC/50tCYC/Sub-Clock) of remote control receiver circuit.
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20
LC87F7NJ2A
AD Converter Characteristics at V 1 = V 2 = V 3 = 0V
SS
SS
SS
<12bits AD Converter Mode at Ta =30 to +70C>
Specification
typ max
12
Parameter
Resolution
Symbol
Pin/Remarks
AN0(P80) to
Conditions
V
[V]
min
unit
bit
DD
N
2.5 to 3.6
AN7(P87),
AN8(P70),
AN9(P71),
AN10(XT1),
AN11(XT2)
Absolute
accuracy
Conversion
time
ET
(Note 6-1)
2.5 to 3.6
±16
LSB
tCAD
• See Conversion time calculation
formulas.
3.0 to 3.6
2.7 to 3.6
2.5 to 3.6
64
115
230
460
128
256
s
(Note 6-2)
Analog input
voltage range
Analog port
input current
VAIN
V
V
V
SS
DD
IAINH
IAINL
VAIN=V
DD
2.5 to 3.6
2.5 to 3.6
1
A
VAIN=V
SS
1
<8bits AD Converter Mode at Ta =30 to +70C>
Specification
typ max
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
unit
bit
DD
Resolution
N
AN0(P80) to
2.5 to 3.6
8
AN7(P87),
AN8(P70),
AN9(P71),
AN10(XT1),
AN11(XT2)
Absolute
accuracy
Conversion
time
ET
(Note 6-1)
2.5 to 3.6
1.5
LSB
TCAD
• See Conversion time calculation
formulas.
3.0 to 3.6
2.7 to 3.6
2.5 to 3.6
39
79
71
140
280
s
(Note 6-2)
157
Analog input
voltage range
Analog port
input current
VAIN
V
V
V
SS
DD
IAINH
IAINL
VAIN=V
DD
2.5 to 3.6
2.5 to 3.6
1
A
VAIN=V
SS
1
<Conversion time calculation formulas>
12bits AD Converter Mode: tCAD(Conversion time)=((52/(division ratio)) + 2) (1/3) tCYC
8bits AD Converter Mode: tCAD(Conversion time)=((32/(division ratio)) + 2) (1/3) tCYC
Note 6-1: The quantization error (±1/2LSB) must be excluded from the absolute accuracy. The absolute accuracy must
be measured in the microcontroller's state in which no I/O operations occur at the pins adjacent to the analog
input channel.
Note 6-2: The conversion time refers to the period from the time an instruction for starting a conversion process till the
time the conversion results register(s) are loaded with a complete digital conversion value corresponding to
the analog input value.
The conversion time is 2 times the normal-time conversion time when:
• The first AD conversion is performed in the 12-bit AD conversion mode after a system reset.
• The first AD conversion is performed after the AD conversion mode is switched from 8-bit to 12-bit
conversion mode.
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21
LC87F7NJ2A
Consumption Current Characteristics at Ta = 40°C to +85°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
Specification
Pin/
Parameter
Symbol
Conditions
Remarks
V
[V]
min
typ
max
unit
DD
Normal mode
consumption
current
IDDOP(1)
V
1
• FmCF=18MHz ceramic oscillation mode
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 12MHz side
• Internal RC oscillation stopped.
DD
=V
=V
2
3
DD
DD
6.1
15.6
2.7 to 3.6
(Note 7-1)
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
IDDOP(2)
• FmCF=8MHz ceramic oscillation mode
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 12MHz side
• Internal RC oscillation stopped.
3.9
0.4
4.3
8.8
1.7
2.5 to 3.6
2.5 to 3.6
2.5 to 3.6
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
IDDOP(3)
IDDOP(4)
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to internal RC oscillation
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
mA
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
• Internal RC oscillation stopped.
12.0
• System clock set to 10MHz with
frequency variable RC oscillation
• 1/1 frequency division ratio
IDDOP(5)
IDDOP(6)
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
• Internal RC oscillation stopped.
2.5 to 3.6
2.1
6.6
• System clock set to 4MHz with
frequency variable RC oscillation
• 1/1 frequency division ratio
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 32.768kHz side
• Internal RC oscillation stopped.
2.5 to 3.6
19.3
73
A
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors.
Continued on next page.
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22
LC87F7NJ2A
Continued from preceding page.
Specification
Pin/
Parameter
Symbol
Conditions
Remarks
V
[V]
min
typ
max
unit
DD
HALT mode
consumption
current
IDDHALT(1)
V
1
• HALT mode
DD
=V
=V
2
3
• FmCF=18MHz ceramic oscillation mode
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 12MHz side
• Internal RC oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
DD
DD
2.7
6.8
(Note 7-1)
2.7 to 3.6
IDDHALT(2)
• HALT mode
• FmCF=8MHz ceramic oscillation mode
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 12MHz side
• Internal RC oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
1.4
0.2
1.6
3.1
0.75
4.6
2.5 to 3.6
2.5 to 3.6
2.5 to 3.6
IDDHALT(3)
IDDHALT(4)
• HALT mode
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to internal RC oscillation
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
mA
• HALT mode
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
• Internal RC oscillation stopped.
• System clock set to 10MHz with
frequency variable RC oscillation
• 1/1 frequency division ratio
IDDHALT(5)
• HALT mode
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
• Internal RC oscillation stopped.
• System clock set to 4MHz with
frequency variable RC oscillation
• 1/1 frequency division ratio
2.5 to 3.6
0.7
1.75
IDDHALT(6)
• HALT mode
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 32.768kHz side
• Internal RC oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
2.5 to 3.6
12.4
54.9
A
HOLD mode
consumption
current
IDDHOLD(1)
IDDHOLD(2)
V
1
• HOLD mode
DD
• CF1=V
DD
or open (External clock mode)
2.5 to 3.6
2.5 to 3.6
0.08
18.4
34.4
Timer HOLD
mode
• Timer HOLD mode
• CF1=V or open (External clock mode)
DD
• FmX’tal=32.768kHz crystal oscillation mode
10.14
consumption
current
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors.
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23
LC87F7NJ2A
F-ROM Write Characteristics at Ta = +10°C to +55°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
Specification
typ max
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
unit
mA
DD
Onboard
IDDFW(1)
V
1
• Without CPU current
DD
programming
current
3.0 to 3.6
7
11
Programming
time
tFW(1)
tFW(2)
• 2K-byte erase operation
• 2K-byte writing operation
3.0 to 3.6
3.0 to 3.6
12
35
15
45
ms
s
UART (Full Duplex) Operating Conditions at Ta = +40 to +85°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
Specification
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
16/3
typ
max
8192/3
unit
DD
Transfer rate
UBR
UTX(S32),
URX(S33)
2.5 to 3.6
tCYC
Data length : 7/8/9 bits (LSB first)
Stop bits : 1 bit (2-bit in continuous data transmission)
Parity bits : None
Example of 8-bit Data Transmission Mode Processing (Transmit Data=55H)
Start bit
Stop bit
End of
transmission
Start of
transmission
Transmit data (LSB first)
UBR
Example of 8-bit Data Reception Mode Processing (Receive Data=55H)
Stop bit
Start bit
End of
reception
Start of
reception
Receive data (LSB first)
UBR
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24
LC87F7NJ2A
Characteristics of a Sample Main System Clock Oscillation Circuit
Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a Our
designated oscillation characteristics evaluation board and external components with circuit constant values with
which the oscillator vendor confirmed normal and stable oscillation.
Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator
Oscillation
Operating
Circuit Constant
Stabilization
Time
Nominal
Vendor
Name
Voltage
Range
[V]
Oscillator Name
Remarks
Frequency
C1
C2
Rf1
Rd1
typ
max
[ms]
[pF]
[pF]
[]
[]
[ms]
Values shown in parentheses
are capacitance included
in the oscillator
CSTCE18M0V51-R0
CSTLS18M0X51-B0
CSTCE10M00G52-R0
CSTLS10M00G53-B0
CSTCE8M00G52-R0
CSTLS8M00G53-B0
(5)
(5)
(5)
(5)
OPEN
OPEN
OPEN
OPEN
OPEN
OPEN
150
0
2.7 to 3.6
2.7 to 3.6
2.5 to 3.6
2.5 to 3.6
2.5 to 3.6
2.5 to 3.6
0.05
0.11
0.05
0.05
0.05
0.05
0.15
0.33
0.15
0.15
0.15
0.15
18MHz
10MHz
8MHz
MURATA
MURATA
MURATA
Values shown in parentheses
are capacitance included
in the oscillator
(10)
(15)
(10)
(15)
(10)
(15)
(10)
(15)
680
1.5k
680
1.5k
Values shown in parentheses
are capacitance included
in the oscillator
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after V
goes above the operating voltage lower limit (see Figure 4).
DD
Characteristics of a Sample Subsystem Clock Oscillator Circuit
Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a Our
designated oscillation characteristics evaluation board and external components with circuit constant values with
which the oscillator vendor confirmed normal and stable oscillation.
Table 2 Characteristics of a Sample Subsystem Clock Oscillation Circuit with a Crystal Oscillation
Oscillation
Operating
Voltage
Range
[V]
Circuit Constant
Stabilization Time
Nominal
Oscillator
Name
Vendor Name
Remarks
Frequency
C3
C4
Rf2
Rd2
typ
[s]
max
[s]
[pF]
[pF]
[]
[]
EPSON
32.768kHz
MC-306
9
9
Open
330k
2.5 to 3.6
1.0
3.0
CL=7.0pF
TOYOCOM
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the
instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the
oscillation to get stabilized after the HOLD mode is reset (see Fig. 4).
Caution: The components that are involved in oscillation should be placed as close to the IC and to one another as
possible because they are vulnerable to the influences of the circuit pattern.
XT1
XT2
CF1
CF2
Rf2
Rf1
CF
Rd2
C4
Rd1
C2
C3
C1
X’tal
Figure 1 CF Oscillator Circuit
Figure 2 XT Oscillator Circuit
0.5V
DD
Figure 3 AC Timing Measurement Point
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25
LC87F7NJ2A
V
DD
Operating V
lower limit
0V
DD
Power supply
Reset time
RES
Internal RC
oscillation
tmsCF
CF1, CF2
tmsX’tal
XT1, XT2
Operating mode
Unpredictable
Reset
Instruction execution
Reset Time and Oscillation Stabilization Time
HOLD reset signal
absent
HOLD reset signal
HOLD reset signal VALID
Internal RC oscillation
tmsCF
CF1, CF2
tmsX’tal
XT1, XT2
State
HOLD
HALT
HOLD Reset Signal and Oscillation Stabilization Time
Figure 4 Oscillation Stabilization Times
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26
LC87F7NJ2A
V
DD
R
C
Note :
Determine the value of C
is present for a period of 200s after the supply voltage goes
beyond the lower limit of the IC's operating voltage.
RES
and R
so that the reset signal
RES
RES
RES
RES
Figure 5 Reset Circuit
SIOCLK:
DATAIN:
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
DATAOUT:
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DO8
Data RAM
transfer period
(SIO0 only)
tSCK
tSCKH
thDI
tSCKL
SIOCLK:
DATAIN:
tsDI
tdDO
DATAOUT:
Data RAM
transfer period
(SIO0 only)
tSCKL
tSCKHA
SIOCLK:
DATAIN:
tsDI
thDI
tdDO
DATAOUT:
Figure 6 Serial I/O Waveforms
tPIL
tPIH
Figure 7 Pulse Input Timing Signal Waveform
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27
LC87F7NJ2A
V
DD
SW: ON/OFF (programmable)
RLCD
RLCD
RLCD
RLCD
SW: On when VLCD=V
DD
VLCD
RLCD
RLCD
RLCD
RLCD
RLCD
RLCD
GND
2/3 VLCD
1/2 VLCD
1/3 VLCD
Figure 8 LCD bias resistor
ORDERING INFORMATION
Device
Package
Shipping (Qty / Packing)
50 / Tray Foam
QIP100E(1420)
(Pb-Free / Halogen Free)
LC87F7NC8AUEJ-2H
QIP100E(1420)
(Pb-Free / Halogen Free)
LC87F7NC8AVUEJ-2H
50 / Tray Foam
ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiariesin the United States
and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of
SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without
further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitabilityof its products for any particular purpose,
nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including
without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can
and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are
not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicationsintended to support or
sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers,
employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was
negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all
applicable copyright laws and is not for resale in any manner.
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