LC87F83C8A [SANYO]
FROM 128K byte, RAM 6K byte on-chip 8-bit ETR Microcontroller; 从128K字节， RAM 6K字节片上8位微控制器ETR
| 型号： | LC87F83C8A |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | FROM 128K byte, RAM 6K byte on-chip 8-bit ETR Microcontroller |
| 文件： | 总31页 (文件大小：250K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : ENA1780
LC87F83C8A/AU
LC87F8396A/AU
LC87F8364A/AU
CMOS IC
FROM 128K byte, RAM 6K byte on-chip
8-bit ETR Microcontroller
Overview
The LC87F83C8A/AU/96A/AU/64A/AU is an 8-bit ETR microcomputer that, centered around a CPU running at a
minimum bus cycle time of 74.04 ns, integrate on a single chip a number of hardware features such as 128K-bytes of
flash ROM maximum (onboard rewritable), 6K-bytes of RAM maximum, Onchip debugging, direct control of
necessary CD mechanism and CD-DSP for car audio, in the radio reception, the on-chip high-performance PLL circuit
provides a high-speed Lock-Up circuit to search for alternative frequency of RDS in a short time, the ability to control
the C/N characteristics of a local oscillator, and the high S/N through the direct PLL configuration, two sophisticated
16-bit timers/counters (may be divided into 8-bit timers), four 8-bit timers with a prescaler, a base timer serving as a
time-of-day clock, two synchronous SIO ports (with automatic block transmission/reception capabilities), an
asynchronous/synchronous SIO port, two UART ports (full duplex), four 12-bit PWM channels, an 8-bit 10-channel
AD converter, a high-speed clock counter, a system clock frequency divider, and a 29-source 10-vector interrupt
feature.
ROM for each model/Table RAM capacity
Type No.
Flash ROM (byte)
RAM (byte)
LC87F8364A/AU
LC87F8396A/AU
LC87F83C8A/AU
64K
96K
4K
6K
6K
128K
Features
■Flash ROM
• Single 5V power supply, on-board writeable
• Block erase in 128 byte units
* This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by
SANYO Semiconductor Co., Ltd.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer
's products or
equipment.
Ver.1.03
20211HKPC 20100603-S00007, S00009, S00010, S00012, S00013, S00014 No.A1780-1/31
LC87F83C8A/C8AU/96A/96AU/64A/64AU
■Minimum Bus Cycle Time
• 74.04ns (13.5MHz)
Note: Bus cycle time indicates the speed to read ROM.
■Minimum Instruction Cycle Time (tCYC)
• 222ns (13.5MHz)
■Ports
• Normal withstand voltage I/O ports
Ports whose I/O direction can be designated in 1 bit units: 57 (P1n, P2n, P30 to P35, P70 to P73, P8n, PBn, PCn,
SI2Pm, PWM0, PWM1, XT2, n=0 to 7, m=0 to 3)
Ports whose I/O direction can be designated in 2 bit units: 16 (PEn, PFn n=0 to 7)
Ports whose I/O direction can be designated in 4 bit units: 8 (P0n n=0 to 7)
• Normal withstand voltage input ports:
• Main charge pump output ports:
• Sub charge pump output ports:
• AM local oscillator input ports:
• FM local oscillator input ports:
• High-speed, universal counter input ports:
• Universal counter input ports:
• Internal low voltage output ports:
• Dedicated oscillator ports:
• Reset pin:
1 (XT1)
1 (EO)
1 (SUBPD)
1 (AMIN)
1 (FMIN)
1 (HCTR)
1 (LCTR)
1 (VREG)
2 (CF1, CF2)
1 (
RES
)
• Digital power pins:
6 (V n, V n n=1, 2, 4)
SS DD
• Analogue power pins:
2 (AV n, AV )
SS DD
■Timers
• Timer 0: 16-bit programmable timer/counter with capture register
Mode 0: 8-bit programmable timer with an 8-bit programmable prescaler (with two 8-bit capture registers)
× 2 channels
Mode 1: 8-bit programmable timer with an 8-bit programmable prescaler (with two 8-bit capture registers)
+ 8-bit programmable counter (with two 8-bit capture registers)
Mode 2: 16-bit programmable timer with an 8-bit programmable prescaler
(with two 16-bit capture registers)
Mode 3: 16-bit programmable counter (with 2 16-bit capture registers)
• Timer 1: 16-bit programmable timer/counter that support PWM/ toggle output
Mode 0: 8-bit programmable timer with an 8-bit prescaler (with toggle outputs)
+ 8-bit programmable timer/counter (with toggle outputs)
Mode 1: 8-bit PWM with an 8-bit prescaler × 2 channels
Mode 2: 16-bit programmable timer/counter with an 8-bit prescaler (with toggle outputs)
(toggle outputs also from the lower-order 8 bits)
Mode 3: 16-bit programmable timer with an 8-bit prescaler (with toggle outputs)
(The lower-order 8 bits can be used as PWM.)
• Timer 4: 8-bit programmable timer with a 6-bit prescaler
• Timer 5: 8-bit programmable timer with a 6-bit prescaler
• Timer 6: 8-bit programmable timer with a 6-bit prescaler (with toggle outputs)
• Timer 7: 8-bit programmable timer with a 6-bit prescaler (with toggle outputs)
• Base timer
1) The clock is selectable from the subclock (32.768kHz crystal oscillator), cycle clock (tCYC), and timer 0
prescaler output.
2) Interrupts programmable in 5 different time schemes.
■High Speed Clock Counter
1) Can count clocks with a maximum clock rate of 20MHz (When High-speed clock counter is used, timer 0
cannot be used).
2) Can generate output real time.
No.A1780-2/31
LC87F83C8A/C8AU/96A/96AU/64A/64AU
■SIO: 3 channels
• SIO 0: 8 bit synchronous serial interface
1) LSB first/MSB first mode selectable
2) Built-in 8-bit baudrate generator (4/3 to 512/3 tCYC transfer clock cycle)
3) Automatic continuous data transmission (1 to 256 bits)
• SIO 1: 8 bit asynchronous/synchronous serial interface
Mode 0: Synchronous 8-bit serial I/O (2 to or 3 to wire configuration, 2 to 512 tCYC transfer clocks)
Mode 1: Asynchronous serial I/O (Half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates)
Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks)
Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect)
• SIO2: 8 bit synchronous serial interface
1) LSB first mode
2) Built-in 3-bit baudrate generator (4/3 to 512/3 tCYC transfer clock cycle)
3) Automatic continuous data transmission (1 to 32 bytes)
■UART: 2 channels
1) Full duplex
2) 7/8/9 bit data bits selectable
3) 1 stop bit (2 bits in continuous transmission mode)
4) Built-in 8-bit baudrate generator (with baudrates of 16/3 to 8192/3 tCYC)
■AD Converter: 8 bits × 10 channels
■PWM: Multifrequency 12-bit PWM × 4 channels
■Remote Control Receiver Noise Filtering Function (sharing pins with P73, INT3, and T0IN)
1) Noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC
2) The noise filtering function is available for the INT3, T0IN, or T0HCP signal at P73. When P73 is read with an
instruction, the signal level at that pin is read regardless of the availability of the noise filtering function.
■Watchdog Timer
• External RC watchdog timer
• Interrupt and reset signals selectable
■Interrupts
• 29 sources, 10 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of
the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level
takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector
address takes precedence.
No.
1
Vector Address
00003H
Level
X or L
X or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
Interrupt Source
INT0
2
0000BH
00013H
INT1
3
INT2/T0L/INT4
4
0001BH
00023H
INT3/INT5/Base timer (BT0, 1)
T0H/INT6
5
6
0002BH
00033H
T1L/T1H/INT7
7
SIO0/UART1 receive/UART2 receive
SIO1/SIO2/UART1 transmit/UART2 transmit
ADC/T6/T7/PWM4, PWM5
Port 0/T4/T5/PWM0, PWM1
8
0003BH
00043H
9
10
0004BH
• Priority levels X > H > L
• Of interrupts of the same level, the one with the smallest vector address takes precedence.
• The Base timers are two interrupt sources of BT0 and BT1, it is one interrupt source by PWM0 and 1, it is one
interrupt source by PWM4 and 5.
No.A1780-3/31
LC87F83C8A/C8AU/96A/96AU/64A/64AU
■Subroutine Stack Levels
• 3072 levels maximum (1/2 of capacity of RAM, the stack is allocated in RAM.)
■High-speed Multiplication/Division Instructions
• 16 bits × 8 bits
• 24 bits × 16 bits
• 16 bits ÷ 8 bits
• 24 bits ÷ 16 bits
(5 tCYC execution time)
(12 tCYC execution time)
(8 tCYC execution time)
(12 tCYC execution time)
■Oscillation Circuits and PLL
• RC oscillator circuit (internal):
• Main XT crystal oscillator circuit:
• Sub XT crystal oscillator circuit:
For system clock
For system clock with internal Rf, Rd
For time-of-day clock, for low-speed system clock with internal Rf
and external Rd
• Multifrequency RC oscillator circuit (internal): For system clock
• PLL circuit (internal):
For AM/FM tuner
■System Clock Divider Function
• Can run on low current.
• The minimum instruction cycle selectable from 222ns, 444ns, 888ns, 1.78μs, 3.55μs, 7.10μs, 14.2μs, 28.4μs,
and 56.8μs.
■PLL Block
• Twelve reference frequencies when main XT is 13.5MHz: 1kHz, 3kHz, 3.125kHz, 5kHz, 6.25kHz, 9kHz, 10kHz,
12.5kHz, 25kHz, 30kHz, 50kHz, and 100kHz
• Range of input frequency
1) AMIN: 0.5 to 40MHz
2) FMIN: 10 to 150MHz
3) HCTR: 0.4 to 12MHz
4) LCTR: 100 to 500kHz
• Supports dead zone control.
• Built-in unlock detection circuit.
■Universal Counter
• This 20-bit counter can be used for frequency measurement.
■Standby Function
• HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Oscillation is not halted automatically.
2) Canceled by system reset, detection VDET0 or occurrence of interrupt.
• HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
1) The main XT crystal oscillators, RC, and sub XT crystal oscillators automatically stop operation.
2) There are four ways of resetting the HOLD mode.
(1) Setting the Reset pin to the lower level.
(2) Voltage descent detection (VDET1)
(3) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level.
(4) Having an interrupt source established at port 0.
• X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer.
1) The main XT crystal oscillators, and RC oscillators automatically stop operation.
2) The state of crystal oscillation established when the HOLD mode is entered is retained.
3) There are five ways of resetting the X'tal HOLD mode.
(1) Setting the Reset pin to the low level.
(2) Voltage descent detection (VDET0)
(3) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level.
(4) Having an interrupt source established at port 0.
(5) Having an interrupt source established in the base timer circuit.
No.A1780-4/31
LC87F83C8A/C8AU/96A/96AU/64A/64AU
■Reset
• External reset
• Voltage descent detection (VDET0, VDET1) reset circuit (internal)
■Onchip Debugging Function
• Permits software debugging with the test device installed on the target board.
■Shipping Form
• QIP100E (Lead Free Product)
■Flash ROM Version
• LC87F83C8A/96A/64A
• LC87F83C8AU/96AU/64AU (User writing)
No.A1780-5/31
LC87F83C8A/C8AU/96A/96AU/64A/64AU
Absolute Maximum Ratings at Ta = 25°C, V 1 = V 2 = V 4 = AV = 0V
SS
SS
SS
SS
Specification
typ max
Parameter
Symbol
Pins/Remarks
Conditions
V
[V]
min
-0.3
unit
DD
Maximum Supply
voltage
V
max
V
V
1, V 2,
V
1=V 2=V
4
DD
DD
DD
DD DD DD
+6.5
4, AV
DD DD
=AV
DD
Input voltage
V (1)
CF1, XT1,
I
AMIN, FMIN,
HCTR, LCTR
Ports 0, 1, 2
-0.3
-0.3
V
+0.3
DD
Input/Output
voltage
V
(1)
IO
V
Ports 3, 7, 8
Ports B, C, E, F
SI2P0 to SI2P3
PWM0, PWM1, XT2
EO, SUBPD
V
V
+0.3
+0.3
DD
Output voltage
V
(1)
-0.3
-10
O
DD
Peak output
current
IOPH(1)
Ports 0, 1, 2, 3
Ports 71 to 73
Ports B, C, E, F
SI2P0 to SI2P3
PWM0, PWM1
CMOS output select per 1
application pin
IOPH(2)
IOPH(3)
IOMH(1)
Per 1 application pin.
Per 1 application pin.
-20
-5
EO, SUBPD
Average
Ports 0, 1, 2, 3
Ports 71 to 73
Ports B, C, E, F
SI2P0 to SI2P3
PWM0, PWM1
CMOS output select per 1
application pin
output current
(Note 1-1)
-7.5
IOMH(2)
IOMH(3)
ΣIOAH(1)
ΣIOAH(2)
Per 1 application pin.
-15
-3
EO, SUBPD
P71 to P73
Per 1 application pin.
Total output
current
Total of all applicable pins
Total of all applicable pins
-25
mA
PWM0, PWM1
SI2P0 to SI2P3
Ports 0
-25
-25
ΣIOAH(3)
ΣIOAH(4)
Total of all applicable pins
Total of all applicable pins
Port 0
PWM0, PWM1
SI2P0 to SI2P3
Ports 2, 3, B
-45
ΣIOAH(5)
ΣIOAH(6)
ΣIOAH(7)
ΣIOAH(8)
ΣIOAH(9)
ΣIOAH(10)
ΣIOAH(11)
Total of all applicable pins
Total of all applicable pins
Total of all applicable pins
Total of all applicable pins
Total of all applicable pins
Total of all applicable pins
Total of all applicable pins
-25
-25
-45
-25
-25
-45
-10
Ports C
Ports 2, 3, B, C
Ports F
Ports 1, E
Ports 1, E, F
EO, SUBPD
Note 1-1: Average output current is average of current in 100ms interval.
Continued on next page.
No.A1780-6/31
LC87F83C8A/C8AU/96A/96AU/64A/64AU
Continued from preceding page.
Specification
typ max
Parameter
Symbol
IOPL(1)
Pins/Remarks
Conditions
V
[V]
min
unit
DD
Peak output
current
Ports 0, 1, 2, 3, 8
Ports B, C, E, F
SI2P0 to SI2P3
XT2
Per 1 application pin.
10
IOPL(2)
IOPL(3)
IOML(1)
PWM0, PWM1
Per 1 application pin.
Per 1 application pin.
Per 1 application pin.
20
5
EO, SUBPD
Average
Ports 0, 1, 2, 3, 7
Ports 8, B, C, E, F
SI2P0 to SI2P3
XT2
output current
(Note 1-1)
7.5
IOML(2)
IOML(3)
ΣIOAL(1)
ΣIOAL(2)
ΣIOAL(3)
ΣIOAL(4)
PWM0, PWM1
Per 1 application pin.
20
5
EO, SUBPD
Port 7, XT2
Port 8
Per 1 application pin.
Total output
current
Total of all applicable pins
Total of all applicable pins
Total of all applicable pins
Total of all applicable pins
25
25
45
mA
Ports 7, 8, XT2
PWM0, PWM1
SI2P0 to SI2P3
Port 0
25
25
ΣIOAL(5)
ΣIOAL(6)
Total of all applicable pins
Total of all applicable pins
Port 0
PWM0, PWM1
SI2P0 to SI2P3
Ports 2, 3, B
45
ΣIOAL(7)
ΣIOAL(8)
ΣIOAL(9)
ΣIOAL(10)
ΣIOAL(11)
ΣIOAL(12)
ΣIOAL(13)
Pd max
Total of all applicable pins
Total of all applicable pins
Total of all applicable pins
Total of all applicable pins
Total of all applicable pins
Total of all applicable pins
Total of all applicable pins
Ta = -40 to +85°C
25
25
45
25
25
45
10
Ports C
Ports 2, 3, B, C
Port F
Ports 1, E
Ports 1, E, F
EO, SUBPD
QIP100E
Maximum power
consumption
Operating
400
+85
mW
°C
Topr
Tstg
-40
temperature range
Storage
-45
+125
°C
temperature range
Note 1-1: Average output current is average of current in 100ms interval.
No.A1780-7/31
LC87F83C8A/C8AU/96A/96AU/64A/64AU
Recommended operating range at Ta = -40°C to +85°C, V 1 = V 2 = V 4 = AV = 0V
SS SS SS SS
Specification
typ max
5.0
Parameter
Symbol
Pins/Remarks
Conditions
V
[V]
min
unit
DD
Operating
V
(1)
V
1=V 2=V
4
4
PLL operation
CPU operation
4.5
5.5
5.5
DD
DD
DD
DD
DD
supply voltage
=AV
DD
3.0
1.0
Memory sustaining
supply voltage
High level input
voltage
VHD
V
1=V 2=V
DD
RAM and register contents
in HOLD mode.
DD
5.5
=AV
DD
Ports 1, 2
V
(1)
IH
SI2P0 to 3
0.35V
DD
P71 to P73
3.0 to 5.5
3.0 to 5.5
V
DD
+0.7
P70 port input/
interrupt side
Ports 0, 3, 8
Ports B, C, E, F
PWM0, PWM1
V
(2)
IH
0.3V
DD
V
V
DD
+0.7
V
V
V
V
(3)
(4)
Port70 Watchdog timer
side
IH
3.0 to 5.5
3.0 to 5.5
4.0 to 5.5
0.9V
DD
DD
V
RES
XT1, XT2,
When XT1 and XT2
IH
0.75V
V
DD
DD
general purpose input
Low level input
voltage
(1)
(2)
Ports 1, 2
SI2P0 to 3
0.1V
IL
DD
V
SS
SS
+0.4
P71 to P73
IL
P70 port input/
interrupt side
Ports 0, 3, 8
3.0 to 4.0
V
0.2V
DD
DD
V
(3)
0.15V
IL
4.0 to 5.5
3.0 to 4.0
3.0 to 5.5
V
V
V
SS
SS
SS
Ports B, C, E, F
PWM0, PWM1
+0.4
V
V
(4)
(5)
0.2V
IL
DD
DD
Port70 Watchdog timer
side
0.8V
IL
-1.0
RES
V
V
(6)
(1)
XT1, XT2,
When XT1 and XT2
general purpose input
Excluding CF ability
setting=“00”
IL
3.0 to 5.5
4.5 to 5.5
V
0.25V
SS
DD
1.5
Input amplitude
Input frequency
FMIN, AMIN,
IN
0.04
HCTR, LCTR
Vrms
MHz
V
V
(2)
(3)
FMIN, AMIN, HCTR
CF ability setting=“00”
4.5 to 5.5
4.5 to 5.5
4.5 to 5.5
4.5 to 5.5
4.5 to 5.5
4.5 to 5.5
4.5 to 5.5
4.5 to 5.5
4.5 to 5.5
0.07
0.04
10
1.5
1.5
150
50
IN
FMIN, LCTR
CF ability setting=“00”
IN
FIN(1)
FIN(2)
FIN(3)
FIN(4)
FIN(5)
FIN(6)
FIN(7)
tCYC
FMIN: V (1)
IN
FMIN: V (2)
IN
10
FMIN: V (3)
IN
50
150
40
AMIN(H): V (1) V (2)
2
IN
IN
AMIN(L): V (1) V (2)
IN IN
0.5
0.4
100
10
HCTR: V (1) V (2)
IN IN
12
LCTR: V (1) V (3)
IN IN
500
kHz
Instruction cycle
time (Note 2-1)
Oscillation
3.0 to 5.5
0.222
μs
FmCF(1)
FmRC
CF1, CF2
13.5MHz crystal oscillation.
Internal RC oscillation
3.0 to 5.5
3.0 to 5.5
13.5
1.0
frequency range
0.3
2.0
MHz
FmMRC
Frequency variable RC
oscillation source
oscillation
3.0 to 5.5
16
FsX’tal
XT1, XT2
32.768kHz crystal
oscillation.
3.0 to 5.5
32.768
kHz
Note 2-1: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at
a division ratio of 1/2.
No.A1780-8/31
LC87F83C8A/C8AU/96A/96AU/64A/64AU
Electrical Characteristics at Ta = -40°C to +85°C, V 1 = V 2 = V 4 = AV = 0V
SS
SS
SS
SS
Specification
Parameter
Symbol
Pins/Remarks
Conditions
V
[V]
min
typ
max
unit
DD
High level input
curre
I
(1)
Ports 0, 1, 2
Ports 3, 7, 8
Ports B, C, E, F
SI2P0 to SI2P3
RES
Output disable
Pull-up resistor OFF
=V
IH
V
IN DD
3.0 to 5.5
1
(including the off-leak current of
the output Tr.)
PWM0, PWM1
XT1, XT2
I
(2)
Using as an input port
IH
3.0 to 5.5
3.0 to 5.5
4.5 to 5.5
1
15
30
V
V
=V
IN DD
I
I
(3)
(4)
CF1
=V
1
5
IH
IN DD
FMIN, AMIN,
HCTR, LCTR
Ports 0, 1, 2
Ports 3, 7, 8
Ports B, C, E, F
SI2P0 to SI2P3
RES
V
=V
IH
IN DD
μA
Low level input
current
I
(1)
Output disable
IL
IL
Pull-up resistor OFF
V
=V
IN DD
3.0 to 5.5
-1
-1
(including the off-leak current of
the output Tr.)
PWM0, PWM1
XT1, XT2
I
(2)
Using as an input port
3.0 to 5.5
3.0 to 5.5
4.5 to 5.5
V
V
=V
IN SS
I
I
(3)
(4)
CF1
=V
-15
-30
-5
-1
IL
IN SS
FMIN, AMIN,
V
=V
IL
IN SS
HCTR, LCTR
High level output
voltage
V
V
(1)
Ports 0, 1, 2, 3
Ports B, C, E, F
Ports 71, 72, 73
SI2P0 to SI2P3
PWM0, PWM1
P30, P31(PWM4,
5 output mode)
EO, SUBPD
I
=-1.0mA
OH
OH
4.5 to 5.5
V
-1
DD
(2)
I
=-0.4mA
OH
OH
3.0 to 5.5
4.5 to 5.5
3.0 to 5.5
4.5 to 5.5
V
V
V
-0.4
-1.5
-0.4
-1
DD
V
V
(3)
(4)
I
I
=-10mA
=-1.6mA
OH
OH
DD
OH
OH
DD
V
V
V
(5)
I
I
=-500μA
OH
OH
DD
V
Low level output
voltage
(1)
Ports 0, 1, 2, 3
Ports B, C, E, F
Ports 71, 72, 73
SI2P0 to SI2P3
PWM0, PWM1
=1.0mA
OL
OL
4.5 to 5.5
3.0 to 5.5
1.0
0.4
V
(2)
I
=0.4mA
OL
OL
V
V
V
V
(3)
(4)
(5)
(6)
I
I
I
I
=10mA
=1.6mA
=1.6mA
=500μA
=0.9V
4.5 to 5.5
3.0 to 5.5
3.0 to 5.5
4.5 to 5.5
4.5 to 5.5
1.5
0.4
0.4
1.0
80
OL
OL
OL
OL
OL
OL
OL
OL
Ports 70, 8, XT2
EO, SUBPD
Pull-up resistation
Hysteresis voltage
Pin capacitance
Rpu(1)
Rpu(2)
Ports 0, 1, 2, 3
Port 7
V
OH
15
15
35
35
DD
kΩ
3.0 to 5.5
150
Ports B, C, E, F
RES
VHYS
Ports 1, 2, 7
SI2P0 to SI2P3
All pins
3.0 to 5.5
0.1V
V
DD
CP
• For pins other than that under
test: V =V
IN SS
• f=1MHz
3.0 to 5.5
10
pF
V
• Ta=25°C
Power down
VDET0
VDET1
V
1
• Excluding the HOLD mode
3.0
1.1
3.3
1.6
3.6
2.1
DD
detection voltage
• HOLD mode
No.A1780-9/31
LC87F83C8A/C8AU/96A/96AU/64A/64AU
Serial I/O Characteristics at Ta = -40°C to +85°C, V 1 = V 2 = V 4 = AV = 0V
SS
SS
SS
SS
1. SIO0 Serial I/O Characteristics (Note 4-1-1)
Specification
typ max
Pins/
Parameter
Frequency
Symbol
tSCK(1)
Conditions
Remarks
V
[V]
min
unit
DD
SCK0(P12)
• See Fig. 2.
2
1
1
Low level
tSCKL(1)
pulse width
High level
pulse width
tSCKH(1)
tSCKHA(1a)
• Continuous data
transmission/reception mode
• SIO2 is not in use simultaneous.
• See Fig. 2.
3.0 to 5.5
4
tCYC
• (Note 4-1-2)
tSCKHA(1b)
• Continuous data
transmission/reception mode
• SIO2 is in use simultaneous.
• See Fig. 2.
6
• (Note 4-1-2)
Frequency
tSCK(2)
SCK0(P12)
• CMOS output selected.
• See Fig. 2.
4/3
Low level
tSCKL(2)
tSCKH(2)
tSCKHA(2a)
1/2
1/2
pulse width
High level
pulse width
tSCK
• Continuous data
transmission/reception mode
• SIO2 is not in use simultaneous.
• CMOS output selected.
• See Fig. 2.
3.0 to 5.5
tSCKH(2)
+2tCYC
tSCKH(2)
+(10/3)tCYC
tCYC
tSCKHA(2b)
• Continuous data
transmission/reception mode
• SIO2 is in use simultaneous.
• CMOS output selected.
• See Fig. 2.
tSCKH(2)
+2tCYC
tSCKH(2)
+(16/3)tCYC
Data setup time
Data hold time
tsDI(1)
thDI(1)
tdD0(1)
SI0(P11),
SB0(P11)
• Must be specified with respect to
rising edge of SIOCLK
• See fig. 2.
0.03
0.03
3.0 to 5.5
Output
SI0(P11),
SB0(P11)
• Continuous data
transmission/reception mode
• (Note 4-1-3)
(1/3)tCYC
+0.05
delay time
μs
tdD0(2)
tdD0(3)
• Synchronous 8-bit mode.
• (Note 4-1-3)
1tCYC
+0.05
3.0 to 5.5
• (Note 4-1-3)
(1/3)tCYC
+0.05
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock is
"H" to the first negative edge of the serial clock must be longer than tSCKHA.
Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of
output state change in open drain output mode. See Fig. 2.
No.A1780-10/31
LC87F83C8A/C8AU/96A/96AU/64A/64AU
2. SIO1 Serial I/O Characteristics (Note 4-2-1)
Specification
typ max
Pins/
Parameter
Frequency
Symbol
tSCK(3)
Conditions
• See Fig. 2.
Remarks
V
[V]
min
unit
DD
SCK1(P15)
2
1
1
2
Low level
tSCKL(3)
tSCKH(3)
tSCK(4)
tSCKL(4)
tSCKH(4)
tsDI(2)
3.0 to 5.5
3.0 to 5.5
3.0 to 5.5
pulse width
High level
pulse width
Frequency
tCYC
SCK1(P15)
• CMOS output selected.
• See Fig. 2.
Low level
pulse width
1/2
1/2
tSCK
High level
pulse width
Data setup time
SI1(P14),
SB1(P14)
• Must be specified with respect to
rising edge of SIOCLK
• See fig. 2.
0.03
0.03
Data hold time
thDI(2)
tdD0(4)
μs
Output
SO1(P13),
SB1(P14)
• Must be specified with respect to
falling edge of SIOCLK
• Must be specified as the time to
the beginning of output state
change in open drain output
mode.
delay time
(1/3)tCYC
+0.05
3.0 to 5.5
• See Fig. 2.
Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.
No.A1780-11/31
LC87F83C8A/C8AU/96A/96AU/64A/64AU
3. SIO2 Serial I/O Characteristics (Note 4-3-1)
Specification
typ max
Pins/
Parameter
Frequency
Symbol
tSCK(5)
Conditions
• See Fig. 2.
Remarks
V
[V]
min
unit
DD
SCK2
2
1
1
(SI2P2)
Low level
tSCKL(5)
pulse width
High level
pulse width
tSCKH(5)
tSCKHA(5a)
• Continuous data
transmission/reception mode of
SIO0 is not in use simultaneous.
• See Fig. 2.
3.0 to 5.5
4
tCYC
• (Note 4-3-2)
tSCKHA(5b)
• Continuous data
transmission/reception mode of
SIO0 is in use simultaneous.
• See Fig. 2.
7
• (Note 4-3-2)
Frequency
tSCK(6)
SCK2
• CMOS output selected.
• See Fig. 2.
4/3
(SI2P2)
SCK2O
(SI2P3)
Low level
tSCKL(6)
tSCKH(6)
tSCKHA(6a)
1/2
1/2
pulse width
High level
pulse width
tSCK
• Continuous data
transmission/reception mode of
SIO0 is not in use simultaneous.
• CMOS output selected.
• See Fig. 2.
3.0 to 5.5
tSCKH(6)
tSCKH(6)
+(5/3)tCYC
+(10/3)tCYC
tCYC
tSCKHA(6b)
• Continuous data
transmission/reception mode of
SIO0 is in use simultaneous.
• CMOS output selected.
• See Fig. 2.
tSCKH(6)
tSCKH(6)
+(5/3)tCYC
+(19/3)tCYC
Data setup time
Data hold time
tsDI(3)
thDI(3)
tdD0(5)
SI2(SI2P1),
SB2(SI2P1)
• Must be specified with respect to
rising edge of SIOCLK
• See fig. 2.
0.03
0.03
3.0 to 5.5
μs
Output delay
time
SO2(SI2P0), • Must be specified with respect to
SB2(SI2P1)
falling edge of SIOCLK
• Must be specified as the time to
the beginning of output state
change in open drain output
mode.
(1/3)tCYC
+0.05
3.0 to 5.5
• See Fig. 2.
Note 4-3-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-3-2: To use serial-clock-input, a time from SI2RUN being set when serial clock is "H" to the first negative edge
of the serial clock must be longer than tSCKHA.
No.A1780-12/31
LC87F83C8A/C8AU/96A/96AU/64A/64AU
Pulse Input Conditions at Ta = -40°C to +85°C, V 1 = V 2 = V 4 = AV = 0V
SS
SS
SS
SS
Specification
Parameter
Symbol
Pins/Remarks
Conditions
V
[V]
min
typ
max
unit
tCYC
μs
DD
High/low level
pulse wid
tPIH(1)
tPIL(1)
INT0(P70),
• Interrupt source flag can be set.
• Event inputs for timer 0 or 1 are
enabled.
INT1(P71),
INT2(P72),
INT4(P20 to P23),
INT5(P24 to P27),
INT6(P20),
3.0 to 5.5
1
2
INT7(P24)
tPIH(2)
tPIL(2)
INT3(P73) when noise
filter time constant is 1/1.
• Interrupt source flag can be set.
• Event inputs for timer 0 are
enabled.
3.0 to 5.5
3.0 to 5.5
tPIH(3)
tPIL(3)
INT3(P73)
• Interrupt source flag can be set.
• Event inputs for timer 0 are
enabled.
(The noise rejection clock
is selected to 1/32.)
INT3(P73)
64
tPIH(4)
tPIL(4)
• Interrupt source flag can be set.
• Event inputs for timer 0 are
enabled.
(The noise rejection clock
is selected to 1/128.)
RES
3.0 to 5.5
3.0 to 5.5
256
200
tPIL(5)
Reset acceptable
V
DD
RES
Internal regulator stabilization time
must be 10ms (max.) or more.
Figure Power-on Time Reset Timing
AD Converter Characteristics at Ta = -40°C to +85°C, V 1 = V 2 = V 4 = AV = 0V
SS
SS
SS
SS
Specification
Parameter
Symbol
Pins/Remarks
Conditions
V
[V]
min
typ
8
max
unit
bit
DD
Resolution
N
AN0(P80)
to AN7(P87)
AN8(P70)
AN9(P71)
3.0 to 5.5
3.0 to 5.5
Absolute precision
Conversion time
ET
(Note 6-1)
1.5
LSB
TCAD
AD conversion time=32×tCYC
(when ADCR2=0) (Note 6-2)
AD conversion time=64×tCYC
(when ADCR2=1) (Note 6-2)
7.104(tCYC=
0.222μs)
3.0 to 5.5
3.0 to 5.5
3.0 to 5.5
μs
14.21(tCYC=
0.222μs)
Analog input
voltage range
Analog port
input current
VAIN
V
V
V
SS
DD
IAINH
IAINL
VAIN=V
DD
3.0 to 5.5
3.0 to 5.5
1
μA
VAIN=V
SS
-1
Note 6-1: The quantization error ( 1/2 LSB) is excluded from the absolute accuracy value.
Note 6-2: The conversion time refers to the interval from the time the instruction for starting the converter is issued till
the complete digital value corresponding to the analog input value is loaded in the required register.
No.A1780-13/31
LC87F83C8A/C8AU/96A/96AU/64A/64AU
Consumption Current Characteristics at Ta = -40°C to +85°C, V 1 = V 2 = V 4 = AV = 0V
SS
SS
SS
SS
Specification
Pins/
Parameter
Symbol
Conditions
Remarks
V
[V]
min
typ
max
unit
DD
Normal mode
consumption
current
IDDOP(1)
V
1
• FmCF=13.5MHz crystal oscillation mode
• FmX’tal=32.768kHz by crystal oscillation
mode
DD
=V
=V
2
4
DD
DD
4.5 to 5.5
3.0 to 4.5
8.0
10.0
8.0
(Note 7-1)
=AV
• System clock set to 13.5MHz side
• Internal RC oscillation stopped
• Frequency variable RC oscillation stopped
• 1/1 frequency division ratio.
DD
IDDOP(2)
6.0
IDDOP(3)
IDDOP(4)
IDDOP(5)
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz by crystal oscillation
mode
4.5 to 5.5
3.0 to 4.5
0.8
0.6
1.2
1.0
mA
• System clock set to internal RC oscillation
• Frequency variable RC oscillation stopped
• 1/2 frequency division ratio.
• FmCF=0Hz (oscillation stopped)
• FmX'al=32.768kHz by crystal oscillation
mode.
4.5 to 5.5
3.0 to 4.5
4.5 to 5.5
3.0 to 4.5
0.8
0.5
2.0
1.5
• Internal RC oscillation stopped
• System clock set to 1MHz with frequency
variable RC oscillation
IDDOP(6)
IDDOP(7)
IDDOP(8)
IDDOP(9)
• 1/2 frequency division ratio.
• FmCF=0Hz (oscillation stopped)
• FmX'al=32.768kHz by crystal oscillation
mode.
300
250
500
450
• System clock set to 32.768kHz side.
• Internal RC oscillation stopped
• Frequency variable RC oscillation stopped
• 1/2 frequency division ratio.
μA
• FmCF=13.5MHz crystal oscillation mode
• FmX’tal=32.768kHz by crystal oscillation
mode
• System clock set to 13.5MHz side
• Internal RC oscillation operation
• Frequency variable RC oscillation stopped
• 1/1 frequency division ratio.
4.5 to 5.5
15.0
20.0
mA
• FM Amp ON 130MHz Reception
• HCTR Amp ON IF count 10.7MHz
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors.
General-purpose I/O port "L" output when the above-mentioned data is measured
However, the P0 port is an input setting because of the mode setting
Continued on next page.
No.A1780-14/31
LC87F83C8A/C8AU/96A/96AU/64A/64AU
Continued from preceding page.
Specification
typ max
Pins/
Parameter
Symbol
Conditions
Remarks
V
[V]
min
unit
DD
HALT mode
consumption
current
IDDHALT(1)
V
1
• HALT mode
DD
=V
=V
2
4
• FmCF=13.5MHz crystal oscillation mode
• FmX’tal=32.768kHz by crystal oscillation
mode
DD
4.5 to 5.5
3.0 to 4.5
2.0
3.0
2.5
DD
(Note 7-1)
=AV
DD
• System clock set to 13.5MHz side
• Internal RC oscillation stopped
• Frequency variable RC oscillation stopped
• 1/1 frequency division ratio.
IDDHALT(2)
1.8
IDDHALT(3)
IDDHALT(4)
IDDHALT(5)
• HALT mode
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz by crystal oscillation
mode
4.5 to 5.5
3.0 to 4.5
0.5
0.3
1.0
0.8
mA
• System clock set to internal RC oscillation
• Frequency variable RC oscillation stopped
• 1/2 frequency division ratio.
• HALT mode
• FmCF=0Hz (oscillation stopped)
• FmX'al=32.768kHz by crystal oscillation
mode.
4.5 to 5.5
3.0 to 4.5
4.5 to 5.5
3.0 to 4.5
1.0
0.8
2.0
1.5
• Internal RC oscillation stopped
• System clock set to 1MHz with frequency
variable RC oscillation
IDDHALT(6)
IDDHALT(7)
IDDHALT(8)
• 1/2 frequency division ratio.
• HALT mode
• FmCF=0Hz (oscillation stopped)
• FmX'al=32.768kHz by crystal oscillation
mode.
250
200
500
400
• System clock set to 32.768kHz side.
• Internal RC oscillation stopped
• Frequency variable RC oscillation stopped
• 1/2 frequency division ratio.
Current drain
during HOLD
mode
IDDHOLD(1)
IDDHOLD(2)
IDDHOLD(3)
V
1
• HOLD mode
DD
4.5 to 5.5
3.0 to 4.5
1.5
1.0
20.0
18.0
Current drain
during time-
base clock
V
1
• Timer HOLD mode
DD
4.5 to 5.5
3.0 to 4.5
150
100
300
200
• FmX'tal=32.768kHz by crystal oscillation
mode
μA
IDDHOLD(4)
HOLD mode
Current drain
during
IDDCLOCK(1)
V
1
• Intermittent for clock mode
DD
=V
2
4
• Each 500ms is shifted to a normal mode,
and 20 steps are executed.
DD
Intermittent for
clock mode
=V
4.5 to 5.5
3.0 to 4.5
250
500
DD
=AV
• FmCF=0Hz (oscillation stopped)
• FmX'al=32.768kHz by crystal oscillation
mode.
DD
IDDCLOCK(2)
• System clock set to 32.768kHz side.
• Internal RC oscillation stopped
• Frequency variable RC oscillation stopped
• 1/1 frequency division ratio.
200
400
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors.
General-purpose I/O port "L" output when the above-mentioned data is measured
However, the P0 port is an input setting because of the mode setting
No.A1780-15/31
LC87F83C8A/C8AU/96A/96AU/64A/64AU
F-ROM Write Characteristics at Ta = +10°C to +55°C, V 1 = V 2 = V 4 = AV = 0V
SS
SS
SS
SS
Specification
typ max
Pins/
Parameter
Symbol
Conditions
Remarks
V
[V]
min
unit
mA
DD
Onboard
programming
current
IDDFW(1)
V
1
DD
• 128-byte programming
• Erasing current including
3.0 to 5.5
3.0 to 5.5
25
40
35
Programming
time
tFW(1)
• 128-byte programming
• Erasing current including
22.5
ms
• Time for setting up 128 byte data is excluded.
UART(Full Duplex) Operating Conditions at Ta = -40°C to +85°C, V 1 = V 2 = V 4 = AV = 0V
SS
SS
SS
SS
Specification
Pins/
Parameter
Symbol
Conditions
Remarks
V
[V]
min
typ
max
unit
DD
Clock rate
UBR, UBR2
UTX1(P32),
RTX1(P33),
UTX2(P33),
RTX2(P34)
3.0 to 5.5
16/3
8192/3
tCYC
Data length: 7, 8, and 9 bits ( LSB first )
Stop bits:
1 bit (2-bit in continuous data transmission)
Parity bits: Non
Example of Continuous 8-bit Data Transmission Mode Processing (First Transmit Data=55H)
Start bit
Stop bit
End of
transmission
Start of
transmission
Transmit data (LSB first)
UBR,
UBR2
Example of Continuous 8-bit Data Reception Mode Processing (First Receive Data=55H)
Start bit
Stop bit
Start of
reception
End of
reception
Received data (LSB first)
UBR,
UBR2
No.A1780-16/31
LC87F83C8A/C8AU/96A/96AU/64A/64AU
Package Dimensions
unit : mm (typ)
3151A
23.2
20.0
80
51
81
50
100
31
1
30
0.65
0.3
0.15
(0.58)
SANYO : QIP100E(14X20)
No.A1780-17/31
LC87F83C8A/C8AU/96A/96AU/64A/64AU
Pin Assignment
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
SI2P1/SI2/SB2
SI2P0/SO2
PF7
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
PB5
PB4
PB3
PF6
PB2
PF5
PB1
PF4
PB0
PF3
VREG
PF2
AV
SS
PF1
AV
DD
LC87F83C8A/AU
LC87F8396A/AU
LC87F8364A/AU
PF0
FMIN
AMIN
HCTR
LCTR
EO
V
V
4
DD
4
SS
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
SUBPD
PC0
PC1
PC2
PC3
PC4
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Top view
SANYO: QIP100E (Lead Free Product)
No.A1780-18/31
LC87F83C8A/C8AU/96A/96AU/64A/64AU
PIN No.
1
NAME
PIN No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
NAME
PC5/DBGP0
PC6/DBGP1
SI2P2/SCK2
SI2P3/SCK2O
PWM1
2
3
PC7/DBGP2
4
P70/INT0/T0LCP/AN8
P71/INT1/T0HCP/AN9
P72/INT2/T0IN/T0LCP
P73/INT3/T0IN/T0HCP
RES
PWM0
5
V
2
2
DD
6
V
SS
7
P00
8
P01
9
XT1
XT2
P02
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
P03
V
1
P04
SS
CF1
CF2
P05/CKO
P06/T6O
V
1
P07/T7O
DD
P80/AN0
P20/INT4/T1IN/T0LCP/T0HCP/INT6/T0LCP1
P81/AN1
P82/AN2
P83/AN3
P84/AN4
P85/AN5
P86/AN6
P87/AN7
P10/SO0
P11/SI0/SB0
P12/SCK0
P13/SO1
P14/SI1/SB1
P15/SCK1
P16/T1PWML
P17/T1PWMH/BUZ
PE0
P21/INT4/T1IN/T0LCP/T0HCP
P22/INT4/T1IN/T0LCP/T0HCP
P23/INT4/T1IN/T0LCP/T0HCP
P24/INT5/T1IN/T0LCP/T0HCP/INT7/T0HCP1
P25/INT5/T1IN/T0LCP/T0HCP
P26/INT5/T1IN/T0LCP/T0HCP
P27/INT5/T1IN/T0LCP/T0HCP
P30/PWM4
P31/PWM5
P32/UTX1
P33/URX1
P34/UTX2
P35/URX2
PB7
PB6
PB5
PE1
PB4
PE2
PB3
PE3
PB2
PE4
PB1
PE5
PB0
PE6
VREG
PE7
AV
SS
V
V
4
4
AV
DD
SS
FMIN
AMIN
HCTR
LCTR
EO
DD
PF0
PF1
PF2
PF3
PF4
SUBPD
PC0
PF5
PF6
PC1
PF7
PC2
SI2P0/SO2
SI2P1/SI2/SB2
PC3
PC4
No.A1780-19/31
LC87F83C8A/C8AU/96A/96AU/64A/64AU
System Block Diagram
CF1
CF2
MainXT
RC
Interrupt control
Standby control
Bus Interface
XT1
XT2
SubXT
MRC
Timer 0
Timer 1
Timer 4
Timer 5
Port 0
Port 1
Port 3
Port 7
Port 8
ADC
IR
PLA
RES
ROM
VREG
Regulator
PC
V
DD
V
SS
ACC
B register
C register
SIO0
SIO1
ALU
INT0 to 3 noise
rejection filter
SIO2
PSW
RAR
RAM
PWM0
PWM1
Port 2 INT4, 5, 6, 7
Port B
Base Timer
Timer 6
Port C
Stack pointer
Watchdog timer
Port E
Port F
PWM4
Timer 7
UART1
VREG operation
PWM5
UART2
V
operation
DD
No.A1780-20/31
LC87F83C8A/C8AU/96A/96AU/64A/64AU
Pin Description
Name
Pin No.
I/O
-
Function Description
Option
No
V
V
V
1
11
56
39
88
14
55
40
89
• Power supply pin
SS
2
• Connect it with GND
SS
SS
4
AV
V
SS
1
-
• Power supply pin
No
DD
V
2
4
• Connect it with V
DD
DD
V
DD
AV
DD
Port 0
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 4-bit units
• Pull-up resistor can be turned on and off in 4-bit units
• HOLD release input
P00
P01
P02
P03
P04
P05
P06
P07
Port 1
57
58
59
60
61
62
63
64
• Port 0 interrupt input
• Pin functions
P05: System clock output
P06: Timer 6 toggle output
P07: Timer 7 toggle output
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 1-bit units
P10
P11
P12
P13
P14
P15
P16
P17
23
24
25
26
27
28
29
30
• Pull-up resistor can be turned on and off in 1-bit units
• Pin functions
P10: SIO0 data output
P11: SIO0 data input, bus I/O
P12: SIO0 clock I/O
P13: SIO1 data output
P14: SIO1 data input, bus I/O
P15: SIO1 clock I/O
P16: Timer 1 PWML output
P17: Timer 1 PWMH output, beeper output
• 8-bit I/O port
Port 2
I/O
Yes
• I/O specifiable in 1-bit units
P20
P21
P22
P23
P24
P25
P26
P27
65
66
67
68
69
70
71
72
• Pull-up resistor can be turned on and off in 1-bit units
• Other functions
P20: INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input/INT6 input/timer 0L capture 1 input
P21 to P23: INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input
P24: INT5 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input/INT7 input/timer 0H capture 1 input
P25 to P27: INT5 input/HOLD reset input/timer 1 event input/timer0L capture input/
timer 0H capture input Interrupt acknowledge type
• Interrupt acknowledge type
Rising/
Rising
Falling
H level
L level
Falling
enable
enable
enable
enable
INT4
INT5
INT6
INT7
enable
enable
enable
enable
enable
enable
enable
enable
disable
disable
disable
disable
disable
disable
disable
disable
Port 3
I/O
• 6-bit I/O port
Yes
• I/O specifiable in 1-bit units
P30
P31
P32
P33
P34
P35
73
74
75
76
77
78
• Pull-up resistor can be turned on and off in 1-bit units
• Pin functions
P30: PWM4 output
P31: PWM5 output
P32: UART1 transmit
P33: UART1 receive
P34: UART2 transmit
P35: UART2 receive
Continued on next page.
No.A1780-21/31
LC87F83C8A/C8AU/96A/96AU/64A/64AU
Continued from preceding page.
Name
Port 7
Pin No.
I/O
I/O
Function Description
Option
No
• 4-bit I/O port
• I/O specifiable in 1-bit units
P70
P71
P72
P73
4
5
6
7
• Pull-up resistor can be turned on and off in 1-bit units
• Other functions
P70: INT0 input/HOLD release input/Timer 0L capture input/Output for watchdog timer/
AD converter input port
P71: INT1 input/HOLD release input/Timer 0H capture input/
AD converter input port
P72: INT2 input/HOLD release input/Timer 0 event input/timer0L capture input
P73: INT3 input with noise filter/Timer 0 event input/timer 0H capture input
• Interrupt acknowledge type
Rising/
Rising
Falling
H level
L level
Falling
disable
disable
enable
enable
INT0
INT1
INT2
INT3
enable
enable
enable
enable
enable
enable
enable
enable
enable
enable
disable
disable
enable
enable
disable
disable
Port 8
I/O
I/O
I/O
I/O
I/O
• 8-bit I/O port (Output: N-channel open drain)
• I/O specifiable in 1-bit units
No
Yes
Yes
No
P80
P81
P82
P83
P84
P85
P86
P87
Port B
15
16
17
18
19
20
21
22
• Other functions
P80 to P87: AD converter input port
• 8-bit I/O port
• I/O specifiable in 1-bit units
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
Port C
86
85
84
83
82
81
80
79
• Pull-up resistor can be turned on and off in 1-bit units
• 8-bit I/O port
• I/O specifiable in 1-bit units
• Pull-up resistor can be turned on and off in 1-bit units
Pin functions
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
Port E
96
97
98
99
100
1
PC5 to PC7: On-chip Debugger
2
3
• 8-bit I/O port
• I/O specifiable in 2-bit units
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
Port F
31
32
33
34
35
36
37
38
• Pull-up resistor can be turned on and off in 1-bit units
• 8-bit I/O port
No
• I/O specifiable in 2-bit units
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
41
42
43
44
45
46
47
48
• Pull-up resistor can be turned on and off in 1-bit units
Continued on next page.
No.A1780-22/31
LC87F83C8A/C8AU/96A/96AU/64A/64AU
Continued from preceding page.
Name
SIO2
Pin No.
I/O
I/O
Function Description
Option
No
• 4-bit I/O port
• I/O specifiable in 1-bit units
• Shared functions:
SI2P0
SI2P1
SI2P2
SI2P3
49
50
51
52
SI2P0: SIO2 data output
SI2P1: SIO2 data input, bus input/output
SI2P2: SIO2 clock input/output
SI2P3: SIO2 clock output
• PWM0 output port
PWM0
PWM1
RES
54
53
8
I/O
No
No
No
No
• General-purpose I/O available
• PWM1 output port
I/O
• General-purpose I/O available
• Reset pin
I
I
Must connect it with V 1 through RC (Refer to Page27 Figure 1)
DD
• Input terminal for 32.768kHz X'tal oscillation
• Shared functions:
XT1
9
General-purpose input port
Must be set for input with software and connected to V 1 if not to be used.
SS
XT2
10
I/O
• Output terminal for 32.768kHz X'tal oscillation
• Shared functions:
No
General-purpose I/O port
Must be set for general-purpose output and kept open if not to be used.
Please connect suitable dumping resistance for the crystal used between the terminal
when you use it as Output terminal for 32.768kHz X'tal oscillation.
• Input terminal for 13.5MHz X'tal oscillation
CF1
12
13
94
95
90
I
No
No
No
No
No
CF2
O
O
O
I
• Output terminal for 13.5MHz X'tal oscillation
• Output terminal for main charge pump
• Output terminal for sub charge pump
EO
SUBPD
FMIN
• Input terminal for FM VCO (local oscillator)
• The signal input to this pin must be capacitor coupled
• Input frequency: 10 to 150MHz
Please open the terminal when you do not use this terminal. Moreover, please make the
pull-down of this terminal effective with software.
• Input terminal for AM VCO (local oscillator)
AMIN
HCTR
LCTR
VREG
91
92
93
87
I
I
No
No
No
No
• The signal input to this pin must be capacitor coupled
• Input frequency: 0.5 to 40MHz
Please open the terminal when you do not use this terminal. Moreover, please make the
pull-down of this terminal effective with software.
• Input terminal for Universal counter
• The signal input to this pin must be capacitor coupled
• Input frequency: 0.4 to 12MHz
Please open the terminal when you do not use this terminal. Moreover, please make the
pull-down of this terminal effective with software.
• Input terminal for Universal counter
I
• The signal input to this pin must be capacitor coupled
• Input frequency: 100 to 500kHz
Please open the terminal when you do not use this terminal. Moreover, please make the
pull-down of this terminal effective with software.
• Internal low voltage output
O
• Connect a bypass capacitor to this pin. (Refer to Page27)
Note: The coupling capacitors must be placed as close to the pins as possible. A capacitance of 100pF is recommended.
The capacitance value for HCTR and LCTR must be 1000pF or less.
No.A1780-23/31
LC87F83C8A/C8AU/96A/96AU/64A/64AU
Port Output Types
The table below lists the types of port outputs and the presence/absence of a pull-up resistor.
Data can be read into any input port even if it is in the output mode.
Options Selected
Port
Option Type
Output Type
Pull-up Resistor
in Units of
1 bit
P00 to P07
1
2
1
2
CMOS
Programmable (Note 1)
No
N-channel open drain
CMOS
P10 to P17
P20 to P27
P30 to P35
PB0 to PB7
PC0 to PC7
1 bit
Programmable
Programmable
N-channel open drain
1 bit
-
1
2
CMOS
Programmable
Programmable
Programmable
N-channel open drain
CMOS
PE0 to PE7
PF0 to PF7
P70
No
-
-
-
-
No
No
No
No
N-channel open drain
CMOS
Programmable
P71 to P73
P80 to P87
Programmable
N-channel open drain
CMOS
No
No
SI2P0, SI2P2,
SI2P3
PWM0, PWM1
SI2P1
-
-
No
No
CMOS (when selected as ordinary port)
N-channel open drain (When SIO2 data is selected)
Input only
No
No
FMIN, AMIN,
HCTR, LCTR
EO, SUBPD
-
-
-
No
No
No
Output only
Input only
No
No
No
XT1
XT2
Output for 32.768kHz quartz oscillator
N-channel open drain (when in general-purpose
output mode)
Note 1: Programmable pull-up resistors for port 0 are controlled in 4 bit units (P00 to 03, P04 to 07).
*1: Make the following connection to minimize the noise input to the V 1 pin and prolong the backup time.
DD
Be sure to electrically short the V 1, V 2, AV and V 4 pins.
SS SS SS SS
Example 1: When backup is active in the HOLD mode, the high level of the port outputs is supplied by the backup
capacitors.
Back-up
capacitor
LSI
V
V
1
DD
Power
Supply
2
DD
AV
DD
VREG
V
4
DD
V
1 V 2 AV
SS
V
4
SS
SS SS
No.A1780-24/31
LC87F83C8A/C8AU/96A/96AU/64A/64AU
Example 2: The high level output at the ports is unstable when the HOLD mode.backup is in effect.
Back-up
LSI
capacitor
V
1
DD
Power
supply
V
2
DD
AV
DD
VREG
V
4
DD
V
1 V 2 AV
SS
V
4
SS
SS SS
No.A1780-25/31
LC87F83C8A/C8AU/96A/96AU/64A/64AU
V 1, V 1 Terminal condition
DD SS
It is necessary to place capacitors between V 1 and V 1 as describe below.
DD SS
• Place capacitors as close to V 1 and V 1 as possible.
DD SS
• Place capacitors so that the length of each terminal to the each leg of the capacitor be equal (L1 = L1’, L2 = L2’).
• Place high capacitance capacitor C1 and low capacitance capacitor C2 in parallel.
• Capacitance of C2 must be more than 0.1μF.
• Please mount a suitable capacitor about C1.
• Use thicker pattern for V 1 and V 1.
DD SS
L2
L1
V
V
1
SS
C2
C1
1
DD
L1’
L2’
AV , AV
DD
Terminal condition
SS
It is necessary to place capacitors between AV
and AV as describe below.
SS
DD
• Place capacitors as close to AV
and AV as possible.
DD
SS
• Place capacitors so that the length of each terminal to the each leg of the capacitor be equal (L3 = L3’).
• Capacitance of C3 must be more than 1μF.
• Use thicker pattern for AV
and AV
.
DD
SS
L3
AV
AV
SS
DD
C3
L3’
No.A1780-26/31
LC87F83C8A/C8AU/96A/96AU/64A/64AU
VREG, AV
Terminal condition
SS
It is necessary to place capacitors between VREG and AV as describe below.
SS
• Place capacitors as close to VREG and AV as possible.
SS
• Place capacitors so that the length of each terminal to the each leg of the capacitor be equal (L4 = L4’).
• Capacitance of C4 must be more than 1μF to 10μF.
• Use thicker pattern for VREG and AV
.
SS
L4
AV
SS
C4
VREG
L4’
V x, V x Terminal condition x=2, 4
DD SS
• It is necessary to place capacitors between V x and V x as describe below.
DD SS
• Place capacitors as close to V x and V x as possible.
DD SS
• Place capacitors so that the length of each terminal to the each leg of the capacitor be equal (L5 = L5’).
• Capacitance of C5 must be more than 0.1μF.
• Use thicker pattern for V x and V x.
DD
SS
L5
V
V
x
SS
C5
x
DD
L5’
V
DD
(Note) Select C
RES
and R
RES
value to assure that reset is
becomes higher than the
generated after the V
R
RES
DD
minimum operating voltage.
RES
Recommended value
C
R
: 0.47μF
: 270kΩ
C
RES
RES
RES
Figure 1 Reset Circuit
No.A1780-27/31
LC87F83C8A/C8AU/96A/96AU/64A/64AU
SIOCLK:
DATAIN:
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
DATAOUT:
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DO8
Data RAM
transmission period
(only SIO0, 2)
tSCK
tSCKL
tSCKH
SIOCLK:
DATAIN:
tsDI
thDI
tdDO
DATAOUT:
Data RAM
transmission period
(only SIO0, 2)
tSCKL
tSCKHA
SIOCLK:
DATAIN:
tsDI
thDI
tdDO
DATAOUT:
Figure 2 Serial Input/Output Test Condition
tPIL
tPIH
Figure 3 Pulse Input Timing Condition
No.A1780-28/31
LC87F83C8A/C8AU/96A/96AU/64A/64AU
Concerning Differences of the Mask Version and the Flash Version
1) Although the electrical specifications are the same for the mask and flash versions, differences may arise in the
actual values for threshold level of the input ports, output current of the output ports, input sensitivity, etc.
Variations may also be found from lot to lot. It must therefore be kept in mind that if finished products are designed
using the actual values of the samples, these variations may prevent the finished products from operating.
2) The undesirable radiation level is not listed among the specifications. Since differences may arise between the
mask and flash versions, this must be kept in mind when designing the finished products.
Concerning Differences of ROM Writing in Our Company and User
ROM writing in out company
ROM writing in user
LC87F83C8A-FXXXX-E
LC87F8396A-FXXXX-E
LC87F8364A-FXXXX-E
LC87F83C8AU-QIP-E
LC87F8396AU-QIP-E
LC87F8364AU-QIP-E
Name of articles
Tape Out
Necessary
Our company
Our company
Our company
Unnecessary
User
Data confirmation after writing
Terminal destruction confirmation after writing
Terminal curved confirmation after writing
User
User
The W87F83256Q circuit board must be requested as the data writing board.
The AF-9708 made by Ando is recommended as the ROM writer. Confirm ROM writer's version to the office.
Method of ordering ROM when ROM writing by our company is done
Please submit Program of flash ROM and Flash ROM order material to the person in charge of each business.
Condition before it mounts
1. Writing by user
2. Writing by our company
PROM writing shipment goods
Please mount according to
the following procedures.
PROM unwriting shipment goods
It is recommended to mount according to
the following procedures.
QIP sample
QIP sample
Mounting
Program writing
/Verify
Recommended screening
procedure
No energizing
temperature leaving
+1
150±5°C, 24 Hr
-0
Program reading
Mounting
No.A1780-29/31
LC87F83C8A/C8AU/96A/96AU/64A/64AU
Example of Writing Data onto the on-chip Flash ROM of the LC87F83C8AU/96AU/64AU
(using the AF-9708)
I. Writing the data using the AF-9708 (made by Ando) PROM programmer
1. ROMTYPE settings
ROMTYPE
→ Select [MAKER]
→ Select [SANYO]
→ Select [LC87F83C8A]
→ SET
→ SET
→ SET
It corresponds now PROM PROGRAMMER AF-9708 (made of ANDO). Please inquire of the person in charge of
each business.
2. Start/Stop address settings
FUNCTION
→ 1 : Address setting mode
Type No.
ROM capacity
STOP ADDRESS
1FFFF
LC87F8364AU
LC87F8396AU
LC87F83C8AU
64KB
96KB
128KB
3. Executing data erasure
DEVICE → B → SET : For data erasure execution.
4. Executing data writing
DEVICE
→ F → SET : For program and verify execution.
II. Writing board
The writing board is shown in the figure below. The position of pin 1 must checked before connecting to the
EPROM programmer.
LC87F83C8AU/96AU/64AU
1pin
EPROM PROGRAMMER
1pin
To be used for the general-purpose EPROM programmer: Model W87F83256Q
No.A1780-30/31
LC87F83C8A/C8AU/96A/96AU/64A/64AU
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using
products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.
products described or contained herein.
SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all
semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or
malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise
to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt
safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not
limited to protective circuits and error prevention circuits for safe design, redundant design, and structural
design.
In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are
controlled under any of applicable local export control laws and regulations, such products may require the
export license from the authorities concerned in accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise,
without the prior written consent of SANYO Semiconductor Co.,Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the
SANYO Semiconductor Co.,Ltd. product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed
for volume production.
Upon using the technical information or products described herein, neither warranty nor license shall be granted
with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third
party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's
intellctual property rights which has resulted from the use of the technical information and products mentioned
above.
This catalog provides information as of February, 2011. Specifications and information herein are subject
to change without notice.
PS No.A1780-31/31
相关型号：
©2020 ICPDF网 联系我们和版权申明