LC898128DP1XGTBG [ONSEMI]
OIS 和开放式自动对焦控制 LSI;
| 型号： | LC898128DP1XGTBG |
| 厂家： | 
ONSEMI |
| 描述： | OIS 和开放式自动对焦控制 LSI 外围集成电路 |
| 文件： | 总10页 (文件大小：166K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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OIS & Open-AF Control LSI
LC898128DP
WLCSP30
CASE 567WE
Overview
This is a system LSI integrating an on−chip 32bit DSP, a FLASH
ROM and peripherals including analog circuits for OIS (Optical
Image Stabilization) / Open−AF (Auto Focus) control, constant
current drivers.
MARKING DIAGRAM
128DP1XH
AWLYYWW
Features
• On−chip 32bit DSP
♦ Built−in Software for Digital Servo Filter
♦ Built−in Software for Gyro Filter
A
WL
YY
= Assembly Location
= Wafer Lot
= Year
• Memory
WW
= Work Week
♦ 40 kB Flash Memory
♦ Program ROM
♦ Program SRAM
♦ Data SRAM
ORDERING INFORMATION
†
Device
Package
Shipping
• Peripherals
LC898128DP1XHTBG WLCSP30
4,000 /
♦ AD Converter
(Pb−Free) Tape & Reel
♦ DA Converter
♦ 2−wire Serial I/F Circuit
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
2
(The Communication Protocol is Compatible with I C)
♦ Hall Bias Circuit
♦ Hal Amp
♦ OSC (Oscillator)
♦ LDO (Low Drop−Out Regulator)
♦ Temperature Sensor
♦ Digital Gyro I/F (SPI)
♦ Interrupt I/F
• Driver
♦ OIS:
Constant Current Linear Driver (x2ch, I = 200 mA)
full
♦ OP−AF (Bi−direction):
Constant Current Linear Driver (x1ch, I = 130 mA)
full
• Package
♦ WLCSP30 (4.300 mm x 1.175 mm) Thickness Max. 0.35 mm,
with Back Coat
♦ Ball 3 x 10
♦ Pitch 0.4 mm
♦ Lead−Free
♦ Halogen Free
• Power Supply Voltage
♦ AD/DA/VGA/LDO/OSC/Flash/:
AVDD30 = 2.7 V to 3.3 V
♦ Driver: VM1,2 = 1.8 V to 3.3 V
♦ 1.8 V I/O: IOVDD = 1.7 V to 3.3 V
♦ Core Logic: Generated by On−chip LDO
Connect 1 mF Capacitor to LDPO Pin
© Semiconductor Components Industries, LLC, 2021
1
Publication Order Number:
September, 2021 − Rev. 0
LC898128DP1XH/D
LC898128DP
BLOCK DIAGRAM
DSP
RAM
ROM
RAM
FLASH
Temp
Sensor
SCL
SDA
2−wire
Serial I/F
Hall
VGA
ADC
SSB
SCLK
MOSI
MISO
SPI
INT
Hall Offset
/ Bias
Port
EIRQ 1
EIRQ 2
AVDD 30
OUT 1
OUT 2
OUT 3
OUT 4
OUT 5
OUT 6
LDPO
AVSS
LDO
POR
OSC
1 mF
H−Bridge
Driver
VM1
VM2
PGND
Figure 1. Block Diagram
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2
LC898128DP
PIN LAYOUT
C
B
A
OUT1
VM1
OUT2
PGND
OUT5
VM2
HLXBO
AVSS
HLYBO
EIRQ2
MISO
MOSI
IOVDD
SSB
SCLK
SDA
PCNT OPINPX OPINPY MON1
OUT3
1
OUT4
2
OUT6 AVDD30
LDPO OPINMX OPINMY MON2
EIRQ1
9
SCL
10
3
4
5
6
7
8
Driver
VDD/VSS
Internal VDD Output
1.8 V I/O
Figure 2. Pin Layout (Bottom View)
PIN DESCRIPTION
PIN DESCRIPTION
No.
1
Pin
MON1
MON2
SCL
I/O
B
I/O Pwr
AVDD30
AVDD30
IOVDD
Primary Function
Servo Monitor Analog In/Out
Servo Monitor Analog In/Out
2−wire serial HOST I/F Clock Slave
2−wire serial HOST I/F Data Slave
I/O Power (1.7 V to 3.3 V)
Sub Functions
Init
Z
2−wire serial Monitor Data
2
B
2−wire serial Monitor Clock
Z
3
B
Z
4
SDA
B
IOVDD
Z
5
IOVDD
SSB
P
−
6
B
IOVDD
IOVDD
Digital Gyro Data I/F Chip Select
Out (3/4−wire Master)
Digital Gyro Data I/F Chip Select In
(3/4−wire Slave)
Z
7
8
SCLK
B
B
Digital Gyro Data I/F Clock Out
(3/4−wire Master)
Digital Gyro Data I/F Clock In
(3/4−wire Slave)
Z
Z
2−wire serial Sensor Hub I/F Clock
Slave
MOSI
IOVDD
IOVDD
Digital Gyro Data I/F Data InOut
(3−wire Master)
Digital Gyro Data I/F Data Out
(4−wire Master)
Digital Gyro Data I/F Data InOut
(3wire Slave)
Digital Gyro Data I/F Data In
(4−wire Slave)
2−wire serial Sensor Hub I/F Data
Slave
9
MISO
B
Digital Gyro Data I/F Data In
(4−wire Master)
Digital Gyro Data I/F Data Out
(4−wire Slave)
U
Digital Gyro Data I/F Chip Select 2
Out (3−wire Master)
10
11
EIRQ1
EIRQ2
B
B
IOVDD
IOVDD
Interrupt Input 1
Interrupt Input 2
Z
Z
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3
LC898128DP
PIN DESCRIPTION (continued)
No.
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Pin
I/O
O
O
O
I
I/O Pwr
AVDD30
AVDD30
AVDD30
AVDD30
AVDD30
AVDD30
AVDD30
VM1
Primary Function
Sub Functions
Init
Z
Z
Z
−
PCNT
No use
HLXBO
HLYBO
OPINMX
OPINPX
OPINMY
OPINPY
OUT1
OIS Hall X Bias Output
OIS Hall Y Bias Output
OIS Hall X Opamp Input Minus
OIS Hall X Opamp Input Plus
OIS Hall Y Opamp Input Minus
OIS Hall Y Opamp Input Plus
OIS Driver Output
I
−
I
−
I
−
O
O
O
O
O
O
P
P
P
P
Z
Z
Z
Z
Z
Z
−
OUT2
VM1
OIS Driver Output
OUT3
VM1
OIS Driver Output
OUT4
VM1
OIS Driver Output
OUT5
VM2
OP−AF Driver Output
OUT6
VM2
OP−AF Driver Output
AVDD30
AVSS
Analog Power (2.7 V to 3.3 V)
Analog GND
−
VM1
OIS Driver Power (1.8 V to 3.3 V)
−
VM2
OP−AF Driver Power
(1.8 V to 3.3 V)
−
29
30
PGND
LDPO
P
P
Driver GND
−
−
Internal 1.38 V LDO Power Output
*Process when pins are not used
• PIN TYPE “O” – Ensure that it is set to OPEN.
• PIN TYPE “I” – OPEN is inhibited. Ensure that it is connected to the V or V even when it is unused.
DD
SS
(Please contact onsemi for more information about selection of V or V .)
DD
SS
• PIN TYPE “B” – If you are unsure about processing method on the pin description of pin layout table, please contact us.
Note that incorrect processing of unused pins may result in defects.
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4
LC898128DP
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS (AVSS = 0 V, PGND = 0 V)
Parameter
Power Supply Voltage
Symbol
Conditions
T ≤ 25°C
A
Ratings
−0.3 to 4.6
−0.3 to 4.6
−0.3 to 4.6
Unit
V
V
30 max
AD
V
max
max
T
≤ 25°C
≤ 25°C
≤ 25°C
≤ 25°C
≤ 25°C
V
M
A
V
IO
T
A
V
Input/Output Voltage
V 30, V 30
T
A
−0.3 to V 30 + 0.3
V
AI
AO
AD
V
30, V 30
T
A
−0.3 to V 30 + 0.3
V
MI
MO
M
V , V
T
A
−0.3 to V 18 + 0.3
V
II
IOO
IO
Storage Temperature
T
stg
−55 to 125
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
ALLOWABLE OPERATING RATINGS (T = −30 to 85°C, AVSS = 0 V, PGND = 0 V)
A
Parameter
3.0 V POWER SUPPLY (AVDD30)
Power Supply Voltage
Symbol
Min
Typ
Max
Unit
V
AD
30
2.7
0
2.8
3.3
V
V
Input Voltage Range
V
INA
−
V
AD
30
3.0 V POWER SUPPLY (VM1, VM2)
Power Supply Voltage
V 30
1.8
2.8
the lower of
3.3 and
V
V
M
(Note 1)
AVDD30 + 0.5
Input Voltage Range
V
INM
0
−
V 30
M
1.8 V POWER SUPPLY (IOVDD)
Power Supply Voltage
Input Voltage Range
V
1.7
0
1.8
3.3
V
V
IO
V
INI
−
V
IO
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
1. Constant current.
DC CHARACTERISTICS: INPUT/OUTPUT
(T = −30 to 85°C, AVSS = 0 V, PGND = 0 V, AVDD30 = 2.7 to 3.3 V, IOVDD = 1.7 to 3.3 V)
A
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Applicable Pins
High−level Input Voltage
V
CMOS
0.7
V
SCL, SDA, SSB,
SCLK, MOSI,
MISO, EIRQ1,
EIRQ2
IH
Schmitt
IOVDD
Low−level Input Voltage
High−level Input Voltage
Low−level Input Voltage
High−level Output Voltage
V
0.3
V
V
V
V
IL
IOVDD
V
IH
CMOS
Schmitt
0.7
AVDD30
MON1, MON2
MON1, MON2
V
0.3
AVDD30
IL
V
OH
I
I
= −3 mA
IOVDD −
SDA, SSB, SCLK,
MOSI, MISO,
EIRQ1, EIRQ2
OH
0.2
Low−level Output Voltage
V
OL
= 3 mA
0.2
0.2
V
SCL, SDA, SSB,
SCLK, MOSI,
MISO, EIRQ1,
EIRQ2
OL
High−level Output Voltage
Low−level Output Voltage
V
OH
I
I
= −2 mA
AVDD30
− 0.2
V
V
MON1, MON2
OH
V
OL
= 2 mA
MON1, MON2
OL
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5
LC898128DP
DC CHARACTERISTICS: INPUT/OUTPUT (continued)
(T = −30 to 85°C, AVSS = 0 V, PGND = 0 V, AVDD30 = 2.7 to 3.3 V, IOVDD = 1.7 to 3.3 V)
A
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Applicable Pins
Analog Input Voltage
V
AI
AVSS
AVDD30
V
MON1, MON2,
OPINPX, OPINMX,
OPINPY, OPINMY
Pull Up Resistor
R
R
20
20
250
250
kW
kW
SSB, SCLK, MOSI,
MISO, EIRQ1,
EIRQ2, MON1,
MON2
up
dn
Pull Down Resistor
DRIVER OUTPUT
(T = 25°C, V = 0 V, PGND = 0 V, AVDD30 = VM1,2 = 2.8 V)
A
SS
Parameter
Symbol
Conditions
Min
Typ
Max
210
Unit
mA
mA
Output Current, OUT1−OUT4
I
full
Full code
Full code
190
200
130
Output Current, OUT5, OUT6
123.5
136.5
OP−AF (bi−direction)
NON−VOLATILE MEMORY CHARACTERISTICS
Parameter
Symbol
Conditions
Read for FLASH
Program & Erase for FLASH
Value
−30 to 85
Unit
°C
Operating Temperature
T
opr1
T
opr2
−10 to 65 (Note 2)
°C
2. All drivers must be in the standby state.
Item
Symbol
EN
Conditions
Min
−
Typ
Max
1000
−
Unit
Cycles
Years
ms
Applicable Circuit
Endurance
−
−
−
Flash Memory
Data Retention
Write Time
RT
10
−
t
3
WT
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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6
LC898128DP
AC CHARACTERISTICS
Power Supply Timing
t
R
t
W
AVDD30
Min V
V
bot
VM1.2
IOVDD
10%
Figure 3. VDD Supply Timing
Table 1.
Item
Symbol
Min
Typ
Max
Unit
Rise Time
t
−
100
−
−
−
−
3
−
ms
ms
V
R
Wait Time
t
W
Bottom Voltage
V
bot
0.2
Injection order between AVDD30, VM1,2 and IOVDD is below.
1.7 V
1.7 V
IOVDD
t
t
AVIO
IOAV
2.7 V
2.7 V
AVDD30
VM1,2
0.2 V
0.2 V
t
t
AVVM
VMAV
0.2 V
0.2 V
Figure 4. Injection Order between AVDD30, VM1,2 and IOVDD
Table 2.
Item
Symbol
Min
Typ
Max
Unit
IOVDD On to AVDD30 ON
AVDD30 ON to VM1,2 ON
VM1,2 OFF to AVDD30 OFF
AVDD30 OFF to IOVDD OFF
t
0
0
0
0
−
−
−
−
−
−
−
*
ms
ms
ms
ms
IOAV
t
AVVM
VMAV
t
t
AVIO
*Please make IOPRSTB (D0_0064h, bit0) = 0 before turning OFF AVDD when AVDD is turned off with keeping IOVDD on.
NOTES:
− VM1, VM2 ≤ AVDD30 + 0.5 V
− Power ON/OFF of VM1 and VM2, is possible individually.
SDA, SCL, SSB, SCLK, MOSI, MISO, EIRQ1 and EIRQ2 tolerate 3 V input at the time of power off.
The data in the Flash memory may be rewritten unintentionally if you do not keep specifications.
And it is forbidden to power off during Flash memory access. The data in the Flash memory may be rewritten unintentionally.
OIS driver is recommended to set standby before VM1 power off.
AF driver is recommended to set standby before VM2 power off.
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7
LC898128DP
2−wire Serial Interface Timing
The 2−wire serial interface timing definition and electric characteristics are shown below. The communication protocol is
2
compatible with I C. This circuit has clock stretch function.
Static Address: 7’b0100100
t
f
t
r
t
BUF
V
IHmin
SDA
V
(MOSI)
ILmin
t
t
t
t
t
t
SU;STO
HD;STA
HD;DAT SU;DAT
SU;STA HD;STA
t
f
t
r
V
IHmin
SCL
(SCLK)
V
ILmin
t
t
1/f
SCL
LOW
HIGH
Start Condition
Repeated Start Condition
Stop Condition Start Condition
Figure 5. 2−wire Serial Interface Timing
Table 3.
Standard−mode
Fast−mode
Fast−mode Plus
Min
Max
Min
Max
Min
Max
Item
SCL Clock Frequency
Symbol
Units
kHz
ms
f
−
100
−
−
400
−
−
1000
SCL
START Condition Hold Time
SCL Clock Low Period
SCL Clock High Period
t
t
4.0
4.7
4.0
4.7
0.6
1.3
0.6
0.6
0.26
0.5
−
−
−
−
HD;STA
t
−
−
ms
LOW
t
−
−
0.26
0.26
ms
HIGH
Setup Time for Repetition
START Condition
−
−
ms
SU;STA
Data Hold Time
t
0 (Note 3)
3.45
−
0 (Note 3)
0.9
−
0 (Note 3)
0.45
−
ms
ns
ns
ns
ms
ms
HD;DAT
Data Setup Time
t
250
−
100
−
50
−
SU;DAT
SDA, SCL Rising Time
SDA, SCL Falling Time
STOP Condition Setup Time
t
r
1000
300
−
300
300
−
120
120
−
t
f
−
−
−
t
4.0
4.7
0.6
1.3
0.26
0.5
SU;STO
Bus Free Time between
STOP and START
t
−
−
−
BUF
2
3. Although the I C specification defines a condition that 300 ns of hold time is required internally, this LSI is designed for a condition with typ.
40 ns of hold time. If SDA (MOSI) signal is unstable around falling point of SCL (SCLK) signal, please implement an appropriate treatment
on board, such as inserting a resister.
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8
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WLCSP30 1.175x4.3X0.33
CASE 567WE
ISSUE O
DATE 28 MAR 2018
GENERIC
MARKING DIAGRAM*
XXXXX = Specific Device Code
*This information is generic. Please refer to
A
= Assembly Location
= Wafer Lot
= Year
XXXXXXXX
AWLYYWW
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some products
may not follow the Generic Marking.
WL
YY
WW
= Work Week
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON86072G
WLCSP30 1.175x4.3X0.33
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
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© Semiconductor Components Industries, LLC, 2018
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