LC898129DP1XHTBG [ONSEMI]

OIS & ClosedAF Control LSI;


型号：	LC898129DP1XHTBG
厂家：	ONSEMI
描述：	OIS & ClosedAF Control LSI
文件：	总10页 (文件大小：187K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DATA SHEET

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Summary of Specification for

OIS & CL-AF Control LSI

WLCSP40, 1.60x4.15x0.33

LC898129DP1XHTBG

CASE 567XS

MARKING DIAGRAM

Overview

LC898129DP1XHTBG is a system LSI integrating an on−chip

32 bit DSP, a FLASH ROM and peripherals including analog circuits

for OIS (Optical Image Stabilization) / Closed Loop−AF (Auto Focus)

control and drivers.

898129XH

AWLYYWW

898129XH = Specific Device Code

= Assembly Location

= Wafer Lot

= Year of Production

= Work Week

Features

• On−chip 32 bit DSP

♦ Built−in Software for Digital Servo Filter

♦ Built−in Software for Gyro Filter

• Memory

ORDERING INFORMATION

See detailed ordering and shipping information on page 8 of

this data sheet.

♦ Flash Memory

♦ Program ROM

♦ Program SRAM

♦ Data SRAM

• Peripherals

♦ AD Converter

♦ DA Converter

♦ 2−wire Serial I/F Circuit (The Communication Protocol is

Compatible with I C)

♦ Hall Bias Circuit

♦ Hall Amp

♦ OSC (Oscillator)

♦ LDO (Low Drop−Out Regulator)

♦ Digital Gyro I/F (SPI)

♦ Interrupt I/F

• Driver

♦ OIS

Linear Driver (x2ch, I = 200 mA)

full

♦ CL−AF (bi−direction)

Linear Driver (x1ch, I = 150 mA)

full

• Power Supply Voltage

♦ AD/DA/VGA/LDO/OSC/Flash: AVDD30 = 2.7 V to 3.3 V

♦ Driver: VM = 1.8 V to 3.3 V

♦ 1.8 V I/O: IOVDD = 1.7 V to 3.3 V

♦ Core Logic: Generated by On−chip LDO

Connect 1 mF Capacitor to LDPO pin

• Package

♦ WLCSP40 (4 x 10 Pin) Thickness Max. 0.35 mm, with Back Coat

• These Devices are Pb−Free, Halogen Free/BFR Free

and are RoHS Compliant

Publication Order Number:

August, 2021 − Rev. 1

LC898129DP1XH/D

LC898129DP1XHTBG

BLOCK DIAGRAM

DSP

RAM

ROM

RAM

FLASH

SCL

SDA

2−wire

serial I/F

Slave

Hall

VGA

ADC

SSB

SCLK

MOSI

MISO

SPI

Hall Offset

/ Bias

EIRQ1

EIRQ2

Port

INT

AVDD30

SCL2

SDA2

2−wire

serial I/F

Master

LDPO

AVSS

LDO

POR

OSC

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

1 mF

H−Bridge

Driver

PGND

Figure 1. Block Diagram

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LC898129DP1XHTBG

PIN LAYOUT

OUT1

OUT2

OUT3

OUT5

PGND

OUT6

HLBO1

OPINM2

HLBO2

MON1

MON2

HLBO3

SCL2

EIRQ1

EIRQ2

AVSS

SSB

SCLK

MOSI

SCL

SDA

MISO

PGND

AVSS

OPINM1

OPINM3

SDA2

OUT4

OPINP1

OPINP2

OPINP3

AVSS

AVDD30

LDPO

AVSS

IOVDD

Driver

VDD/VSS

Internal VDD Output

1.8 V I/O

Figure 2. Pin Layout (Bottom View)

Table 1. PIN DESCRIPTION

No.

MON1

MON2

SCL

I/O

I/O Pwr

AVDD30

IOVDD

Function

Init

Servo Monitor Analog In/Out

2−wire serial HOST I/F Clock Slave

2−wire serial HOST I/F Data Slave

I/O Power (1.7 V to 3.3 V)

SDA

IOVDD

SSB

−

IOVDD

Digital Gyro Data I/F Chip Select Out (3/4−wire Master)

Digital Gyro Data I/F Clock Out (3/4−wire Master)

SCLK

MOSI

Digital Gyro Data I/F Data InOut (3−wire Master)

Digital Gyro Data I/F Data Out (4−wire Master)

MISO

EIRQ1

EIRQ2

SCL2

IOVDD

Digital Gyro Data I/F Data In (4−wire Master)

Interrupt Input 1

−

IOVDD

Interrupt Input 2

AVDD30

2−wire serial I/F Clock Master

2−wire serial I/F Data Master

Hall Bias Output 1

SDA2

HLBO1

HLBO2

HLBO3

OPINM1

Hall Bias Output 2

Hall Bias Output 3

Hall Opamp Input Minus 1

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LC898129DP1XHTBG

Table 1. PIN DESCRIPTION (continued)

No.

OPINP1

OPINM2

OPINP2

OPINM3

OPINP3

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

AVDD30

AVSS

I/O

I/O Pwr

AVDD30

Function

Init

−

Hall Opamp Input Plus 1

Hall Opamp Input Minus 2

Hall Opamp Input Plus 2

Hall Opamp Input Minus 3

Hall Opamp Input Plus 3

OIS Driver Output

CL−AF Driver Output

Analog Power (2.7 V to 3.3 V)

Analog GND

Driver Power (1.8 V to 3.3 V)

Driver GND

PGND

LDPO

AVSS

PGND

Internal 1.38 V LDO Power Output

Analog GND

Driver GND

*Process when pins are not used

PIN TYPE “O” – Ensure that it is set to OPEN.

PIN TYPE “I” – OPEN is inhibited. Ensure that it is connected to the V or V even when it is unused.

(Please contact onsemi for more information about selection of V or V .)

PIN TYPE “B” – If you are unsure about processing method on the pin description of pin layout table, please contact us.

Note that incorrect processing of unused pins may result in defects.

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LC898129DP1XHTBG

ELECTRICAL CHARACTERISTICS

Table 2. ABSOLUTE MAXIMUM RATINGS (AVSS = 0 V, PGND = 0 V)

Parameter

Symbol

Conditions

Ta ≤ 25°C

Ratings

−0.3 to 4.6

Unit

Power supply voltage

30 max

max

Input/Output voltage

V 30, V 30

−0.3 to V 30 + 0.3

, V

−0.3 to V + 0.3

V , V

−0.3 to V + 0.3

IOO

Storage temperature

Tstg

−55 to 125

°C

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

Table 3. ALLOWABLE OPERATING RATINGS (Ta = −30 to 85°C, AVSS = 0 V, PGND = 0 V)

Parameter

3.0 V POWER SUPPLY (AVDD30)

Power supply voltage

Symbol

Min

Typ

Max

Unit

2.7

2.8

3.3

Input voltage range

INA

−

3.0 V POWER SUPPLY (VM) (Note 1)

Power supply voltage

1.8

2.8

3.3

Input voltage range

INM

−

1.8 V POWER SUPPLY (IOVDD)

Power supply voltage

1.7

1.8

3.3

Input voltage range

INI

−

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

1. Three VM pins should be connected.

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LC898129DP1XHTBG

Table 4. D.C. CHARACTERISTICS: INPUT/OUTPUT

(Ta = −30 to 85°C, AVSS = 0 V, PGND = 0 V, AVDD30 = 2.7 to 3.3 V, IOVDD = 1.7 to 3.3 V)

Parameter

Symbol

VIH

Conditions

Min

Typ

−

Max

Unit

Applicable Pins

High−level input voltage

Low−level input voltage

High−level input voltage

Low−level input voltage

High−level input voltage

Low−level input voltage

High−level output voltage

CMOS

schmitt

0.7 IOVDD

−

SCL, SDA, SSB,

SCLK, MOSI, MISO,

EIRQ1, EIRQ2

VIL

−

0.3 IOVDD

VIH

CMOS

schmitt

1.4

−

SCL2, SDA2

VIL

−

0.4

VIH

CMOS

schmitt

0.7 AVDD30

−

MON1, MON2

VIL

−

0.3 AVDD30

VOH

IOH = −3 mA

IOVDD − 0.2

−

SDA, SSB, SCLK,

MOSI, MISO, EIRQ1,

EIRQ2

Low−level output voltage

VOL

IOL = 3 mA

−

0.2

SCL, SDA, SSB,

SCLK, MOSI, MISO,

EIRQ1, EIRQ2

High−level output voltage

Low−level output voltage

High−level output voltage

Low−level output voltage

Analog input voltage

VOH

VOL

VOH

VOL

VAI

IOH = −3 mA

IOL = 3 mA

IOH = −2 mA

IOL = 2 mA

AVDD30 − 0.2

AVSS

−

SCL2, SDA2

0.2

−

MON1, MON2

0.2

AVDD30

MON1, MON2,

OPINP1, OPINM1,

OPINP2, OPINM2,

OPINP3, OPINM3

Pull Up resistor

Rup

Rdn

−

250

SSB, SCLK, MOSI,

MISO, EIRQ1,

EIRQ2, MON1,

Pull Down resistor

MON2, SCL2, SDA2

Table 5. DRIVER OUTPUT (Ta = 25°C, AVSS = 0 V, PGND = 0 V, AVDD30 = VM = 2.8 V)

Parameter

Symbol

Condition

Min

190

Typ

200

150

Max

210

Unit

Output Current OUT1~OUT4

Output Current OUT5, OUT6

Ifull

Full code

Full code, OP−AF (bidirection)

142.5

157.5

Table 6. NON−VOLATILE MEMORY CHARACTERISTICS

Operating temperature

Topr1

Topr2

Read for FLASH

−30~85

°C

Program & Erase for FLASH

−10~65 (Note 2)

Item

Symbol

Condition

Min

−

Typ

−

Max

Unit

Cycles

Years

Applicable Circuit

Endurance

1000

Flash Memory

Data retention

Write time

−

tWT

−

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

2. All drivers must be in the standby state.

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LC898129DP1XHTBG

AC CHARACTERISTICS

Power Supply Timing

AVDD30

Min V

IOVDD

10 %

Vbot

Figure 3. V_DDSupply Timing

Table 7.

Item

Symbol

Min

−

Typ

−

Max

Units

Rise time

Wait time

Bottom Voltage

100

−

Vbot

−

0.2

Injection order between AVDD30, VM and IOVDD is below.

1.7 V

IOVDD

tIOAV

tAVIO

2.7 V

AVDD30

0.2 V

tAVVM

tVMAV

0.2 V

Figure 4.

Table 8.

Item

IOVDD ON to AVDD30 ON

AVDD30 ON to VM ON

Symbol

tIOAV

Min

Typ

−

Max

Units

−

tAVVM

tVMAV

tAVIO

−

VM OFF to AVDD30 OFF

AVDD30 OFF to IOVDD OFF

−

SDA, SCL, SSB, SCLK, MOSI, MISO, EIRQ1 and

EIRQ2 tolerate 3 V input at the time of IOVDD power off.

SCL2 and SDA2 tolerate 3 V input at the time of AVDD30

power off.

The data in the Flash memory may be rewritten

unintentionally if you do not keep specifications.

And it is forbidden to power off during Flash memory

access. The data in the Flash memory may be rewritten

unintentionally.

OIS,AF driver is recommended to set standby before VM

power off.

*Please make IOPRSTB(D0_0064h, bit0) = 0 before

turning OFF AVDD30 when AVDD30 is turned off with

keeping IOVDD on.

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LC898129DP1XHTBG

2−wire Serial Interface Timing

The 2−wire serial interface timing definition and electric

characteristics are shown below. The communication

protocol is compatible with I C. This circuit has clock

stretch function.

Static Address : 7’b0100100

tBUF

VIHmin

VILmax

SDA

SCL

tHD;STA

tHD;DAT tSU;DAT

tSU;STO

tSU;STA

tHD;STA

VIHmin

VILmax

tLOW

tHIGH

1/fSCL

Start Condition

Repeated Start Condition

Stop Condition Start Condition

Figure 5.

Table 9.

Standard−mode

Fast−mode

Fast−mode Plus

Min

−

Max

100

−

Min

Max

400

−

Min

−

Max

1000

−

Item

Symbol

fSCL

Units

kHz

SCL clock frequency

−

START condition hold time

SCL clock Low period

SCL clock High period

tHD;STA

tLOW

4.0

4.7

4.0

4.7

0.6

1.3

0.6

0.26

0.5

−

tHIGH

−

0.26

−

Setup time for repetition START condition

Data hold time

tSU;STA

tHD;DAT

−

3.45

0.9

0.45

(Note 3)

Data setup time

tSU;DAT

250

−

1000

300

−

100

−

300

−

120

−

SDA, SCL rising time

SDA, SCL falling time

STOP condition setup time

−

tSU;STO

tBUF

4.0

4.7

0.6

1.3

0.26

0.5

Bus free time between STOP and START

−

3. Although the I C specification defines a condition that 300 ns of hold time is required internally, this LSI is designed for a condition with

typ. 25 ns of hold time. If SDA signal is unstable around falling point of SCL signal, please implement an appropriate treatment on board,

such as inserting a resister.

ORDERING INFORMATION

†

Part Number

Package

Shipping

LC898129DP1XHTBG

WLCSP40

(Pb−Free, Halogen−Free)

4000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D

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MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

WLCSP40 1.60x4.15x0.33

CASE 567XS

ISSUE O

DATE 12 APR 2019

GENERIC

MARKING DIAGRAM*

XXXXXXXX

AWLYYWW

XXX = Specific Device Code

*This information is generic. Please refer to

device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “G”, may

or may not be present. Some products may

not follow the Generic Marking.

= Assembly Location

WL = Wafer Lot

YY = Year

WW = Work Week

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98AON05909H

WLCSP40 1.60x4.15x0.33

PAGE 1 OF 1

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

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For additional information, please contact your local Sales Representative at

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

LC898129DP1XHTBG [ONSEMI]

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