LE25S161XATAG [ONSEMI]
Serial Flash Memory;
ONSEMI 
LE25S161
Serial Flash Memory
16 Mb (2048K x 8)
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1. Overview
The LE25S161 is a SPI bus flash memory device with a 16M bit (2048K
8-bit) configuration. It uses a single power supply. While making the most
of the features inherent to a serial flash memory device, the LE25S161 is
housed in an 8-pin ultra-miniature package. All these features make this
device ideally suited to storing program in applications such as portable
information devices, which are required to have increasingly more
compact dimensions.
SOIC 8, 150mils
VSOIC8 NB
The LE25S161 also has a small sector erase capability which makes the
device ideal for storing parameters or data that have fewer rewrite cycles
and conventional EEPROMs cannot handle due to insufficient capacity.
WLCSP8, 2.92x1.53
UDFN8 4x3, 0.8P
2. Features
Operations power supply
Operating frequency
Temperature range
Serial interface
: 1.65 to 1.95V supply voltage range
: 70MHz (max)
: –40 to +90C
: SPI mode 0, mode 3 supported
Electronic Identification
Sector size
: JDEC ID, Device ID, Serial Flash Discoverable Parameter (SFDP)
: 4K bytes/small sector, 64K bytes/sector
Erase functions
Page program function
Status functions
: small sector erase (SSE), sector erase (SE), chip erase (CHE)
: 256 bytes/page
: Ready/Busy information, protect information
Low operation current
Erase time
Page program time (tPP)
: 5.0mA (Low-power program mode, typ), 3.5mA (Low-Power Read mode, typ)
: 10ms (SSE, typ), 15ms (SE, typ), 210ms (CHE, typ)
: 0.4ms/256 bytes (typ.), 0.7ms/256 bytes (max.)
Emergency shutdown of the current consumption
: transition to a standby state in less than 20s from the active by Write Suspend
: transition to a standby state in less than 40s from the active by Software Reset
: 100,000 erase/program cycles
: 20 years data retention period
High reliability
Package
: LE25S161MDTWG SOIC 8, 150 mils
: LE25S161FDTWG VSOIC8 NB
CASE 751BD
CASE 753AA
: LE25S161XATAG WLCSP8, 2.921.53 CASE 567LC
: LE25S161PCTXG UDFN8 43, 0.8P
CASE 506DC
: KGD
N/A
* This product is licensed from Silicon Storage Technology, Inc. (USA).
ORDERING INFORMATION
See detailed ordering and shipping information on page 54 of this data sheet.
© Semiconductor Components Industries, LLC, 2016
February 2016 - Rev. 1
1
Publication Order Number :
LE25S161/D
LE25S161
3. Package Types and Pin Configurations
CS
1
2
3
4
8
7
6
5
V
DD
HOLD
SCK
SO (SIO1)
WP
V
SI (SIO0)
SS
Top view
SOIC8 (LE25S161MDTWG)
VSOIC8 NB (LE25S161FDTWG)
V
DD
CS
8
7
6
5
1
2
3
4
HOLD
SO (SIO1)
WP
SCK
SI (SIO0)
V
SS
Top view
UDFN8 (LE25S161PCTXG)
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2
LE25S161
A
B
CS
SO/SIO1
WP
VDD
HOLD
SCK
A
B
VDD
CS
SO/SIO1
HOLD
C
D
WP
C
D
VSS
SI/SIO0
SI/SIO0
1
VSS
2
2
1
Top View
WLCSP8
Ball side View
WLCSP8
(LE25S161XATAG)
(LE25S161XATAG)
4
3
2
1
5
6
7
8
KGD
Pad No.
Name
CS
1
2
3
4
5
6
7
8
SO (SIO1)
WP
V
SS
SI (SIO0)
SCK
HOLD
V
DD
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3
LE25S161
4. Package Dimensions
unit : mm
LE25S161MDTWG
SOIC 8, 150 mils
CASE 751BD-01
ISSUE O
SYMBOL
MIN
NOM
MAX
1.35
A
1.75
A1
b
0.10
0.33
0.19
4.80
5.80
3.80
0.25
0.51
0.25
5.00
6.20
4.00
c
E1
E
D
E
E1
e
h
L
1.27 BSC
0.25
0.40
0º
0.50
1.27
8º
PIN # 1
IDENTIFICATION
TOP VIEW
D
h
A1
A
c
e
b
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
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4
LE25S161
Package Dimensions
unit : mm
LE25S161FDTWG
VSOIC8 NB
CASE 753AA
ISSUE O
D
NOTES:
NOTE 5
A
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2X
8
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.10mm IN EXCESS OF MAXIMUM MATERIAL
CONDITION.
4. DIMENSION D DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH,
PROTRUSIONS, OR GATE BURRS SHALL NOT
EXCEED 0.15mm PER SIDE. DIMENSION E DOES
NOT INCLUDE INTERLEAD FLASH OR
PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25mm PER
SIDE. DIMENSIONS D AND E ARE DETERMINED AT
DATUM F.
F
0.10 C D
5
NOTE 6
A1
NOTE 4
E
E1
2X 4 TIPS
L2
L
SEATING
PLANE
0.20
C
C
4
DETAIL A
1
8X
b
B
NOTE 5
M
0.25
C
A-B D
TOP VIEW
5. DATUMS A AND B ARE TO BE DETERMINED AT
DATUM F.
6. A1 IS DEFINED AS THE VERTICAL DISTANCE
FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
2X
0.10
C
A-B
NOTE 4
MILLIMETERS
DETAIL A
DIM MIN
MAX
0.85
0.05
0.51
0.25
D
8X
A
A1
b
0.65
0.10
C
0.10
C
0.31
0.17
c
D
E
E1
e
4.90 BSC
A
e
6.00 BSC
3.90 BSC
1.27 BSC
SEATING
PLANE
END VIEW
C
SIDE VIEW
L
0.40
1.27
L2
0.25 BSC
GENERIC
MARKING DIAGRAM*
8
RECOMMENDED
SOLDERING FOOTPRINT*
XXXXXXXXX
ALYWX
1
8X
1.52
7.00
XXXXX = Specific Device Code
A
L
Y
W
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb-Free Package
1
8X
0.60
1.27
PITCH
(Note: Microdot may be in either location)
DIMENSION: MILLIMETERS
*This information is generic. Please refer
to device data sheet for actual part
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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5
LE25S161
Package Dimensions
unit : mm
LE25S161XATAG
WLCSP8, 2.92x1.53
CASE 567LC
ISSUE A
NOTES:
B
D
E
A
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO THE SPHERICAL
CROWNS OF THE SOLDER BALLS.
PIN A1
REFERENCE
MILLIMETERS
DIM
A
A1
b
MIN
MAX
0.50
0.13
0.35
0.03
0.25
D
2.92 BSC
E
e
1.53 BSC
0.50 BSC
2X
0.10
0.10
C
2X
C
TOP VIEW
A
0.10
C
C
0.08
RECOMMENDED
SOLDERING FOOTPRINT*
A1
SIDE VIEW
SEATING
C
PLANE
NOTE 3
PACKAGE
OUTLINE
A1
e
e/2
0.50
PITCH
8X
b
0.05 C A B
0.03 C
8X
0.30
D
C
e
e/2
B
A
0.50
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
MountingTechniques Reference Manual, SOLDERRM/D.
1
2
BOTTOM VIEW
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6
LE25S161
Package Dimensions
unit : mm
LE25S161PCTXG
UDFN8, 4x3, 0.8P
CASE 506DC
ISSUE O
NOTES:
A
B
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
D
L
L
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30MM FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L1
PIN ONE
REFERENCE
E
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTIONS
2X
0.15
C
MILLIMETERS
DIM MIN
0.50
A1 0.00
MAX
0.60
0.05
2X
A
0.15
C
TOP VIEW
A3
b
D
D2 0.70
E
0.152 REF
0.25
0.35
0.90
0.30
EXPOSED Cu
MOLD CMPD
4.00 BSC
DETAIL B
A
0.10
0.08
C
C
3.00 BSC
E2 0.10
e
G
L
0.80 BSC
1.60 BSC
10X
(A3)
DETAIL B
NOTE 4
0.55
0.65
0.15
A1
ALTERNATE
SEATING
PLANE
C
CONSTRUCTIONS
L1
SIDE VIEW
GENERIC
G
MARKING DIAGRAM*
DETAIL A
2X
D2
0.10
XXXXX
XXXXX
AYWW
M
C A B
4
1
2X
E2
M
8X
L
0.10
C A B
XXXXX = Specific Device Code
8
5
8X
b
A
Y
= Assembly Location
= Year
e
M
M
0.10
0.05
C A B
e/2
WW
= Work Week
NOTE 3
C
= Pb-Free Package
BOTTOM VIEW
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
RECOMMENDED
SOLDERING FOOTPRINT*
2.60
8X
0.83
2X
1.00
3.30
PACKAGE
OUTLINE
2X
0.40
8X
0.40
1
0.80
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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7
LE25S161
5. Pin Description
Symbol
CS
Pin Name
IO
I
Description
The device becomes active when the logic level of this pin is low; it is deselected and placed in
standby status when the logic level of the pin is high.
Chip select
This pin controls the data input/output timing.
SCK
Serial clock
I
The input data and addresses are latched synchronized to the rising edge of the serial clock, and
the data is output synchronized to the falling edge of the serial clock.
The data and addresses are input from this pin, and latched internally synchronized to the rising
edge of the serial clock.
SI
Serial data input
I/O
I/O
(SIO0)
(Serial data input output)
(It changes into input/output pin during the Dual operation.)
The data stored inside the device is output from this pin synchronized to the falling edge of the
serial clock.
SO
Serial data output
(SIO1)
(Serial data input output)
( It changes into input/output pin during the Dual operation.)
WP
Write protect
Hold
I
I
The Write Status Register Protect (SRWP) takes effect when the logic level of this pin is low.
Serial communication is suspended when the logic level of this pin is low.
This pin supplies the 1.65 to 1.95V supply voltage.
HOLD
V
Power supply
Ground
DD
V
This pin supplies the 0V supply voltage.
SS
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LE25S161
6. Block Diagram
16M Bit
Flash EEPROM
Cell Array
Power
Circuit
Energy-
consumption
Control Unit
Memory Control Logic
Decoder Logic
Command
Logic
&
Serial-parallel conversion Logic
Serial interface
SCK
SI
(SIO0)
SO
(SIO1)
CS
WP
HOLD
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LE25S161
7. Device Operation
7-1. Standard SPI Modes
The read, erase, program and other required functions of the device are executed through the command registers. The
serial I/O corrugate is shown in "Figure 1. SPI Modes" and the command list are shown in "Table.1-1. Command Settings
(Standard SPI)". At the falling CS edge the device is selected, and serial input is enabled for the commands, addresses, etc.
These inputs are normalized in 8 bit units and taken into the device interior in synchronization with the rising edge of SCK,
which causes the device to execute operation according to the command that is input.
The LE25S161 supports both serial interface SPI mode 0 and SPI mode 3. At the falling CS edge, SPI mode 0 is
automatically selected if the logic level of SCK is low, and SPI mode 3 is automatically selected if the logic level of SCK
is high.
Figure 1. SPI Modes
CS
Mode3
SCK
Mode0
8CLK
SI
1st byte
2nd byte
Nth byte
LSB
(Bit0)
MSB
(Bit7)
High Impedance
DATA
DATA
SO
7-2. Dual SPI Modes
The LE25S161 supports Dual SPI operations when using "Dual Output Read (RDDO: 3Bh)", "Dual I/O Read (RDIO:
BBh)". The SI and SO pins change into the input/output pin (SIOx) during the Dual SPI modes. The command list is
shown in "Table.1-2. Command Settings (Dual SPI)".
Pin Configurations at Dual SPI Mode
Standard SPI
SI
SO
Dual SPI
SIO0
SIO1
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LE25S161
Table 1-1. Command Settings (Standard SPI) --- Max: 70MHz (except RDLP)
Description
1st byte
2nd byte
3rd byte
4th byte
5th byte
6th byte
Nth byte
Command
(clock number)
(0 - 7)
(8 - 15)
(16- 23)
(24 - 31)
(32 - 39)
(40 - 47)
(8N-8 to 8N-1)
WREN
WRDI
Write enable
06h
04h
05h
01h
Write disable
RDSR
WRSR
Read Status Register
Write Status Register
DATA
Low -Power Read
(Max: 33.33MHz)
RDLP
03h
A23-A16
A15-A8
A7-A0
RD (5)
X
RD (5)
RD (5)
RD (5)
RD (5)
RDHS
SSE
SE
High-Speed Read
0Bh
20h / D7h
D8h
A23-A16
A23-A16
A23-A16
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
Small Sector Erase (4KB)
Sector Erase (64KB)
Chip Erase (16M bits)
Normal Page Program
Low-Power Page Program
Write Suspend
CHE
PP
60h / C7h
02h
A23-A16
A15-A8
A7-A0
PD (7)
PD (7)
PD (7)
PPL
0Ah
WSUS
RESM
B0h
Resume
30h
Manufacture
(62h)
Memory
Capacity
(15h)
RJID
RID
Read JEDEC ID
9Fh
ABh
Type (16h)
Read Device ID
Device ID
(88h)
X
X
X
(Exit power down mode)
RSFDP
DP
Read SFDP
5Ah
B9h
A23-A16
A15-A8
A7-A0
X
RD (5)
RD (5)
Deep Power down
Exit Deep
EDP
ABh
Power down
RSTEN
RST
Reset Enable
Reset
66h
99h
Table 1-2. Command Settings (Dual SPI) --- Max: 50MHz
Description
1st byte
2nd byte
3rd byte
4th byte
5th byte
6th byte
Nth byte
Command
RDDO
(clock number)
(0 - 7)
(8 - 15)
(16- 23)
(24 - 31)
(32 - 39)
(40 - 47)
(8N-8 to 8N-1)
Dual Output Read
3Bh
A23-A16
A23-A8(8)
A15-A8
A7-A0
Z
RDD (6)
RDD (6)
A7-A0(8)
X, Z
,
RDIO
Dual I/O Read
BBh
RDD (6)
RDD (6)
RDD (6)
RDD (6)
Note:
1. "X" signifies "don’t care" (that is to say, any value may be input).
2. "Z" signifies "high-impedance".
3. The "h" following each code indicates that the number given is in hexadecimal notation.
4. Addresses A23 to A21 for all commands are "Don't care".
5. "RD" Read data on SO.
6. "RDD" Dual Read data:
SIO0=(Bit6, Bit4, Bit2, Bit0)
SIO1=(Bit7, Bit5, Bit3, Bit1)
7. "PD" Page Program data on SO.
8. Dual SPI address input from SIO0 and SIO1:
SIO0=(A22, A20, A18, A16, A14, A12, A10, A8, A6, A4, A2, A0)
SIO1=(A23, A21, A19, A17, A15, A13, A11, A9, A7, A5, A3, A1)
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LE25S161
8. Memory Organization
Table 2. Memory Organization
16M bits
Sector
small sector
(4KB)
address space
(A23 to A0)
(64KB)
Symbol :SE
31
Symbol :SSE
SSE[511]
to
1FF000h
1FFFFFh
SSE[496]
SSE[495]
to
1F0000h
1EF000h
1F0FFFh
1EFFFFh
30 to 6
SSE[96]
SSE[95]
to
SSE[80]
SSE[79]
to
SSE[64]
SSE[63]
to
SSE[48]
SSE[47]
to
060000h
05F000h
060FFFh
05FFFFh
5
4
3
2
1
050000h
04F000h
050FFFh
04FFFFh
040000h
03F000h
040FFFh
03FFFFh
030000h
02F000h
030FFFh
02FFFFh
SSE[32]
SSE[31]
to
020000h
01F000h
020FFFh
01FFFFh
SSE[16]
SSE[15]
to
010000h
00F000h
010FFFh
00FFFFh
SSE[4]
004000h
003800h
003000h
002800h
002000h
001800h
001000h
000800h
000000h
004FFFh
003FFFh
0037FFh
002FFFh
0027FFh
001FFFh
0017FFh
000FFFh
0007FFh
SSE[3]
SSE[2]
SSE[1]
SSE[0]
0
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LE25S161
9. Status Registers
The status registers hold the operating and setting statuses inside the device, and this information can be read by Read
Status Register (RDSR) and the protect information can be rewritten by Write Status Register (WRSR). There are 8 bits in
total, and "Table 3. Status registers" gives the significance of each bit.
Table 3. Status Registers
Bit
Name
Logic
Function
Power-on Time Information
0
0
1
0
1
0
1
0
1
0
1
0
Ready
RDY
Bit0
Erase/Program
Write disabled
Write enabled
Bit1
Bit2
Bit3
Bit4
WEN
BP0
BP1
BP2
0
Block protect information
Protected area switch
Nonvolatile information
Block protect
Bit5
Bit6
Bit7
TB
Nonvolatile information
Upper side/Lower side switch
1
0
1
0
Erase/Program is not suspended
Erase/Program suspended
SUS
0
Write Status Register enabled
SRWP
Nonvolatile information
1
Write Status Register disabled
Note: All non-volatile bits of the status registers-1 are set "0" in the factory.
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LE25S161
9-1. Contents of each status register
9-1-1. RDY (bit 0)
The RDY register is for detecting the write (Program, Erase and Write Status Register) end. When it is "1", the device is in
a busy state, and when it is "0", it means that write is completed.
9-1-2. WEN (bit 1)
The WEN register is for detecting whether the device can perform write operations. If it is set to "0", the device will not
perform the write operation even if the write command is input. If it is set to "1", the device can perform write operations
in any area that is not block-protected.
WEN can be controlled using the write enable (WREN) and write disable (WRDI). By inputting the write enable (WREN:
06h), WEN can be set to "1" by inputting the write disable (WRDI: 04h), it can be set to "0." In the following states, WEN
is automatically set to "0" in order to protect against unintentional writing.
• At power-on
• Upon completion of Erase (SSE, SE, or CHE)
• Upon completion of Page Program (PP or PPL)
• Upon completion of Write Status Register (WRSR)
* If a write operation has not been performed inside the LE25S161 because, for instance, the command input for any of
the write operations (SSE, SE, CHE, PP, PPL or WRSR) has failed or a write operation has been performed for a
protected address, WEN will retain the status established prior to the issue of the command concerned. Furthermore, its
state will not be changed by a read operation.
9-1-3. BP0, BP1, BP2, TB (bits 2, 3, 4, 5)
Block Protect: BP0, BP1, BP2 and TB are status register bits that can be rewritten, and the memory space to be protected
can be set depending on these bits. For the setting conditions, refer to "Table 4. Protected Level Setting Conditions".
BP0, BP1, and BP2 are used to select the protected area and TB to allocate the protected area to the higher-order address
area or lower-order address area.
Table 4. Protection Level Setting Conditions
Status Register Bits
Protected Level
Protected Block
Protected Area
TB
X
0
BP2
0
BP1
0
BP0
0
0
Whole area unprotected
Upper side 1/32 protected
Upper side 1/16 protected
Upper side 1/8 protected
Upper side 1/4 protected
Upper side 1/2 protected
Lower side 1/32 protected
Lower side 1/16 protected
Lower side 1/8 protected
Lower side 1/4 protected
Lower side 1/2 protected
Whole area protected
None
T1
T2
T3
T4
T5
B1
B2
B3
B4
B5
6
0
0
1
1F0000h to 1FFFFFh
1E0000h to 1FFFFFh
1C0000h to 1FFFFFh
180000h to 1FFFFFh
100000h to 1FFFFFh
000000h to 00FFFFh
000000h to 01FFFFh
000000h to 03FFFFh
000000h to 07FFFFh
000000h to 0FFFFFh
000000h to 1FFFFFh
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
X
1
1
X
Note: Chip Erase is enabled only when the protection level is 0.
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LE25S161
9-1-4. SUS (bit 6)
The SUS register indicates when Erase/Program operation has been suspended. The SUS becomes "1" when the
Erase/Program operation has been suspended (WSUS: B0h). The SUS is cleared to"0" by Resume (RESM:30h) or
re-erase/program (SSE, SE, CHE, PP, PPL).
9-1-5. SRWP (bit 7)
Write Status Register protect SRWP is the bit for protecting the status registers, and its information can be rewritten.
When SRWP is "1" and the logic level of the WP pin is low, the Write Status Register (WRSR: 01h) is ignored, and status
registers BP0, BP1, BP2, TB and SRWP are protected. When the logic level of the WP pin is high, the status registers are
not protected regardless of the SRWP state. The SRWP setting conditions are shown in "Table 5. SRWP Setting
Conditions".
Table 5. SRWP Setting Conditions
WP
Pin
SRWP
Status Register Protect State
Unprotected
0
1
0
1
0
Protected
Unprotected
1
Unprotected
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LE25S161
10. Description of Commands and Operations
A detailed description of the functions and operations corresponding to each command is presented below.
10-1. Read Status Register (RDSR)
The contents of the status registers can be read using the Read Status Register (RDSR). This command can be executed
even during the following operations.
• Erase (SSE, SE or CHE)
• Page Program (PP or PPL)
• Write Status Register (WRSR)
"Figure 2. Read Status Register (RDSR)" shows the timing waveforms.
The sequence of RDSR operation :
CS goes to low input RDSR command (05h)
Status Register data (SRWP, SUS, TB, BP2, BP1, BP0,WEN, RDY) out on SO
completed by CS=high
* The data output starts from the falling edge of SCK(7th clock)
This command outputs the contents of the status registers synchronized to the falling edge of the clock (SCK).
If the clock input is continued after bit0 (RDY) has been output, the data is output by returning to bit7 (SRWP) that was
first output, after which the output is repeated for as long as the clock input is continued. The data can be read by this
command at any time (even during a program, erase cycle). By setting CS to high, the device is deselected, and Read
JEDEC ID cycle is completed. While the device is deselected, the output pin SO is in a high-impedance state
Figure 2. Read Status Register (RDSR)
CS
Mode 3
0
1
2
3
4
5
6
7
8
15 16
23
SCK
SI
Mode 0
8CLK
05h
MSB
High Impedance
SO
DATA DATA DATA
MSB MSB MSB
● DATA: Status Resister, "Table 3 Status Register"
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10-2. Write Status Register (WRSR)
The information in status registers BP0, BP1, BP2, TB and SRWP can be rewritten using this command. bit0 ( RDY), bit1
(WEN) and bit6 (SUS) are read-only bits and cannot be rewritten. The information in bits BP0, BP1, BP2, TB and SRWP
is stored in the non-volatile memory, and when it is written in these bits, the contents are retained even at power-down.
"Figure 3. Write Status Register (WRSR)" shows the timing waveforms.
"Figure 31. Write Status Register Flowcharts" shows the flowcharts.
The sequence of WRSR operation :
CS goes to low input WRSR command (01h)
Status Register data input on SI
CS goes to high (be executed by the rising CS edge)
Erase and program are performed automatically inside the device by Write Status Register. So that erasing or other
processing is unnecessary before executing the command. By the operation of this command, the information in bits BP0,
BP1, BP2, TB and SRWP can be rewritten. Since bits bit0 (RDY), bit1 (WEN), bit 6 (SUS) of the status register cannot be
written, no problem will arise if an attempt is made to set them to any value when rewriting the status register. Write
Status Register ends can be detected by RDY of Read Status Register (RDSR). To initiate Write Status Register, the logic
level of the WP pin must be set high and status register WEN must be set to "1".
Self-timed
Write Cycle
Figure 3. Write Status Register (WRSR)
t
WRSR
CS
SCK
SI
Mode3
Mode0
0
1
2
3
4
5
6
7
8
15
8CLK
01h
DATA
MSB
High Impedance
SO
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LE25S161
10-3. Write Enable (WREN)
Before performing any of the operations listed below, the device must be placed in the write enable state.
• Erase (SSE, SE, CHE or CHE)
• Page Program (PP or PPL)
• Write Status Register (WRSR)
Operation is the same as for setting status register WEN to "1", and the state is enabled by this command.
"Figure 4. Write Enable (WREN)" shows the timing waveforms.
The sequence of WREN operation :
CS goes to low input WREN command (06h)
CS goes to high (be executed by the rising CS edge)
Figure 4. Write Enable (WREN)
CS
Mode3
0
1 2 3 4 5 6 7
SCK
SI
Mode0
8CLK
06h
MSB
High Impedance
SO
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LE25S161
10-4. Write Disable (WRDI)
This command sets status register WEN to "0" to prohibit unintentional writing. The write disable state (WEN "0") is
exited by setting WEN to "1" using the write enable (WREN: 06h).
"Figure 5. Write Disable (WRDI)" shows the timing waveforms.
The sequence of WRDI operation :
CS goes to low input WRDI command (04h)
CS goes to high (be executed by the rising CS edge)
Figure 5. Write Disable (WRDI)
CS
Mode3
0
1 2 3 4 5 6 7
SCK
SI
Mode0
8CLK
04h
MSB
High Impedance
SO
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LE25S161
Standard SPI Read
There are two Read commands, "Low-Power Read (RDLP: 03h)" and "High-Speed Read (RDHS: 0Bh)".
10-5. Standard SPI Read
There are two Read commands, Low-Power Read (RDLP) and High-Speed Read (RDHS).
10-5-1. Low-Power Read command (RDLP)
Maximum Clock frequency: 33.33MHz
This command is for reading data out.
"Figure 6. Low-Power Read (RDLP)" shows the timing waveforms.
The sequence of RDLP operation :
CS goes to low input RDLP command (03h) 3 Byte address (A23-A0) input on SI
the corresponding data out on SO
continuous data out (n-byte)
completed by CS=high
* The data output starts from the falling edge of SCK(31th clock)
The Address is latched on rising edge of SCK, and the corresponding data is shifted out on SO by the falling edge of SCK.
The address is automatically incremented to the next higher address after each byte data is shifted out. If the SCK input is
continued after the internal address arrives at the highest address (1FFFFFh), the internal address returns to the lowest
address (000000h). By setting CS to high, the device is deselected, and the read cycle is completed. While the device is
deselected, the output pin SO is in a high-impedance state.
Figure 6. Low-Power Read (RDLP)
CS
Mode3
0
1
2
3
4
5
6
7
8
15 16
23 24
31 32
39 40
47
SCK
SI
Mode0
8CLK
03h
Add
Add
Add
(A23-A16) (A15-A8)
(A7-A0)
Byte 1 Byte 2 Byte 3
DATA DATA DATA
High Impedance
SO
MSB
MSB
MSB
● Address A23 to A21 are "Don't care".
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LE25S161
10-5-2. High-Speed Read command (RDHS)
Maximum Clock frequency: 70MHz
This command is for reading data out at the high frequency operation.
"Figure 7. High-Speed Read (RDHS)" shows the timing waveforms.
The sequence of RDHS operation :
CS goes to low input RDHS command (0Bh) 3 Byte address (A23-A0) input on SI
1 byte dummy cycle the corresponding data out on SO
continuous data out (n-byte)
completed by CS=high
* The data output starts from the falling edge of SCK(39th clock)
The Address is latched on rising edge of SCK. It is necessary to add 1 dummy byte cycle after address is latched, and the
corresponding data is shifted out on SO by the falling edge of SCK. The address is automatically incremented to the next
higher address after each byte data is shifted out. If the SCK input is continued after the internal address arrives at the
highest address (1FFFFFh), the internal address returns to the lowest address (000000h). By setting CS to high, the device
is deselected, and the read cycle is completed. While the device is deselected, the output pin SO is in a high-impedance
state.
Figure 7. High-Speed Read (RDHS)
CS
Mode3
0
1
2
3
4
5
6
7
8
15 16
23 24
31 32
39 40
47 48
55
SCK
SI
Mode0
8CLK
0Bh
Add
Add
Add
X
(A23-A16) (A15-A8)
(A7-A0)
MSB
Byte 1 Byte 2 Byte 3
DATA DATA DATA
High Impedance
SO
MSB
MSB
MSB
● Address A23 to A21 are "Don't care".
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LE25S161
10-6. Dual read
There are two Dual read commands, the Dual Output Read (RDDO) and the Dual I/O Read (RDIO).
They achieve the twice speed-up from "High-Speed Read (RDHS: 0Bh)". The command list is shown in "Table.1-2.
Command Settings (Dual SPI)"
Pin Configurations at Dual SPI Mode
Standard SPI
SI
SO
Dual SPI
SIO0
SIO1
10-6-1. Dual Output Read command (RDDO)
Maximum Clock frequency: 50MHz
The SI and SO pins change into the input/output pin (SIOx) during this operation. It makes the data output x2 bit and has
achieved a high-speed output. bit7, 5, 3 and bit1are output from SIO0. bit6, 4, 2 and bit0 are output from SIO1.
"Figure 8. Dual Output Read (RDDO)" shows the timing waveforms.
The sequence of RDDO operation :
CS goes to low input RDDO command (3Bh) 3 Byte address (A23-A0) input on SI
1 byte dummy cycle the corresponding data out on SI/SIO0 and SO/SIO1
continuous data out (n-byte) per 4clock
completed by CS=high
* The data output starts from the falling edge of SCK(39th clock)
Output Data
SI/SIO0
SO/SIO1
bit6,4,2,0
bit7,5,3,1
The Address is latched on rising edge of SCK. It is necessary to add 1 dummy byte cycle after address is latched, and the
corresponding data is shifted out on SI/SIO0 and SO/SIO1 by the falling edge of SCK. The address is automatically
incremented to the next higher address after each byte data (4 clock cycles) is shifted out. If the SCK input is continued
after the internal address arrives at the highest address (1FFFFFh), the internal address returns to the lowest address
(000000h). By setting CS to high, the device is deselected, and the read cycle is completed. While the device is deselected,
the output pin SO is in a high-impedance state.
Figure 8. Dual Output Read (RDDO)
CS
Mode3
0
1
2
3
4
5
6
7
8
15 16
23 24
31 32
39 40
43 44
47
SCK
Mode0
8CLK
3Bh
Byte 1 Byte 2 Byte 3
DATA0 DATA0 DATA0
dummy
bit
Add
Add
Add
SIO0
SIO1
(A23-A16) (A15-A8)
(A7-A0)
MSB
4CLK
4CLK
High Impedance
DATA1
DATA1 DATA1
MSB
MSB
MSB
DATA0: bit6,bit4,bit2,bit0
DATA1: bit7,bit5,bit3,bit1
● Address A23 to A21 are "Don't care".
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LE25S161
10-6-2. Dual I/O Read command (RDIO)
Maximum Clock frequency: 50MHz
The SI and SO pins change into the input/output pin (SIOx) during this operation. It makes the address input and data
output x2 bit and has achieved a high-speed output. Add1 (A23, A21, -, A3 and A1) is input from SIO1 and Add0 (A22,
A20, -, A2 and A0) is input from SIO0. bit7, 5, 3 and bit1are output from SIO0. bit6, 4, 2 and bit0 are output from SIO1.
"Figure 9. Dual I/O Read (RDIO)" shows the timing waveforms.
The sequence of RDIO operation :
CS goes to low input RDIO command (BBh)
3 Byte address (A23-A0) input on SI/SIO0 and SO/SIO1 by 12 clock cycle
2 dummy clock (SI/SIO0 and SO/SIO1 are don’t care)
+ 2 dummy clock (must set SI/SIO0 and SO/SIO1 high impedance)
the corresponding data out on SI/SIO0 and SO/SIO
continuous data out (n-byte) per 4clock
completed by CS=high
* The data output starts from the falling edge of SCK(23th clock)
Input Address
A22,20,18 --,A2,A0
A23,21,19 --,A3,A1
Output Data
bit6,4,2,0
bit7,5,3,1
SI/SIO0
SO/SIO1
The Address is latched on rising edge of SCK. It is necessary to add 4 dummy clocks after address is latched,
2CLK of the latter half of the dummy clock is in the state of high impedance, the controller can switch I/O for this period.
The corresponding data is shifted out on SI/SIO0 and SO/SIO1 by the falling edge of SCK. The address is automatically
incremented to the next higher address after each byte data (4 clock cycles) is shifted out. If the SCK input is continued
after the internal address arrives at the highest address (1FFFFFh), the internal address returns to the lowest address
(000000h). By setting CS to high, the device is deselected, and the read cycle is completed. While the device is deselected,
the output pin SO is in a high-impedance state.
Figure 9. Dual I/O Read (RDIO)
CS
0
1
2
3
4
5
6
7
8
22 23 24
27 28
31
20 21
19
Mode3
Mode0
SCK
dummy
bit
8CLK
BBh
Byte 1 Byte2
Byte3
Add1:A22,A20-A2,A0
X
SIO0
SIO1
DATA0 DATA0 DATA0
MSB
4CLK
12CLK
2CLK
2CLK
X
High Impedance
Add2:A23,A21-A3,A1
DATA1 DATA1 DATA1
MSB
MSB
MSB
DATA0: bit6,bit4,bit2,bit0
DATA1: bit7,bit5,bit3,bit1
● Address A23 to A21 are "Don't care".
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LE25S161
10-7. Small Sector Erase (SSE)
Small Sector Erase is an operation that sets the memory cell data in any small sector to "1". A small sector consists of
4Kbytes.
"Figure 10. Small Sector Erase (SSE)" shows the timing waveforms.
"Figure 32. Small Sector Erase Flowcharts" shows the flowcharts.
The sequence of SSE operation :
CS goes to low input SSE command (20h or D7h) 3 Byte address (A23-A0) input on SI
CS goes to high (be executed by the rising CS edge)
* A20 to A12 are valid address
After the correct input sequence the internal erase operation is executed by the rising CS edge, and it is completed
automatically by the control exercised by the internal timer (tSSE). The end of erase operation can also be detected by
status register (RDY).
Figure 10. Small Sector Erase (SSE)
Self-timed
Erase Cycle
t
SSE
CS
Mode3
0
1
2
3
4
5
6
7
8
15 16
23 24
31
SCK
SI
Mode0
8CLK
20h / D7h
Add
Add
Add
(A23-A16) (A15-A8)
(A7-A0)
MSB
High Impedance
SO
● Address A23 to A21, A11 to A0 are "Don't care".
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LE25S161
10-8. Sector Erase (SE)
Sector Erase is an operation that sets the memory cell data in any sector to "1". A sector consists of 64Kbytes.
"Figure 11. Sector Erase (SE)" shows the timing waveforms.
"Figure 33. Sector Erase Flowcharts" shows the flowcharts.
The sequence of SE operation :
CS goes to low input SE command (D8h) 3 Byte address (A23-A0) input on SI
CS goes to high (be executed by the rising CS edge)
* A20 to A16 are valid address
After the correct input sequence the internal erase operation is executed by the rising CS edge, and it is completed
automatically by the control exercised by the internal timer (tSE). The end of erase operation can also be detected by
status register (RDY).
Figure 11. Sector Erase (SE)
Self-timed
Erase Cycle
t
SE
CS
Mode3
0
1
2
3
4
5
6
7
8
15 16
23 24
31
SCK
SI
Mode0
8CLK
D8h
Add
Add
Add
(A23-A16) (A15-A8)
(A7-A0)
MSB
High Impedance
SO
● Address A23 to A21 , A15 to A0 are "Don't care.
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LE25S161
10-9. Chip Erase (CHE)
Chip Erase is an operation that sets the memory cell data in all sectors to "1".
"Figure 12. Chip Erase (CHE)" shows the timing waveforms.
"Figure 34. Chip Erase Flowcharts" shows the flowcharts.
The sequence of CHE operation :
CS goes to low input CHE command (60h or C7h)
CS goes to high (be executed by the rising CS edge)
After the correct input sequence the internal erase operation is executed by the rising CS edge, and it is completed
automatically by the control exercised by the internal timer (tSE). The end of erase operation can also be detected by
status register (RDY).
Figure 12. Chip Erase (CHE)
Self-timed
Erase Cycle
t
CHE
CS
Mode3
Mode0
0
1 2 3 4 5 6 7
SCK
8CLK
60h / C7h
SI
MSB
High Impedance
SO
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LE25S161
10-10. Page Program
10-10-1. Normal Page Program (PP)
10-10-2. Low-Power Page Program (PPL)
There are two Page Program commands, Normal program (PP: 02h ) and Low-Power program (PPL: 0Ah) These two
commands are completely functionally the same. By selecting the Low-Power program (PPL), the operating current is
reduced, but the program cycle time is extended. (Iccpp > Iccppl , tPPL > tPP)
Page Program is an operation that programs any number of bytes from 1 to 256 bytes within the same sector page (page
addresses: A20 to A8). Before initiating Page Program, the data on the page concerned must be erased using Small Sector
Erase, Sector Erase, or Chip Erase. Page Program (PP, PPL) allows only previous erased data (FFh).
"Figure 13. Normal Page Program (PP)". "Figure 14. Low-power Page Program (PPL)" shows the timing waveforms.
"Figure 35. Page Program Flowcharts" shows the flowcharts.
The sequence of PP or PPL operation :
CS goes to low input PP command (02h) or PPL command (0Ah)
3 Byte address (A23-A0) input on SI
n-Byte data input on SI
CS goes to high (be executed by the rising CS edge)
The program data must be loaded in 1-byte increments. If the data loaded has exceeded 256 bytes, the 256 bytes loaded
last are programmed. After the correct input sequence the internal program operation is executed by the rising CS edge,
and it is completed automatically by the control exercised by the internal timer (tPP or tPPL). The end of program
operation can also be detected by status register (RDY).
Self-timed
Program Cycle
Figure 13. Normal Page Program (PP)
t
PP
CS
Mode3
Mode0
2079
0
1
2
3
4
5
6
7
8
15 16
23 24
31 32
39 40
47
SCK
Byte
256
8CLK
02h
Byte 1 Byte 2
PD PD
Add
Add
Add
SI
PD
(A23-A16) (A15-A8)
(A7-A0)
MSB
High Impedance
SO
● Address A23 to A21 are "Don't care".
Self-timed
Program Cycle
Figure 14. Low-Power Page Program (PPL)
t
PPL
CS
Mode3
0
1
2
3
2079
4
5
6
7
8
15 16
23 24
31 32
39 40
47
SCK
Mode0
Byte
256
8CLK
0Ah
Byte 1 Byte 2
PD PD
Add
Add
Add
SI
PD
(A23-A16) (A15-A8)
(A7-A0)
MSB
High Impedance
SO
● Address A23 to A21 are "Don't care".
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10-11. Write Suspend (WSUS)
The Write Suspend (WSUS) allow the system to interrupt Small Sector Erase (SSE), Sector Erase (SE), Chip Erase (CHE)
or Page Program (PP, PPL).
"Figure 15. Write Suspend (WSUS)" shows the timing waveforms.
The sequence of WSUS operation :
CS goes to low input WSUS command (B0h)
CS goes to high (be executed by the rising CS edge)
After the command has been input, the device becomes consumption current equivalent to standby within 20 us. The
recovery time (tRSUS) is needed before next command from suspend. The internal operation status could be checked by
using status register RDY bit or SUS bit, but the device will not accept another command until it is ready.
• The Write Suspend is valid Erase cycle (SSE, SE and CHE) or Program cycle (PP, PPL).
• If the Erase (SSE, SE, CHE) or Program (PP, PPL) entry during the suspension, the suspension will be canceled
automatically. And a new Erase (SSE, SE, CHE), Program (PP, PPL) will be executed. In this case, it is
necessary to erase/program the suspended area again.
• During Write Suspend, Read (RDSR, RDLP, RDHS, RDDO, RDIO) and Resume (RESM) can be accepted.
• If the Software Reset is executed during the suspension, the suspension will be canceled automatically.
Figure 15. Write Suspend (WSUS)
Recovery time
from Suspend
t
RSUS
CS
20us
Mode3
Mode0
0
1
2
3
4
5
6
7
3 4 5 6 7
0 1 2
SCK
8CLK
B0h
Next Command
(Read or Resume)
MSB
SI
MSB
High Impedance
SO
Operation Current
= Isb
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LE25S161
10-12. Resume (RESM)
This command (RESM) restarts erase cycle (SSE, SE, CHE) or program cycle (PP, PPL) that was suspended.
"Figure 16. Resume (RESM)" shows the timing waveforms.
The sequence of RESM operation :
CS goes to low input RESM command (30h)
CS goes to high (be executed by the rising CS edge)
The internal operation status could be checked by using status register RDY bit or SUS bit.
This command will be ignored if the previous Write Suspend operation was interrupted by unexpected power off or
re-erase/program (cancel of suspend) or Software Reset(RST). To execute Write Suspend (WSUS) again after Resume, it
is necessary to wait for some time (tSUS).
Figure 16. Resume (RESM)
Self-timed
Write Cycle
t
t
t
t
CHE/ SE/ SSE/
t
PP/ PPL
CS
Mode3
Mode0
0
1 2 3 4 5 6 7
SCK
8CLK
30h
SI
MSB
High Impedance
SO
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10-13. Read ID
Read ID is an operation that reads the manufacturer code (RJID) and device ID information (RID). These Read ID
commands are not accepted during writing. There are two methods of reading the silicon ID, each of which is assigned a
device ID.
10-13-1. Read JEDEC ID (RJID)
This command (RJID) is compatible with the JEDEC standard for SPI compatible serial memories.
"Table 6. JEDEC ID codes" lists the silicon ID codes.
"Figure 17. Read JEDEC ID (RJID)" shows the timing waveforms.
The sequence of RJID operation :
CS goes to low input RJID command (9Fh)
Manufacture code (62h) out on SO Memory type code (16h) out on SO
Memory capacity code out on SO (15h) Reserve code (00h)
completed by CS=high
* The 4-byte code is output repeatedly as long as clock inputs are present
* The data output starts from the falling edge of SCK(7th clock)
By setting CS to high, the device is deselected, and Read JEDEC ID cycle is completed. While the device is deselected,
the output pin SO is in a high-impedance state.
Table 6. JEDEC ID codes
Output code
62h
16h
Manufacturer code
Memory type
Memory capacity code
Reserve code
2 byte device ID
15h (16M Bit)
00h
Figure 17. Read JEDEC ID (RJID)
CS
Mode3
0
1
2
3
4
5
6
7
8
15 16
23 24
31 32
39
SCK
SI
Mode0
8CLK
9Fh
High Impedance
SO
00h
MSB
62h
MSB
62h
MSB
16h
MSB
15h
MSB
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10-13-2. Read Device ID (RID)
This command (RID) is an operation that reads the Device ID.
"Table 7. Device ID code" lists the device ID codes.
"Figure 18. Read Device ID (RID)" shows the timing waveforms.
The sequence of RID operation :
CS goes to low input RID command (ABh) 3 byte dummy cycle
Device ID (88h) out on SO
completed by CS=high
* The Device ID (88h) is output repeatedly as long as clock inputs are present
* The data output starts from the falling edge of SCK(31th)
By setting CS to high, the device is deselected, and Read ID cycle is completed. While the device is deselected, the output
pin SO is in a high-impedance state.
Table 7. Device ID code
Output Code
88h
1 byte device ID
(LE25S161)
Figure 18. Read Device ID (RID)
CS
Mode3
0
1
2
3
4
5
6
7
8
15 16
23 24
31 32
39
SCK
SI
Mode0
8CLK
ABh
X
X
X
High Impedance
SO
88h
MSB
88h
MSB
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10-14. Deep Power-down (DP)
The standby current can be further reduced with this command (DP).
"Figure 19. Deep Power-down (DP)" shows the timing waveforms.
The sequence of DP operation :
CS goes to low input DP command (B9h)
CS goes to high (be executed by the rising CS edge)
The deep power-down command issued during an internal write operation will be ignored.
The deep power-down state is exited using the deep power-down exit (EDP). All other commands are ignored.
Figure 19. Deep Power-down (DP)
Deep Power-down Standby
Standby current (Isb)
Current (Idsb)
CS
t
DP
Mode3
Mode0
0
1 2 3 4 5 6 7
SCK
8CLK
B9h
SI
MSB
High Impedance
SO
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10-15. Exit Deep Power-down (EDP) / Read Device ID (RDDI)
The Exit Deep Power-down (EDP) / Read Device ID (RID) command is a multi-purpose command. It can be used to exit
the device from the deep power-down state, or read the device ID information.
Exit Deep Power-down (EDP)
The exit deep power-down command consists only of the first byte cycle, and it is initiated by inputting (ABh).
"Figure 20. Exiting from Deep Power-down" shows the timing waveforms.
The sequence of EDP operation :
CS goes to low input EDP command (ABh)
CS goes to high (be executed by the rising CS edge)
Figure 20. Exiting from Deep Power-down (EDP)
Deep Power-down Standby
Standby current (Isb)
current (Idsb)
CS
t
RDP
Mode3
Mode0
0
1 2 3 4 5 6 7
SCK
8CLK
ABh
SI
MSB
High Impedance
SO
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LE25S161
Read Device ID (RDDI)
Also the exit from deep power-down is completed by one byte cycle or more of the Read Device ID (RID: ABh).
"Table 7. Device ID code" lists the device ID codes.
"Figure 21. Read Device ID " shows the timing waveforms.
The sequence of EDP & RID operation :
CS goes to low input RID command (ABh) 3 byte dummy cycle
Device ID out on SO
completed by CS=high
* The Device ID is output repeatedly as long as clock inputs are present
* The data output starts from the falling edge of SCK(31th clock)
By setting CS to high, the device is deselected, and Read ID cycle is completed. While the device is deselected, the output
pin SO is in a high-impedance state.
Figure 21. Read Device ID
Standby
Deep Power-down Standbycurrent (Idsb)
current (Isb)
CS
SCK
SI
t
RDP
Mode3
Mode0
0
1
2
3
4
5
6
7
8
31 32
39
24 Dummy
Bits
8CL
ABh
X
X
High Impedance
SO
Dev ID
Dev ID
Dev ID
MSB
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LE25S161
10-16. Software Reset
The Software Reset reset the device to the state just after power-on. This operation consists of two commands: the Reset
Enable (RSTEN) and the Reset command (RST).
"Figure 22. Software Reset" shows the timing waveforms.
The sequence of Software Reset operation :
CS goes to low input RSTEN command (66h)
CS goes to high
CS goes to low input RST command (99h)
CS goes to high (be executed by the rising CS edge)
When the Software Reset is executed, an internal write (erase/program) operation is cancel, a suspended status is reset,
and all volatility status register bits (WEN/ RDY/SUS) are reset. After the internal reset time (tRST), the device will
become stand-by state. If the Software Reset is executed during a write (erase/program) operation, any dates on the write
operation will be broken.
The Reset command must input just after input the Reset Enable command. If another command input after the Reset
Enable command, the Reset-Enable state will be invalid.
Figure 22. Software Reset
Internal reset time
(tRST)
CS
Mode3
0
1
2
3
4
5
6
7
0 1 2 3
4 5 6 7
SCK
Mode0
8CLK
66h
8CLK
99h
SI
MSB
High Impedance
MSB
SO
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LE25S161
10-17. Read SFDP (RSFDP)
The Read SFDP (Serial Flash Discoverable Parameter) is an operation that reads the parameter about device
configurations, available commands and other features. The SFDP parameters are stored in internal parameter tables.
These parameter tables can be interrogated by host system software to enable adjustments needed to accommodate
divergent features from multiple vendors. SFDP is a standard of JEDEC. JESD216. Rev 1.0.
"Table 8. SFDP Header" shows SFDP Header.
"Table 9. SFDP Parameter Table" shows SFDP Parameter Table.
"Figure 23. Read SFDP (RSFDP)" shows the timing waveforms.
The sequence of RSFDP operation :
CS goes to low input RSFDP command (5Ah) 3 Byte address (A23-A0) input on SI
1 byte dummy cycle the corresponding parameter out on SO
continuous parameter out (n-byte)
completed by CS=high
* A10 to A0 are valid address
* The parameter output starts from the falling edge of SCK(39th clock)
The Address is latched on rising edge of SCK. It is necessary to add 1 dummy byte cycle after address is latched, and the
corresponding parameter is shifted out on SO by the falling edge of SCK. The address is automatically incremented to the
next higher address after each byte parameter is shifted out. By setting CS to high, the device is deselected, and Read
SFDP cycle is completed. While the device is deselected, the output pin SO is in a high-impedance state.
Figure 23. Read SFDP (RSFDP)
CS
Mode3
0
1
2
3
4
5
6
7
8
15 16
23 24
31 32
39 40
47 48
55
SCK
SI
Mode0
8CLK
5Ah
Add
Add
Add
X
(A23-A16) (A15-A8)
(A7-A0)
MSB
Byte 1
Byte 2 Byte 3
High Impedance
SO
Param1 Param2 Param3
MSB MSB MSB
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LE25S161
Table 8. SFDP Header
SFDP Header 1st and 2nd DWORD
Byte Address
(Hex)
Data
(Hex)
Description
Comment
Bits
00h
01h
02h
03h
04h
05h
06h
07h
7:0
53h
46h
44h
50h
05h
01h
02h
FFh
15:8
50444653h
(SFDP)
SFDP Signature
23:16
31:24
7:0
SFDP Minor Revision Number
SFDP Major Revision Number
Number of Parameter Headers
Unused
Start from 00h
Start from 01h
15:8
02h indicates 3 parameters
23:16
31:24
1st Parameter Header (JDEC Basic Flash parameters)
Description
Byte Address
(Hex)
Data
(Hex)
Comment
Bits
7:0
ID number (JEDEC ID)
00h(JEDEC specified header)
Start from 00h
08h
00h
Parameter Table Minor Revision
Number
09h
15:8
00h
Parameter Table Major Revision
Number
Parameter Table Length
(in double word)
Start from 01h
0Ah
0Bh
23:16
31:24
01h
10h
How many DWORDs in the Parameter table
10h indicates 16 DWORDs
0Ch
0Dh
0Eh
0Fh
7:0
40h
00h
00h
FFh
First address of JEDEC Flash
Parameter table
Parameter Table Pointer (PTP)
Unused
15:8
23:16
31:24
2nd Parameter Header (Vender parameters 1)
Byte Address
(Hex)
Data
(Hex)
Description
Comment
Bits
7:0
ID number
(ON Semiconductor
manufacturer ID)
62h(ON Semiconductor manufacturer ID)
10h
62h
Parameter Table Minor Revision
Number
Parameter Table Major Revision
Number
Parameter Table Length
(in double word)
Start from 00h
Start from 01h
11h
12h
13h
15:8
23:16
31:24
00h
01h
04h
How many DWORDs in the Parameter table
04h indicates 4 DWORDs
14h
15h
16h
17h
7:0
C0h
00h
00h
FFh
First address of On Semiconductor
Parameter table
Parameter Table Pointer (PTP)
Unused
15:8
23:16
31:24
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LE25S161
Table 9. SFDP Parameter Tables
Parameter Table : JDEC Basic Flash Parameter Tables (from 1th DWORD to 4th DWORD)
Byte
Address
(Hex)
Data
(Binary)
Data
(Hex)
Description
Comment
Bits
1:0
00b: Reserved
01b: support 4 KB Erase
10b: Reserved
11b: not support 4KB Erase
Block/Sector Erase Sizes
Write Granularity
01b
0: 1Byte, 1:64 Byte or larger
2
3
1b
0b
Volatile Status Register Block Protect
bits
0: Non-volatile
1: Volatile
40h
E5h
0: use 50h opcode, 1: use 06h opcode
Note: If target flash status register is nonvolatile,
then bits 3 and 4 must be set to 00b.
Write Enable Instruction Select for
Writing to Volatile Status Register
4
0b
Unused
Contains 111b and can never be changed
7:5
15:8
16
111b
0010_0000b
1b
4KB Erase Instruction
(1-1-2) Fast Read
20h
41h
42h
43h
20h
91h
0=not support 1=support
00: 3Byte only, 01: 3 or 4Byte,
10: 4Byte only, 11: Reserved
Address Bytes
18:17
19
00b
0b
Double Transfer Rate (DTR)
Clocking
0=not support 1=support
(1-2-2) Fast Read
(1-4-4) Fast Read
(1-1-4) Fast Read
Unused
0=not support 1=support
0=not support 1=support
0=not support 1=support
20
21
1b
0b
22
0b
1b
23
Unused
31:24
1111_1111b
FFh
44h
45h
46h
47h
Flash Memory Density
16 M bits
31:0
4:0
-
00FFFFFFh
(1-4-4) Fast Read Number of Wait
states (dummy clocks)
(1-4-4) Fast Read Number of Mode
Clocks
0 0000b: Wait states (dummy Clocks) not support
000b: Mode Bits not support
0_0000b
48h
49h
4Ah
4Bh
4Ch
4Dh
4Eh
4Fh
00h
FFh
00h
FFh
08h
3Bh
04h
BBh
7:5
000b
(1-4-4) Fast Read Instruction
15:8
20:16
1111_1111b
0_0000b
(1-1-4) Fast Read Number of Wait
states (dummy clocks)
(1-1-4) Fast Read Number of Mode
Clocks
0 0000b: Wait states (dummy Clocks) not support
000b: Mode Bits not support
23:21
31:24
4:0
000b
(1-1-4) Fast Read Instruction
1111_1111b
0_1000b
(1-1-2) Fast Read Number of Wait
states (dummy clocks)
(1-1-2) Fast Read Number of Mode
Clocks
0 0000b: Wait states (dummy Clocks) not support
000b: Mode Bits not support
7:5
000b
(1-1-2) Fast Read Instruction
15:8
20:16
0011_1011b
0_0100b
(1-2-2) Fast Read Number of Wait
states (dummy clocks)
(1-2-2) Fast Read Number of Mode
Clocks
0 0000b: Wait states (dummy Clocks) not support
000b: Mode Bits not support
23:21
31:24
000b
(1-2-2) Fast Read Instruction
1011_1011b
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LE25S161
Parameter Table : JDEC Basic Flash Parameter Tables (from 5th DWORD to 8th DWORD)
Byte
Address
(Hex)
Data
(Binary)
Data
(Hex)
Description
Comment
Bits
(2-2-2) Fast Read
0=not support 1=support
0
3:1
4
0b
111b
0b
Reserved
Default all 1’s
50h
EEh
(4-4-4) Fast Read
Reserved
0=not support 1=support
Default all 1’s
7:5
111b
51h
52h
53h
54h
55h
FFh
FFh
FFh
FFh
FFh
Reserved
Default all 1’s
31:8
-
Reserved
Default all 1’s
15:0
-
(2-2-2) Fast Read Number of Wait
states (dummy clocks)
(2-2-2) Fast Read Number of Mode
Clocks
0 0000b: Wait states (dummy Clocks) not support
000b: Mode Bits not support
20:16
0_0000b
56h
00h
23:21
31:24
15:0
000b
(2-2-2) Fast Read Instruction
57h
1111_1111b
-
FFh
58h
59h
FFh
FFh
Reserved
Default all 1’s
(4-4-4) Fast Read Number of Wait
states (dummy clocks)
(4-4-4) Fast Read Number of Mode
Clocks
0 0000b: Wait states (dummy Clocks) not support
000b: Mode Bits not support
20:16
0_0000b
5Ah
00h
23:21
31:24
7:0
000b
(4-4-4) Fast Read Instruction
5Bh
5Ch
5Dh
5Eh
5Fh
1111_1111b
0000_1100b
0010_0000b
0001_0000b
1101_1000b
FFh
0Ch
20h
10h
D8h
Sector/block size = 2^N bytes
0Ch indicates 4Kbytes
Sector Type 1 Size
Sector Type 1 erase Instruction
Sector Type 2 Size
15:8
Sector/block size = 2^N bytes
10h indicates 64Kbytes
23:16
31:24
Sector Type 2 erase Instruction
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LE25S161
Parameter Table : JDEC Basic Flash Parameter Tables (from 9th DWORD to 12th DWORD)
Byte
Address
(Hex)
Data
(Binary)
Data
(Hex)
Description
Comment
Bits
Sector/block size = 2^N bytes
00h indicates not exist
Sector Type 3 Size
60h
61h
62h
63h
7:0
0000_0000b
1111_1111b
0000_0000b
1111_1111b
00h
FFh
00h
FFh
Sector Type 3 erase Instruction
Sector Type 4 Size
15:8
Sector/block size = 2^N bytes
00h indicates not exist
23:16
31:24
Sector Type 4 erase Instruction
SE (64K-Byte erase):
150ms=2*(n+1)*15ms
n=4
SSE (4K-Byte erase)
10ms: ((n+1)*1ms=10ms)
n=9
SE (64K-Byte erase)
15ms: ((n+1)*1ms=15ms)
n=14
Multiplier from typical erase time to
maximum erase time
3:0
0100b
64h
94h
70h
10:4
00_01001b
Sector Type 1 Erase, Typical time
Sector Type 2 Erase, Typical time
65h
66h
67h
17:11
24:18
00_01110b
00_00000b
00h
00h
Sector Type 3 Erase, Typical time
Sector Type 4 Erase, Typical time
-
-
31:25
3:0
00_00000b
0010b
(n+1)*0.3ms
Multiplier from typical time to max
time for Page or byte program
=0.9ms: n=2,
0.9ms > 0.7ms(spec)
68h
82h
E6h
07h
0Ch
Page Size
256Bytes=2^8
7:4
1000b
(n+1)*64µs
Page Program Typical time
13:8
1_00110b
=448us: n=6,
448µs > 400µs(spec)
69h
6Ah
15:14
18:16
Byte Program Typical time,
first byte
(n+1)*8us
=128us: n=15,
1_1111b
0_0000b
Byte Program Typical time,
additional byte
(count+1)*1µs/byte
=1us/byte: Count=0
(n+1)*16ms
23:19
Chip Erase, Typical time
Reserved
30:24
31
00_01100b
0b
=208ms: n=12
208ms = 210ms(spec)
6Bh
-
xxx0b: May not initiate a new erase anywhere
xxx1b: May not initiate
suspended page size
a new erase in the program
xx0xb: May not initiate a new page program anywhere
xx1xb: May not initiate a new page program in the program
suspended page size
x0xxb: Refer to vendor datasheet for read restrictions
x1xxb: May not initiate a read in the program suspended
page size
Prohibited Operations During
Program Suspend
3:0
1101b
0xxxb: Additional erase or program restrictions apply
1xxxb: The erase and program restrictions in bits 1:0 are
sufficient
6Ch
FDh
xxx0b: May not initiate a new erase anywhere
xxx1b: May not initiate
suspended sector size
a new erase in the erase
xx0xb: May not initiate a page program anywhere
xx1xb: May not initiate
suspended sector size
x0xxb: Refer to vendor datasheet for read restrictions
x1xxb: May not initiate a read in the erase suspended
sector size
a page program in the erase
Prohibited Operations During Erase
Suspend
7:4
1111b
0xxxb: Additional erase or program restrictions apply
1xxxb: The erase and program restrictions in bits 5:4 are
sufficient
Reserved
-
8
0b
Program Resume to
Suspend Interval
6Dh
12:9
0000b
80h
<64µs: (count+1)*64µs, count=0
15:13
19:16
Suspend in-progress
Program max latency
10_00100b
0000b
40µs: ((4+1)*8us=40µs)
6Eh
6Fh
08h
44h
Erase Resume to
Suspend Interval
Suspend in-progress
erase max latency
23:20
<64µs: (count+1)*64µs, count=0
40µs: ((4+1)*8µs=40us)
30:24
31
10_00100b
0b
Suspend /resume supported
0=support 1=not support
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LE25S161
Parameter Table : JDEC Basic Flash Parameter Tables (from 13th DWORD to 16th DWORD)
Byte
Address
(Hex)
Data
(Binary)
Data
(Hex)
Description
Comment
Bits
Program Resume Instruction
(program operation)
Program Suspend Instruction
(program operation)
Resume Instruction
(write or erase type operation)
30h (as same as erase resume)
B0h (as same as erase suspend)
30h (as same as program resume)
B0h (as same as program suspend)
70h
71h
72h
73h
7:0
0011_0000b
1011_0000b
0011_0000b
30h
B0h
30h
B0h
15:8
23:16
Suspend Instruction
(write or erase type operation)
31:24
1:0
1011_0000b
00b
Reserved
74h
04h
Status Register Polling
Device Busy
Use legacy polling by reading the Status Register
with 05h instruction
7:2
0000_01b
Exit Deep Power down to next
operation delay
10_00100b
1010_1011b
1011_1001b
14:8
40µs: ((4+1)*8µs=40µs)
75h
76h
C4h
15
22:16
23
Exit Deep Power down Instruction
Enter Deep Power down Instruction
ABh
B9h
D5h
5Ch
00h
30:24
31
77h
78h
Deep Power down Supported
0=support 1=not support
-
0b
0000b
0000b
0b
(4-4-4) Mode Disable Sequences
3:0
7:4
(4-4-4) Mode Enable Sequences
-
8
(0-4-4) Mode supported
(0-4-4) Mode Exit Method
(0-4-4) Mode Entry Method
Quad Enable requirements (QER)
Hold and WP Disable
0=not support 1=support
79h
9
0b
00h
-
15:10
19:16
22:20
23
00_0000b
0000b
000b
-
00b:not have a QE bit
7Ah
7Bh
00h
00h
0: not supported
-
0b
Reserved
31:24
0000_0000b
xxx_xxx1b: Non-Volatile Status Register 1, powers-up to
last written value, use
instruction 06h to enable write
xx1_xxxxb: Status Register 1 contains a mix of volatile and
non-volatile bits. The 06h instruction is used to enable
writing of the register.
Volatile or Non-Volatile Register and
Write Enable Instruction for Status
Register 1
6:0
001_1001b
7Ch
19h
Reserved
-
7
0b
Soft Reset and
Rescue Sequence Support
Issue reset enable instruction 66h, and then issue
reset instruction 99h.
13:8
01_0000b
7Dh
10h
15:14
23:16
31:24
00b
Exit 4-Byte Addressing
Enter 4-Byte Addressing
7Eh
7Fh
0000_0000b
0000_0000b
00h
00h
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LE25S161
Parameter Table : Vender(ON Semiconductor) Parameter 1 Tables (from 1th DWORD to 4th DWORD)
Byte
Data
(Hex)
LE25S161
Data
(Binary)
Description
Comment
Address
(Hex)
Bits
1900h=1.900V
1950h=1.950V
2000h=2.000V
2200h=2.200V
1600h=1.600V
1650h=1.650V
1700h=1.700V
1800h=1.800V
2400h=2.400V
50h
19h
2700h=2.700V
3000h=3.000V
3600h=3.600V
20000h=2.000V
22000h=2.200V
23000h=2.300V
27000h=2.700V
C0h
C1h
Supply Maximum Voltage
15:0
-
-
50h
16h
C2h
C3h
Supply Minimum Voltage
31:16
0=not support
1= support
0=active logic is 0
1=active logic is 1
0=not support
1= support
0=active logic is 0
1=active logic is 1
0=not support
1= support
RESET Pin
0
1
2
3
4
0b
0b
1b
0b
1b
RESET Active Logic Level
HOLD Pin
14h
C4h
HOLD Active Logic Level
WP Pin
0=active logic is 0
1=active logic is 1
WP Active Logic Level
Reserved
5
0b
00b
7:6
00b
FFh
FFh
FFh
C5h
C6h
C7h
1111_1111b
1111_1111b
1111_1111b
Reserved
All FFh
9Fh
31:8
9Fh
62h
JDEC ID Operation code
C8h
C9h
7:0
1001_1111b
0110_0010b
JDEC ID Read Data
(Manufacture code)
JDEC ID Read Data
(Memory type)
JDEC ID Read Data
(Memory capacity code)
62h (ON Semiconductor)
16h
15:8
CAh
CBh
23:16
31:24
0001_0110b
0001_0101b
16h
15h
15h (16M bits)
Device ID Operation code
Device ID Read Data
ABh
CCh
CDh
7:0
1010_1011b
1000_1000b
ABh
88h
88h(LE25S161)
15:8
CEh
CFh
1111_1111b
1111_1111b
FFh
FFh
Reserved
All FFh
31:16
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LE25S161
11. Hold Function
Using the HOLD pin, the hold function suspends serial communication (it places it in the hold status). "Figure 24. HOLD
Function" shows the timing waveforms. The device is placed in the hold status at the falling HOLD edge while the logic
level of SCK is low, and it exits from the hold status at the rising HOLD edge. When the logic level of SCK is
high, HOLD must not rise or fall. The hold function takes effect when the logic level of CS is low, the hold status is exited
and serial communication is reset at the rising CS edge. In the hold status, the SO output is in the high-impedance state,
and SI and SCK are "don't care".
Figure 24. HOLD Function
Active
HOLD
Active
CS
t
t
HS
HS
SCK
t
t
HH
HH
HOLD
SO
t
t
HLZ
HHZ
High Impedance
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LE25S161
12. Power-on
In order to protect against unintentional writing, CS must be within at V -0.3 to V +0.3 on power-on. After
DD
DD
power-on, the supply voltage has stabilized at V
The device is in the standby state after power is turned on.
(min) or higher, and waits for t
before CS is driven to "Low".
DD
VSL
Figure 25. Power-on Timing
V
DD
V
V
(Max)
DD
DD
Program, Erase and Write Commands are Ignored
CS
Chip Select ( ="L") is Not Allowed
(Min)
tVSL
Read Command is
allowed
Full Access Allowed
Reset
State
V
WI
t
PUW
0V
time
Power-up timing
spec
Parameter
CS
Symbol
unit
min
300
max
t
µs
µs
V
V
(Min) to
Low
VSL
DD
Time to Write Operation
Operation Inhibit Voltage
t
100
1.0
500
1.5
PUW
V
WI
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LE25S161
13. Hardware Data Protection
LE25S161 incorporates a power-on reset function. The following conditions must be met in order to ensure that the power
reset circuit will operate stably.
No guarantees are given for data in the event of an instantaneous power failure occurring during the writing period.
Figure 26. Power-down Timing
V
DD
V
V
(Max)
DD
DD
(Min)
t
PD
0V
vBOT
Power-down timing
spec
Parameter
Symbol
unit
min
10
max
0.2
power-down time
t
ms
V
PD
power-down voltage
V
BOT
14. Software Data Protection
The LE25S161 eliminates the possibility of unintentional operations by not recognizing commands under the following
conditions.
• When a write command is input and the rising CS edge timing is not in a byte cycle (8 CLK units of SCK)
• When the Page Program data is not in 1-byte increments
• When the Write Status Register command is input for 2 bytes cycles or more
15. Decoupling Capacitor
0.1µF ceramic capacitor must be provided to each device and connected between V
device will operate stably.
and V in order to ensure that the
SS
DD
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LE25S161
16. Specifications
16-1. Absolute Maximum Ratings
Parameter
Maximum supply voltage
DC voltage (all pins)
Storage temperature
Symbol
Conditions
Ratings
unit
V
With respect to V
With respect to V
−0.5 to +2.6
SS
SS
−0.5 to V +0.5
V
DD
Tstg
−55 to +150
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
16-2. Operating Conditions
Parameter
Symbol
Conditions
Ratings
unit
V
Operating supply voltage
1.65 to 1.95
Operating
−40 to +90
°C
ambient temperature
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
16-3. Data retention, Rewriting cycles
Parameter
Symbol
cycRW
tDRET
condition
min
100,000
100,000
20
max
unit
Status resister write
Program/Erase
cycles/
Sector
Rewrite Cycles
Data retention
year
16-4. Pin Capacitance at Ta=25°C, f=1MHz
Ratings
max
12
Parameter
Symbol
Conditions
unit
Output pin capacitance
Input pin Capacitance
C
V
V
=0V
SO
pF
pF
SO
C
=0V
IN
6
IN
Note: These parameter values do not represent the results of measurements undertaken for all devices but rather values for
some of the sampled devices.
16-5. AC Test Conditions
Input pulse level··········· 0.2V
Input rising/falling time ·· 5ns
to 0.8V
DD
DD
Input timing level ········· 0.3V , 0.7V
DD
DD
Output timing level ······· 1/2×V
Output load················· 15pF
DD
Note: As the test conditions for "typ", the measurements are conducted using 1.8V for V
at room temperature.
DD
Input / Output timing level
0.7VDD
Input level
0.8VDD
0.2VDD
1/2VDD
0.3VDD
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LE25S161
16-6. DC Characteristics
V
=1.65 to 1.95V
Ratings
DD
Parameter
Symbol
Conditions
unit
min
typ
max
4.5
Low-Power Read
(RDLP: 03h)
33.33MHz
33.33MHz
70MHz
3.5
4.0
6.0
5.0
6.0
mA
mA
mA
mA
mA
5.5
7.0
7.0
8.0
SCK=
0.1V /0.9V
DD
,
High-Speed Read
(RDHS: 0Bh)
DD
Read mode
HOLD=WP=
I
CCR
operating current
0.9V
,
DD
SO=open
Dual Output Read
(RDDO: 3Bh)
or
Dual I/O Read
(RDIO: BBh)
33.33MHz
50MHz
t
=max,
SSE
Average current
Small Sector Erase operating current
Sector Erase operating current
Chip Erase operating current
I
3.5
3.5
4.0
4.5
4.5
5.0
mA
mA
mA
CCSSE
t
=max
SE
Average current
I
CCSE
t
=max
CHE
Average current
I
CCCHE
Normal
t
=max
PP
Average current
Program mode
operating current
I
6.5
5.0
7.5
6.5
mA
mA
CCPP
Low-Power
t
=max
PPL
Program mode
operating current
I
CCPPL
Average current
=V
,
=
=V
,
,
CS
HOLD WP
CMOS
DD
SS DD,
DD
SO=open,
I
9
50
12
µA
µA
SB
SI=V /V
standby current
Deep Power-down standby current
=V
,
=
=V
CS
HOLD WP
DD
SS DD,
DD
SO=open,
I
3.0
DSB
SI=V /V
Input leakage current
Output leakage current
Input low voltage
I
2.0
2.0
µA
µA
V
LI
I
LO
V
−0.3
0.3V
IL
DD
Input high voltage
V
0.7V
V
+0.3
V
IH
DD
DD
0.2
0.4
I
I
I
=100µA, V =V
DD DD
min
min
min
OL
OL
OH
Output low voltage
Output high voltage
V
V
V
OL
=1.6mA, V =V
DD DD
V
=−100µA, V =V
DD DD
V
-0.2
DD
OH
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
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47
LE25S161
16-7. AC Characteristics
Ratings
typ
Parameter
Symbol
unit
min
max
Low-Power Read (RDLP: 03h)
Dual Output Read (RDDO: 3Bh)
33.33
50
Clock
f
MHz
V/ns
CLK
Dual I/O Read
(RDIO: BBh)
frequency
Other instructions
70
0.1
11
Input signal rising/falling time
t
RF
33.33MHz
50MHz
SCK logic high level pulse
width
t
8
6
ns
ns
CLHI
70MHz
33.33MHz
50MHz
11
8
SCK logic low level pulse
width
t
CLLO
70MHz
6
CS
CS
active setup time
t
6
6
ns
ns
ns
ns
ns
ns
ns
ns
SLCH
not active hold time
t
CHSL
Data setup time
Data hold time
t
3
DS
t
3
DH
CS
CS
CS
wait pulse width
active hold time
t
20
6
CPH
t
CHSH
not active setup time
t
6
SHCH
CS
Output high impedance time from
t
8
10
8
CHZ
33.33MHz
50MHz
Output data time from SCK
Output data hold time
t
ns
V
8
70MHz
t
1
0
6
6
ns
ns
ns
ns
ns
ns
ns
ns
ms
HO
Output low impedance time from SCK
t
CLZ
HOLD
HOLD
setup time
hold time
t
HS
t
HH
HOLD
HOLD
Output low impedance time from
t
8
8
HLZ
Output high impedance time from
t
HHZ
WP
WP
setup time
hold time
t
20
20
WPS
t
WPH
Write status register time
t
5
8
WRSR
256Byte
0.40
0.70
Normal Page Programming
cycle time
t
ms
ms
0.14 +
PP
nByte
0.35 + n * 0.35/256
1.20
n * 0.26/256
0.60
256Byte
nByte
Low-Power Page Programming
cycle time
t
0.14 +
n * 0.46/256
10
PPL
0.50 + n * 0.70/256
Small Sector Erase cycle time
Sector Erase cycle time
Chip Erase cycle time
t
120
150
2400
40
ms
ms
ms
µs
SSE
t
15
SE
t
210
CHE
Recovery time from suspend
Deep Power-down time
Deep Power-down recovery time
Internal reset time
t
RSUS
t
5
µs
DP
t
40
µs
RDP
tRST
40
µs
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
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48
LE25S161
17. Timing waveforms
Figure 27. Serial Input Timing
t
CPH
CS
t
t
t
t
t
SHCH
CHSL
SLCH
CLHI CLLO
t
CHSH
SCK
t
t
DH
DS
SI
DATA VALID
High Impedance
High Impedance
SO
Figure 28. Serial Output Timing
CS
SCK
t
t
t
CHZ
CLZ
HO
SO
SI
DATA VALID
t
V
Figure 29. Hold Timing
CS
t
t
HS
t
t
HS
HH
HH
SCK
HOLD
SI
t
t
HLZ
HHZ
High Impedance
Figure 30. Status Resister Write Timing
CS
t
t
WPH
WPS
WP
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49
LE25S161
Figure 31. Write Status Register Flowcharts
Write Status Register
Start
06h
Write enable
(WREN)
01h
Set Write Status
Register command
(WRSR)
Data
Program start on rising
edge of CS
Set
05h
Read Status Register
command
(RDSR)
NO
Bit 0= "0" ?
YES
End of Write Status
Register
* Automatically placed in write disabled state
at the end of the Write Status Register
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50
LE25S161
Figure 32. Small Sector Erase Flowcharts
Figure 33. Sector Erase Flowcharts
Sector Erase
Start
Small Sector Erase
Start
Write enable
(WREN)
06h
Write enable
(WREN)
06h
Set Sector Erase
command
(SE)
Set Small Sector
Erase command
(SSE)
D8h
20h / D7h
Address 1
Address 2
Address 3
Address 1
Address 2
Address 3
Start erase on rising
edge of CS
Start erase on rising
edge of CS
Set
Set
05h
Read Status Register
command
(RDSR)
05h
Read Status Register
command
(RDSR)
NO
Bit 0 = "0" ?
YES
NO
Bit 0 = "0" ?
YES
End of erase
End of erase
* Automatically placed in write disabled
state at the end of the erase
* Automatically placed in write disabled
state at the end of the erase
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51
LE25S161
Figure 34. Chip Erase Flowcharts
Chip Erase
Start
Write enable
06h
(WREN)
Set Chip Erase
command
(CHE)
60h / C7h
Start erase on rising
edge of CS
Set
05h
Read Status Register
command
(RDSR)
Bit 0 = "0" ?
YES
NO
End of erase
* Automatically placed in write disabled state at
the end of the erase
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52
LE25S161
Figure 35. Page Program Flowcharts
Page Program
Start
06h
Write enable
(WREN)
02h or 0Ah
Address 1
Set Page Program
command
(PP/PPL)
*02h: Normal Program Mode (PP)
*0Ah: Low-Power Program Mode (PPL)
Address 2
Address 3
Data 0
Data n
Start program on rising
edge of CS
Set
05h
Read Status Register
command
(RDSR)
NO
Bit 0= "0" ?
YES
End of
programming
* Automatically placed in write disabled state at
the end of the programming operation.
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53
LE25S161
ORDERING INFORMATION
Device
Package
Shipping (Qty / Packing)
2000 / Tape & Reel
SOIC 8, 150 mils
(Pb-Free / Halogen Free)
LE25S161MDTWG
LE25S161FDTWG
LE25S161XATAG
LE25S161PCTXG
VSOIC8 NB
(Pb-Free / Halogen Free)
3000 / Tape & Reel
4000 / Tape & Reel
2000 / Tape & Reel
WLCSP8, 2.92x1.53
(Pb-Free / Halogen Free)
UDFN8 4x3, 0.8P
(Pb-Free / Halogen Free)
† For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel
Packaging Specifications Brochure, BRD8011/D. http://www.onsemi.com/pub_link/Collateral/BRD8011-D.PDF
ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiariesin the United States
and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of
SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without
further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitabilityof its products for any particular purpose,
nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including
without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can
and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are
not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicationsintended to support or
sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers,
employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was
negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all
applicable copyright laws and is not for resale in any manner.
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