LE25S161XBTAG_技术文档

DATA SHEET

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Serial Flash Memory

16 Mb (2048K x 8)

8

1

VSOIC8 NB

CASE 753AA

SOIC 8

CASE 751BD

LE25S161

Overview

The LE25S161 is a SPI bus flash memory device with a 16 Mbit

(2048K x 8−bit) configuration. It uses a single power supply. While

making the most of the features inherent to a serial flash memory

device, the LE25S161 is housed in an 8−pin ultra−miniature package.

All these features make this device ideally suited to storing program in

applications such as portable information devices, which are required

to have increasingly more compact dimensions.

1

UDFN8

CASE 506DC

WLCSP8

CASE 567YR

MARKING DIAGRAM

The LE25S161 also has a small sector erase capability which makes

the device ideal for storing parameters or data that have fewer rewrite

cycles and conventional EEPROMs cannot handle due to insufficient

capacity.

5S161

00

ALYW

5S16100 = Specific Device Code

Features

A

L

Y

W

= Assembly Site

= Wafer Lot Number

= Year of Production

= Work Week

• Operations Power Supply: 1.65 to 1.95 V Supply Voltage Range

• Operating Frequency: 70 MHz (Max)

• Temperature Range: –40 to +90°C

• Serial Interface: SPI Mode 0, Mode 3 Supported

ORDERING INFORMATION

• Electronic Identification: JDEC ID, Device ID, Serial Flash

†

Device

Package

Shipping

Discoverable Parameter (SFDP)

• Sector Size: 4 kbytes/Small Sector, 64 kbytes/Sector

• Erase Functions: Small Sector Erase (SSE), Sector Erase (SE),

Chip Erase (CHE)

LE25S161FDTWG

VSOIC8 NB

(Pb−Free /

Halide Free)

3000 /

Tape & Reel

LE25S161MDTWG

LE25S161PCTXG

LE25S161XBTAG

SOIC8

(Pb−Free /

Halide Free)

2000 /

Tape & Reel

• Page Program Function: 256 bytes/Page

• Status Functions: Ready/Busy Information, Protect Information

UDFN8

(Pb−Free /

Halide Free)

2000 /

Tape & Reel

• Low Operation Current: 5.0 mA (Low−power Program Mode, Typ),

3.5 mA (Low−Power Read Mode, Typ)

• Erase Time: 10 ms (SSE, Typ), 15 ms (SE, Typ),

210 ms (CHE, Typ)

• Page Program Time (tPP): 0.4 ms/256 bytes (Typ.),

0.7 ms/256 bytes (Max.)

• Emergency Shutdown of the Current Consumption:

Transition to a Standby State in Less than 20 ms from the

Active by Write Suspend

WLCSP8

(Pb−Free /

Halide Free)

4000 /

Tape & Reel

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

Transition to a Standby State in Less than 40 ms from the

Active by Software Reset

• High Reliability: 100,000 Erase/Program Cycles

20 Years Data Retention Period

• Package:

LE25S161FDTWG VSOIC8 NB, CASE 753AA

LE25S161MDTWG SOIC 8, 150 mils, CASE 751BD

LE25S161PCTXG UDFN8 4 x 3, 0.8P, CASE 506DC

LE25S161XBTAG WLCSP8, 2.92 x 1.53, CASE 567YR

KGD

*This product is licensed from Silicon Storage Technology, Inc. (USA).

1

Publication Order Number:

February, 2022 − Rev. 2

LE25S161/D

LE25S161

PACKAGE TYPES AND PIN CONFIGURATIONS

(Top View)

CS

1

8

V

DD

CS

1

8

V

DD

SO (SIO1)

WP

2

3

4

7

6

5

HOLD

SCK

SO (SIO1)

WP

2

3

4

7

6

5

HOLD

SCK

V

SS

SI (SIO0)

V

SS

SI (SIO0)

Figure 1. SOIC8 (LE25S161MDTWG) and

VSOIC8 NB (LE25S161FDTWG)

Figure 2. UDFN8 (LE25S161PCTXG)

(Top View)

(Ball Side View)

A

B

VDD

HOLD

SCK

CS

SO/SIO1

WP

VDD

A

B

CS

SO/

SIO1

HOLD

WP

SCK

C

D

C

D

SI/

SIO0

VSS

SI/SIO0

1

VSS

2

1

Figure 3. WLCSP8 (LE25S161XBTAG)

Table 1. PIN CONFIGURATION

Pad No.

Name

CS

A2

B2

C2

D2

D1

C1

B1

A1

SO (SIO1)

WP

V

SS

SI (SIO0)

SCK

HOLD

V

DD

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2

LE25S161

4

3

2

1

5

6

7

8

Figure 4. KGD

Table 2. PIN CONFIGURATION

Pad No.

Name

CS

1

2

3

4

5

6

7

8

SO (SIO1)

WP

V

SS

SI (SIO0)

SCK

HOLD

V

DD

PIN DESCRIPTION

Table 3. PIN DESCRIPTION

Symbol

Pin Name

IIO

Description

CS

Chip Select

I

The device becomes active when the logic level of this pin is low; it is deselected

and placed in standby status when the logic level of the pin is high.

SCK

Serial Clock

I

This pin controls the data input/output timing.

The input data and addresses are latched synchronized to the rising edge of the

serial clock, and the data is output synchronized to the falling edge of the serial

clock.

SI

Serial Data Input

I/O

The data and addresses are input from this pin, and latched internally synchronized

to the rising edge of the serial clock.

(SIO0)

(Serial Data Input Output)

(It changes into input/output pin during the Dual operation.)

SO

(SIO1)

Serial Data Output

(Serial Data Input Output)

The data stored inside the device is output from this pin synchronized to the falling

edge of the serial clock.

(It changes into input/output pin during the Dual operation.)

WP

Write Protect

I

The Write Status Register Protect (SRWP) takes effect when the logic level of this

pin is low.

HOLD

Hold

Serial communication is suspended when the logic level of this pin is low.

This pin supplies the 1.65 to 1.95 V supply voltage.

This pin supplies the 0 V supply voltage.

V

DD

Power Supply

Ground

V

SS

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3

LE25S161

BLOCK DIAGRAM

16 MBit

Flash EEPROM

Cell Array

Energy−

consumption

Control Unit

Power

Circuit

Memory Control Logic

Decoder Logic

Command

Logic

&

Serial−parallel Conversion Logic

Serial Interface

SI

(SIO0)

SO

(SIO1)

SCK

CS

WP

HOLD

Figure 5. Block Diagram

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4

LE25S161

DEVICE OPERATION

Standard SPI Modes

taken into the device interior in synchronization with the

rising edge of SCK, which causes the device to execute

operation according to the command that is input.

The LE25S161 supports both serial interface SPI mode 0

and SPI mode 3. At the falling CS edge, SPI mode 0 is

automatically selected if the logic level of SCK is low, and

SPI mode 3 is automatically selected if the logic level of

SCK is high.

The read, erase, program and other required functions of

the device are executed through the command registers. The

serial I/O corrugate is shown in “Figure 6. SPI Modes” and

the command list are shown in “Table 5. Command Settings

(Standard SPI)”. At the falling CS edge the device is

selected, and serial input is enabled for the commands,

addresses, etc. These inputs are normalized in 8 bit units and

CS

Mode3

SCK

Mode0

8CLK

1st byte

SI

Nth byte

2nd byte

LSB

(Bit0)

MSB

(Bit7)

High Impedance

DATA

SO

Figure 6. SPI Modes

Dual SPI Modes

Table 4. PIN CONFIGURATIONS AT DUAL SPI MODE

The LE25S161 supports Dual SPI operations when using

“Dual Output Read (RDDO: 3Bh)”, “Dual I/O Read (RDIO:

BBh)”. The SI and SO pins change into the input/output pin

(SIOx) during the Dual SPI modes. The command list is

shown in “Table 6. Command Settings (Dual SPI)”.

Standard SPI

Dual SPI

SIO0

SI

→

SO

SIO1

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5

LE25S161

Table 5. COMMAND SETTINGS (STANDARD SPI) − MAX: 70 MHz (EXCEPT RDLP)

st

nd

rd

th

Description

1

Byte

2

Byte

3

Byte

4

Byte

5

Byte

6

Byte

N

Byte

(Clock Number)

(0−7)

06h

04h

05h

01h

03h

(8−15)

(16−23)

(24−31)

(32−39)

(40−47)

(8N−8 to 8N−1)

Command

WREN

WRDI

Write Enable

Write Disable

RDSR

Read Status Register

Write Status Register

WRSR

RDLP

DATA

Low−Power Read

(Max: 33.33 MHz)

A23−A16

A15−A8

A7−A0

RD

(Note 5)

RD

(Note 5)

RD (Note 5)

RDHS

High−Speed Read

0Bh

A23−A16

X

RD

(Note 5)

SSE

SE

Small Sector Erase (4 kB)

Sector Erase (64 kB)

Chip Erase (16 Mbits)

Normal Page Program

Low−Power Page Program

Write Suspend

20h / D7h

D8h

A23−A16

A15−A8

A7−A0

CHE

PP

60h / C7h

02h

A23−A16

A15−A8

A7−A0

PD

(Note 6)

PD

(Note 6)

PD (Note 6)

PPL

0Ah

WSUS

RESM

RJID

B0h

Resume

30h

Manufacture

(62h)

Read JEDEC ID

9Fh

Memory

Type

(16h)

Capacity

(15h)

RID

Read Device ID

ABh

5Ah

X

Device ID

(88h)

(Exit power down mode)

RSFDP

Read SFDP

A23−A16

A15−A8

A7−A0

X

RD

(Note 5)

RD (Note 5)

DP

Deep Power Down

B9h

ABh

EDP

Exit Deep

Power Down

RSTEN

RST

Reset Enable

Reset

66h

99h

1. “X” signifies “don’t care” (that is to say, any value may be input).

2. “Z” signifies “high−impedance”.

3. The “h” following each code indicates that the number given is in hexadecimal notation.

4. Addresses A23 to A21 for all commands are “Don’t care”.

5. “RD” Read data on SO.

6. “PD” Page Program data on SO.

Table 6. COMMAND SETTINGS (DUAL SPI) − MAX: 50 MHz

st

nd

rd

th

Description

(Clock Number)

1

Byte

2

Byte

(8−15)

3

Byte

4

Byte

5

Byte

6

Byte

N

Byte

(0−7)

(16−23)

(24−31)

(32−39)

(40−47)

(8N−8 to 8N−1)

Command

RDDO

Dual Output Read

3Bh

A23−A16

A15−A8

A7−A0

Z

RDD

(Note 11)

RDD (Note 11)

RDIO

Dual I/O Read

BBh

A23−A8

A7−A0

RDD

(Note 11)

RDD

(Note 11)

RDD (Note 11)

(Note 12) (Note 12), (Note 11)

X, Z

7. “X” signifies “don’t care” (that is to say, any value may be input).

8. “Z” signifies “high−impedance”.

9. The “h” following each code indicates that the number given is in hexadecimal notation.

10.Addresses A23 to A21 for all commands are “Don’t care”.

11. “RDD” Dual Read data:

SIO0 = (Bit6, Bit4, Bit2, Bit0)

SIO1 = (Bit7, Bit5, Bit3, Bit1)

12.Dual SPI address input from SIO0 and SIO1:

SIO0 = (A22, A20, A18, A16, A14, A12, A10, A8, A6, A4, A2, A0)

SIO1 = (A23, A21, A19, A17, A15, A13, A11, A9, A7, A5, A3, A1)

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6

LE25S161

MEMORY ORGANIZATION

Table 7. MEMORY ORGANIZATION (16 Mbits)

Sector (64 kB)

Symbol: SE

Small Sector (4 kB)

Symbol: SSE

Address Space (A23 to A0)

31

SSE[511]

to

1FF000h

1FFFFFh

SSE[496]

SSE[495]

to

1F0000h

1EF000h

1F0FFFh

1EFFFFh

30 to 6

SSE[96]

SSE[95]

to

060000h

05F000h

060FFFh

05FFFFh

5

4

3

2

1

0

SSE[80]

SSE[79]

to

050000h

04F000h

050FFFh

04FFFFh

SSE[64]

SSE[63]

to

040000h

03F000h

040FFFh

03FFFFh

SSE[48]

SSE[47]

to

030000h

02F000h

030FFFh

02FFFFh

SSE[32]

SSE[31]

to

020000h

01F000h

020FFFh

01FFFFh

SSE[16]

SSE[15]

to

010000h

00F000h

010FFFh

00FFFFh

SSE[4]

SSE[3]

004000h

003800h

003000h

002800h

002000h

001800h

001000h

000800h

000000h

004FFFh

003FFFh

0037FFh

002FFFh

0027FFh

001FFFh

0017FFh

000FFFh

0007FFh

SSE[2]

SSE[1]

SSE[0]

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7

LE25S161

STATUS REGISTERS

The status registers hold the operating and setting statuses

inside the device, and this information can be read by Read

Status Register (RDSR) and the protect information can be

rewritten by Write Status Register (WRSR). There are 8 bits

in total, and “Table 8. Status registers” gives the significance

of each bit.

Table 8. STATUS REGISTERS

Bit

Name

Logic

Function

Ready

Power−on Time Information

Bit0

RDY

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

3

Erase/Program

Write disabled

Write enabled

Bit1

Bit2

Bit3

Bit4

Bit5

Bit6

Bit7

WEN

BP0

0

Block protect information

Protected area switch

Nonvolatile information

BP1

BP2

TB

Block protect

Upper side/Lower side switch

Nonvolatile information

SUS

SRWP

Erase/Program is not suspended

Erase/Program suspended

0

Write Status Register enabled

Write Status Register disabled

Nonvolatile information

13.All non−volatile bits of the status registers−1 are set “0” in the factory.

Contents of Each Status Register

• Upon completion of Page Program (PP or PPL)

RDY (Bit 0)

• Upon completion of Write Status Register (WRSR)

The RDY register is for detecting the write (Program,

Erase and Write Status Register) end. When it is “1”, the

device is in a busy state, and when it is “0”, it means that

write is completed.

*If a write operation has not been performed inside the

LE25S161 because, for instance, the command input for

any of the write operations (SSE, SE, CHE, PP, PPL or

WRSR) has failed or a write operation has been performed

for a protected address, WEN will retain the status

established prior to the issue of the command concerned.

Furthermore, its state will not be changed by a read

operation.

WEN (Bit 1)

The WEN register is for detecting whether the device can

perform write operations. If it is set to “0”, the device will

not perform the write operation even if the write command

is input. If it is set to “1”, the device can perform write

operations in any area that is not block−protected.

WEN can be controlled using the write enable (WREN)

and write disable (WRDI). By inputting the write enable

(WREN: 06h), WEN can be set to “1” by inputting the write

disable (WRDI: 04h), it can be set to “0.” In the following

states, WEN is automatically set to “0” in order to protect

against unintentional writing.

BP0, BP1, BP2, TB (Bits 2, 3, 4, 5)

Block Protect: BP0, BP1, BP2 and TB are status register

bits that can be rewritten, and the memory space to be

protected can be set depending on these bits. For the setting

conditions, refer to “Table 9. Protected Level Setting

Conditions”.

BP0, BP1, and BP2 are used to select the protected area

and TB to allocate the protected area to the higher−order

address area or lower−order address area.

• At power−on

• Upon completion of Erase (SSE, SE, or CHE)

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8

LE25S161

Table 9. PROTECTION LEVEL SETTING CONDITIONS

Status Register Bits

Protected

Level

TB

X

0

BP2

0

BP1

0

BP0

0

Protected Block

Protected Area

None

0

Whole area unprotected

Upper side 1/32 protected

Upper side 1/16 protected

Upper side 1/8 protected

Upper side 1/4 protected

Upper side 1/2 protected

Lower side 1/32 protected

Lower side 1/16 protected

Lower side 1/8 protected

Lower side 1/4 protected

Lower side 1/2 protected

Whole area protected

T1

T2

T3

T4

T5

B1

B2

B3

B4

B5

6

0

1

1F0000h to 1FFFFFh

1E0000h to 1FFFFFh

1C0000h to 1FFFFFh

180000h to 1FFFFFh

100000h to 1FFFFFh

000000h to 00FFFFh

000000h to 01FFFFh

000000h to 03FFFFh

000000h to 07FFFFh

000000h to 0FFFFFh

000000h to 1FFFFFh

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

1

X

14.Chip Erase is enabled only when the protection level is 0.

SUS (Bit 6)

are protected. When the logic level of the WP pin is high, the

status registers are not protected regardless of the SRWP

state. The SRWP setting conditions are shown in “Table 10.

SRWP Setting Conditions”.

The SUS register indicates when Erase/Program

operation has been suspended. The SUS becomes “1” when

the Erase/Program operation has been suspended (WSUS:

B0h). The SUS is cleared to “0” by Resume (RESM: 30h)

or re−erase/program (SSE, SE, CHE, PP, PPL).

Table 10. SRWP SETTING CONDITIONS

SRWP (Bit 7)

WP Pin

SRWP

Status Register Protect State

Unprotected

Write Status Register protect SRWP is the bit for

protecting the status registers, and its information can be

rewritten. When SRWP is “1” and the logic level of the WP

pin is low, the Write Status Register (WRSR: 01h) is

ignored, and status registers BP0, BP1, BP2, TB and SRWP

0

1

0

1

Protected

1

Unprotected

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9

LE25S161

DESCRIPTION OF COMMANDS AND OPERATIONS

A detailed description of the functions and operations

corresponding to each command is presented below.

→ Status Register data (SRWP, SUS, TB, BP2, BP1,

BP0,WEN, RDY) out on SO →→

→ completed by CS = high

*The data output starts from the falling edge of SCK (7th

clock)

Read Status Register (RDSR)

The contents of the status registers can be read using the

Read Status Register (RDSR). This command can be

executed even during the following operations.

• Erase (SSE, SE or CHE)

• Page Program (PP or PPL)

• Write Status Register (WRSR)

“Figure 7. Read Status Register (RDSR)” shows the

timing waveforms.

This command outputs the contents of the status registers

synchronized to the falling edge of the clock (SCK).

If the clock input is continued after bit0 (RDY) has been

output, the data is output by returning to bit7 (SRWP) that

was first output, after which the output is repeated for as long

as the clock input is continued. The data can be read by this

command at any time (even during a program, erase cycle).

By setting CS to high, the device is deselected, and Read

JEDEC ID cycle is completed. While the device is

deselected, the output pin SO is in a high−impedance state

The sequence of RDSR operation:

CS goes to low → input RDSR command (05h)

CS

Mode 3

0

1

2

3

4

5

6

7

8

15 16

23

SCK

SI

Mode 0

8CLK

05h

MSB

High Impedance

SO

DATA DATA DATA

MSB MSB MSB

• DATA: Status Resister, “Table 8. Status Register”

Figure 7. Read Status Register (RDSR)

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10

LE25S161

Write Status Register (WRSR)

“Figure 8. Write Status Register (WRSR)” shows the

timing waveforms.

“Figure 37. Write Status Register Flowcharts” shows the

flowcharts.

The information in status registers BP0, BP1, BP2, TB

and SRWP can be rewritten using this command. bit0

(RDY), bit1 (WEN) and bit6 (SUS) are read−only bits and

cannot be rewritten. The information in bits BP0, BP1, BP2,

TB and SRWP is stored in the non−volatile memory, and

when it is written in these bits, the contents are retained even

at power−down.

The sequence of WRSR operation:

CS goes to low → input WRSR command (01h)

→ Status Register data input on SI

→ CS goes to high (be executed by the rising CS edge)

Self−timed Write Cycle

t _WRSR

CS

Mode3

0

1

2

3

4

5

6

7

8

15

SCK

SI

Mode0

8CLK

01h

DATA

MSB

High Impedance

SO

Figure 8. Write Status Register (WRSR)

Write Enable (WREN)

Write Disable (WRDI)

Before performing any of the operations listed below, the

device must be placed in the write enable state.

• Erase (SSE, SE, CHE or CHE)

This command sets status register WEN to “0” to prohibit

unintentional writing. The write disable state (WEN “0”) is

exited by setting WEN to “1” using the write enable

(WREN: 06h).

“Figure 10. Write Disable (WRDI)” shows the timing

waveforms.

• Page Program (PP or PPL)

• Write Status Register (WRSR)

Operation is the same as for setting status register WEN

to “1”, and the state is enabled by this command.

“Figure 9. Write Enable (WREN)” shows the timing

waveforms.

The sequence of WRDI operation:

CS goes to low → input WRDI command (04h)

→ CS goes to high (be executed by the rising CS edge)

The sequence of WREN operation:

CS

CS goes to low → input WREN command (06h)

→ CS goes to high (be executed by the rising CS edge)

Mode3

0

1 2 3

4 5 6 7

SCK

SI

CS

Mode0

8CLK

04h

Mode3

0

1 2 3

4 5 6 7

SCK

SI

Mode0

MSB

8CLK

06h

High Impedance

SO

Figure 10. Write Disable (WRDI)

MSB

High Impedance

SO

Figure 9. Write Enable (WREN)

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11

LE25S161

Standard SPI Read

There are two Read commands, “Low−Power Read

(RDLP: 03h)” and “High−Speed Read (RDHS: 0Bh)”.

→ completed by CS = high

*The data output starts from the falling edge of SCK (31th

clock)

Low−Power Read command (RDLP) − Maximum Clock

Frequency: 33.33 MHz

This command is for reading data out.

“Figure 11. Low−Power Read (RDLP)” shows the timing

waveforms.

The Address is latched on rising edge of SCK, and the

corresponding data is shifted out on SO by the falling edge

of SCK. The address is automatically incremented to the

next higher address after each byte data is shifted out. If the

SCK input is continued after the internal address arrives at

the highest address (1FFFFFh), the internal address returns

to the lowest address (000000h). By setting CS to high, the

device is deselected, and the read cycle is completed. While

the device is deselected, the output pin SO is in a

high−impedance state.

The sequence of RDLP operation:

CS goes to low → input RDLP command (03h) → 3 Byte

address (A23 − A0) input on SI

→ the corresponding data out on SO

→ continuous data out (n−byte) →→

CS

Mode3

0

1

2

3

4

5

6

7

8

15 16

23 24

31 32

39 40 47

SCK

SI

Mode0

8CLK

03h

Add

(A23−A16) (A15−A8)

(A7−A0)

Byte 1 Byte 2 Byte 3

DATA DATA DATA

High Impedance

SO

MSB

• Address A23 to A21 are “Don’t care”.

Figure 11. Low−Power Read (RDLP)

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12

LE25S161

High−Speed Read Command (RDHS) − Maximum Clock

frequency: 70 MHz

This command is for reading data out at the high

frequency operation.

“Figure 12. High−Speed Read (RDHS)” shows the timing

waveforms.

The Address is latched on rising edge of SCK. It is

necessary to add 1 dummy byte cycle after address is

latched, and the corresponding data is shifted out on SO by

the falling edge of SCK. The address is automatically

incremented to the next higher address after each byte data

is shifted out. If the SCK input is continued after the internal

address arrives at the highest address (1FFFFFh), the

internal address returns to the lowest address (000000h). By

setting CS to high, the device is deselected, and the read

cycle is completed. While the device is deselected, the

output pin SO is in a high−impedance state.

The sequence of RDHS operation:

CS goes to low → input RDHS command (0Bh) → 3 Byte

address (A23 − A0) input on SI

→ 1 byte dummy cycle → the corresponding data out on SO

→ continuous data out (n−byte) →→

→ completed by CS = high

*The data output starts from the falling edge of SCK(39th

clock)

CS

Mode3

0

1

2

3

4

5

6

7

8

15 16

23 24

31 32

39 40

47 48

55

SCK

SI

Mode0

8CLK

0Bh

Add

X

(A23−A16) (A15−A8)

(A7−A0)

MSB

Byte 1 Byte 2 Byte 3

DATA DATA DATA

MSB MSB MSB

High Impedance

SO

• Address A23 to A21 are “Don’t care”.

Figure 12. High−Speed Read (RDHS)

Dual Read

→ 1 byte dummy cycle → the corresponding data out on

There are two Dual read commands, the Dual Output Read

(RDDO) and the Dual I/O Read (RDIO).

They achieve the twice speed−up from ”High−Speed

Read (RDHS: 0Bh)”. The command list is shown in

“Table 6. Command Settings (Dual SPI)”

SI/SIO0 and SO/SIO1

→ continuous data out (n−byte) per 4 clock →→

→ completed by CS = high

*The data output starts from the falling edge of SCK (39th

clock)

Output Data

Table 11. PIN CONFIGURATIONS AT DUAL SPI MODE

SI/SIO0

SO/SIO1 bit7, 5, 3, 1

bit6, 4, 2, 0

Standard SPI

Dual SPI

SIO0

The Address is latched on rising edge of SCK. It is

necessary to add 1 dummy byte cycle after address is

latched, and the corresponding data is shifted out on SI/SIO0

and SO/SIO1 by the falling edge of SCK. The address is

automatically incremented to the next higher address after

each byte data (4 clock cycles) is shifted out. If the SCK

input is continued after the internal address arrives at the

highest address (1FFFFFh), the internal address returns to

the lowest address (000000h). By setting CS to high, the

device is deselected, and the read cycle is completed. While

the device is deselected, the output pin SO is in a

high−impedance state.

SI

→

SO

SIO1

Dual Output Read Command (RDDO) − Maximum Clock

Frequency: 50 MHz

The SI and SO pins change into the input/output pin

(SIOx) during this operation. It makes the data output x2 bit

and has achieved a high−speed output. bit7, 5, 3 and bit1are

output from SIO0. bit6, 4, 2 and bit0 are output from SIO1.

“Figure13. Dual Output Read (RDDO)” shows the timing

waveforms.

The sequence of RDDO operation:

CS goes to low → input RDDO command (3Bh) → 3 Byte

address (A23 − A0) input on SI

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LE25S161

CS

Mode3

Mode0

0

1

2

3

4

5

6

7

8

15 16

23 24

31 32

39 40

43 44

47

SCK

8CLK

3Bh

Byte 1

Byte 2 Byte 3

dummy

bit

Add

DATA0 DATA0 DATA0

SIO0

SIO1

(A23−A16) (A15−A8)

(A7−A0)

MSB

4CLK

High Impedance

DATA1

DATA1 DATA1

MSB

DATA0: bit6, bit4, bit2, bit0

DATA1: dit7, bit5, bit3, bit1

• Address A23 to A21 are “Don’t care”.

Figure 13. Dual Output Read (RDDO)

Dual I/O Read Command (RDIO) − Maximum Clock

Frequency: 50 MHz

→ continuous data out (n−byte) per 4 clock →→

→ completed by CS = high

The SI and SO pins change into the input/output pin

(SIOx) during this operation. It makes the address input and

data output x2 bit and has achieved a high−speed output.

Add1 (A23, A21, −, A3 and A1) is input from SIO1 and

Add0 (A22, A20, −, A2 and A0) is input from SIO0. bit7, 5,

3 and bit1 are output from SIO0. bit6, 4, 2 and bit0 are output

from SIO1.

*The data output starts from the falling edge of SCK (23th

clock)

Input Address

Output Data

bit6, 4, 2, 0

bit7, 5, 3, 1

SI/SIO0

A22, 20, 18 −, A2, A0

SO/SIO1 A23, 21, 19 −, A3, A1

The Address is latched on rising edge of SCK. It is

necessary to add 4 dummy clocks after address is latched,

2CLK of the latter half of the dummy clock is in the state of

high impedance, the controller can switch I/O for this

period. The corresponding data is shifted out on SI/SIO0 and

SO/SIO1 by the falling edge of SCK. The address is

automatically incremented to the next higher address after

each byte data (4 clock cycles) is shifted out. If the SCK

input is continued after the internal address arrives at the

highest address (1FFFFFh), the internal address returns to

the lowest address (000000h). By setting CS to high, the

device is deselected, and the read cycle is completed. While

the device is deselected, the output pin SO is in a

high−impedance state.

“Figure 14. Dual I/O Read (RDIO)” shows the timing

waveforms.

The sequence of RDIO operation:

CS goes to low → input RDIO command (BBh)

→ 3 Byte address (A23 − A0) input on SI/SIO0 and

SO/SIO1 by 12 clock cycle

→ 2 dummy clock (SI/SIO0 and SO/SIO1 are don’t care)

+ 2 dummy clock (must set SI/SIO0 and SO/SIO1 high

impedance)

→ the corresponding data out on SI/SIO0 and SO/SIO

CS

0

1

2

3

4

5

6

7

8

22 23 24

19

20 21

27 28

31

Mode3

Mode0

SCK

dummy

bit

8CLK

BBh

Byte 1 Byte2

Byte3

Add1: A22, A20−A2, A0

X

DATA0 DATA0 DATA0

SIO0

SIO1

MSB

4CLK

12CLK

2CLK

X

High Impedance

DATA1 DATA1 DATA1

Add2: A23, A21−A3, A1

MSB

DATA0: bit6, bit4, bit2, bit0

DATA1: dit7, bit5, bit3, bit1

• Address A23 to A21 are “Don’t care”.

Figure 14. Dual I/O Read (RDIO)

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LE25S161

Small Sector Erase (SSE)

CS goes to low → input SSE command (20h or D7h) →

3 Byte address (A23 − A0) input on SI

Small Sector Erase is an operation that sets the memory

cell data in any small sector to “1”. A small sector consists

of 4 kbytes.

“Figure 15. Small Sector Erase (SSE)” shows the timing

waveforms.

→ CS goes to high (be executed by the rising CS edge)

*A20 to A12 are valid address

After the correct input sequence the internal erase

operation is executed by the rising CS edge, and it is

completed automatically by the control exercised by the

internal timer (tSSE). The end of erase operation can also be

detected by status register (RDY).

“Figure 38. Small Sector Erase Flowcharts” shows the

flowcharts.

The sequence of SSE operation:

Self−timed Erase Cycle

t _SSE

CS

Mode3

0

1

2

3

4

5

6

7

8

15 16

23 24

31

SCK

SI

Mode0

8CLK

20h / D7h

Add

(A23−A16) (A15−A8)

(A7−A0)

MSB

High Impedance

SO

• Address A23 to A21, A11 to A0 are “Don’t care”.

Figure 15. Small Sector Erase (SSE)

Sector Erase (SE)

CS goes to low → input SE command (D8h) → 3 Byte

address (A23 − A0) input on SI

Sector Erase is an operation that sets the memory cell data

in any sector to “1”. A sector consists of 64 kbytes.

“Figure 16. Sector Erase (SE)” shows the timing

waveforms.

“Figure 39. Sector Erase Flowcharts” shows the

flowcharts.

→ CS goes to high (be executed by the rising CS edge)

*A20 to A16 are valid address

After the correct input sequence the internal erase

operation is executed by the rising CS edge, and it is

completed automatically by the control exercised by the

internal timer (tSE). The end of erase operation can also be

detected by status register (RDY).

The sequence of SE operation:

Self−timed Erase Cycle

t_SE

CS

Mode3

0

1

2

3

4

5

6

7

8

15 16

23 24

31

SCK

SI

Mode0

8CLK

D8h

Add

(A23−A16) (A15−A8)

(A7−A0)

MSB

High Impedance

SO

• Address A23 to A21, A15 to A0 are “Don’t care”.

Figure 16. Sector Erase (SE)

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LE25S161

Chip Erase (CHE)

Chip Erase is an operation that sets the memory cell data

in all sectors to “1”.

“Figure 17. Chip Erase (CHE)” shows the timing

waveforms.

“Figure40. Chip Erase Flowcharts” shows the flowcharts

CS goes to low → input CHE command (60h or C7h)

→ CS goes to high (be executed by the rising CS edge)

After the correct input sequence the internal erase

operation is executed by the rising CS edge, and it is

completed automatically by the control exercised by the

internal timer (tSE). The end of erase operation can also be

detected by status register (RDY).

The sequence of CHE operation:

Self−timed Erase Cycle

t_CHE

CS

Mode3

0

1

2

3

4

5

6

7

SCK

Mode0

8CLK

60h / C7h

SI

MSB

High Impedance

SO

Figure 17. Chip Erase (CHE)

Page Program

“Figure 41. Page Program Flowcharts” shows the

flowcharts.

Normal Page Program (PP)

The sequence of PP or PPL operation:

Low−Power Page Program (PPL)

CS goes to low → input PP command (02h) or PPL

command (0Ah)

There are two Page Program commands, Normal program

(PP: 02h ) and Low−Power program (PPL: 0Ah). These two

commands are completely functionally the same. By

selecting the Low−Power program (PPL), the operating

current is reduced, but the program cycle time is extended.

(Iccpp > Iccppl, tPPL > tPP)

Page Program is an operation that programs any number

of bytes from 1 to 256 bytes within the same sector page

(page addresses: A20 to A8). Before initiating Page

Program, the data on the page concerned must be erased

using Small Sector Erase, Sector Erase, or Chip Erase. Page

Program (PP, PPL) allows only previous erased data (FFh).

“Figure 18. Normal Page Program (PP)”. “Figure 19.

Low−power Page Program (PPL)” shows the timing

waveforms.

→ 3 Byte address (A23 − A0) input on SI

→ n−Byte data input on SI →→

→ CS goes to high (be executed by the rising CS edge)

The program data must be loaded in 1−byte increments. If

the data loaded has exceeded 256 bytes, the 256 bytes loaded

last are programmed. After the correct input sequence the

internal program operation is executed by the rising CS

edge, and it is completed automatically by the control

exercised by the internal timer (tPP or tPPL). The end of

program operation can also be detected by status register

(RDY).

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LE25S161

Self−timed Program Cycle

t_PP

CS

Mode3

Mode0

0

1

2

3

4

5

6

7

8

15 16

23 24

31 32

39 40

47

2079

SCK

Byte

256

8CLK

02h

Byte 1 Byte 2

PD PD

Add

SI

PD

(A23−A16) (A15−A8)

(A7−A0)

MSB

High Impedance

SO

• Address A23 to A21, A15 to A0 are “Don’t care”.

Figure 18. Normal Page Program (PP)

Self−timed Program Cycle

t_PPL

CS

Mode3

Mode0

0

1

2

3

4

5

6

7

8

15 16

23 24

31 32

39 40

47

2079

SCK

Byte

256

8CLK

0Ah

Byte 1 Byte 2

PD PD

Add

SI

PD

(A23−A16) (A15−A8)

(A7−A0)

MSB

High Impedance

SO

• Address A23 to A21, A15 to A0 are “Don’t care”.

Figure 19. Low−Power Page Program (PPL)

Write Suspend (WSUS)

checked by using status register RDY bit or SUS bit, but the

device will not accept another command until it is ready.

• The Write Suspend is valid Erase cycle (SSE, SE and

CHE) or Program cycle (PP, PPL).

• If the Erase (SSE, SE, CHE) or Program (PP, PPL) entry

during the suspension, the suspension will be canceled

automatically. And a new Erase (SSE, SE, CHE),

Program (PP, PPL) will be executed. In this case, it is

necessary to erase/program the suspended area again.

• During Write Suspend, Read (RDSR, RDLP, RDHS,

RDDO, RDIO) and Resume (RESM) can be accepted.

• If the Software Reset is executed during the suspension,

the suspension will be canceled automatically.

The Write Suspend (WSUS) allow the system to interrupt

Small Sector Erase (SSE), Sector Erase (SE), Chip Erase

(CHE) or Page Program (PP, PPL).

“Figure 20. Write Suspend (WSUS)” shows the timing

waveforms.

The sequence of WSUS operation:

CS goes to low → input WSUS command (B0h)

→ CS goes to high (be executed by the rising CS edge)

After the command has been input, the device becomes

consumption current equivalent to standby within 20 ms. The

recovery time (tRSUS) is needed before next command

from suspend. The internal operation status could be

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LE25S161

t_RSUS

CS

20 ms

Mode3

Mode0

0

1

2

3

4

5

6

7

3

4 5 6 7

0 1 2

SCK

8CLK

B0h

Next Command

(Read or Resume)

SI

MSB

High Impedance

MSB

SO

Operation Current

= Isb

Figure 20. Write Suspend (WSUS)

Resume (RESM)

The internal operation status could be checked by using

status register RDY bit or SUS bit.

This command (RESM) restarts erase cycle (SSE, SE,

CHE) or program cycle (PP, PPL) that was suspended.

“Figure 21. Resume (RESM)” shows the timing

waveforms.

This command will be ignored if the previous Write

Suspend operation was interrupted by unexpected power off

or re−erase/program (cancel of suspend) or Software Reset

(RST). To execute Write Suspend (WSUS) again after

Resume, it is necessary to wait for some time (tSUS).

The sequence of RESM operation:

CS goes to low → input RESM command (30h)

→ CS goes to high (be executed by the rising CS edge)

Self−timed Write Cycle

t / t / t

CHE SE SSE

/

t

/ t

PP PPL

CS

Mode3

0

1 2 3

4 5 6 7

SCK

Mode0

8CLK

30h

SI

MSB

High Impedance

SO

Figure 21. Resume (RESM)

Read ID

“Figure 22. Read JEDEC ID (RJID)” shows the timing

Read ID is an operation that reads the manufacturer code

(RJID) and device ID information (RID). These Read ID

commands are not accepted during writing. There are two

methods of reading the silicon ID, each of which is assigned

a device ID.

waveforms.

The sequence of RJID operation:

CS goes to low → input RJID command (9Fh)

→ Manufacture code (62h) out on SO → Memory type code

(16h) out on SO

Read JEDEC ID (RJID)

→ Memory capacity code out on SO (15h) → Reserve code

(00h) →→

→ completed by CS = high

This command (RJID) is compatible with the JEDEC

standard for SPI compatible serial memories.

“Table 12. JEDEC ID codes” lists the silicon ID codes.

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*The 4−byte code is output repeatedly as long as clock

inputs are present

Table 12. JEDEC ID CODES

Output Code

62h

*The data output starts from the falling edge of SCK (7th

clock)

Manufacturer code

By setting CS to high, the device is deselected, and Read

JEDEC ID cycle is completed. While the device is

deselected, the output pin SO is in a high−impedance state.

2 byte device ID

Memory type

Memory capacity code

Reserve code

16h

15h (16 MBit)

00h

CS

Mode3

0

1

2

3

4

5

6

7

8

15 16

23 24

31 32

39

SCK

SI

Mode0

8CLK

9Fh

High Impedance

SO

00h

MSB

62h

MSB

62h

MSB

16h

MSB

15h

MSB

Figure 22. Read JEDEC ID (RJID)

Read Device ID (RID)

This command (RID) is an operation that reads the Device

ID.

→ completed by CS = high

*The Device ID (88h) is output repeatedly as long as clock

inputs are present

*The data output starts from the falling edge of SCK (31th)

By setting CS to high, the device is deselected, and Read

ID cycle is completed. While the device is deselected, the

output pin SO is in a high−impedance state.

“Table 13. Device ID Code” lists the device ID codes.

“Figure 23. Read Device ID (RID)” shows the timing

waveforms.

The sequence of RID operation:

CS goes to low → input RID command (ABh) → 3 byte

Table 13. DEVICE ID CODE

Output Code

dummy cycle

→ Device ID (88h) out on SO →→

1 byte device ID

88h (LE25S161)

CS

Mode3

0

1

2

3

4

5

6

7

8

15 16

23 24

31 32

39

SCK

SI

Mode0

8CLK

ABh

X

High Impedance

SO

88h

MSB

88h

MSB

Figure 23. Read Device ID (RID)

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LE25S161

Deep Power−down (DP)

The standby current can be further reduced with this

command (DP).

“Figure 24. Deep Power−down (DP)” shows the timing

waveforms.

CS goes to low → input DP command (B9h)

→ CS goes to high (be executed by the rising CS edge)

The deep power−down command issued during an

internal write operation will be ignored.

The deep power−down state is exited using the deep

power−down exit (EDP). All other commands are ignored.

The sequence of DP operation:

Deep Power−down Standby

Standby current (Isb)

Current (Idsb)

CS

t_DP

Mode3

0

1 2 3

4 5 6 7

SCK

Mode0

8CLK

B9h

SI

MSB

High Impedance

SO

Figure 24. Deep Power−down (DP)

Exit Deep Power−down (EDP) / Read Device ID (RDDI)

The Exit Deep Power−down (EDP) / Read Device ID

(RID) command is a multi−purpose command. It can be used

to exit the device from the deep power−down state, or read

the device ID information.

“Figure 25. Exiting from Deep Power−down” shows the

timing waveforms.

The sequence of EDP operation:

CS goes to low → input EDP command (ABh)

→ CS goes to high (be executed by the rising CS edge)

Exit Deep Power−down (EDP)

The exit deep power−down command consists only of the

first byte cycle, and it is initiated by inputting (ABh).

Deep Power−down Standby

Standby current (Isb)

current (Idsb)

CS

t_RDP

Mode3

0

1 2 3

4 5 6 7

SCK

Mode0

8CLK

ABh

SI

MSB

High Impedance

SO

Figure 25. Exiting from Deep Power−down (EDP)

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LE25S161

Read Device ID (RDDI)

→ Device ID out on SO →→

Also the exit from deep power−down is completed by one

byte cycle or more of the Read Device ID (RID: ABh).

“Table 13. Device ID Code” lists the device ID codes.

“Figure 26. Read Device ID” shows the timing

waveforms.

→ completed by CS = high

*The Device ID is output repeatedly as long as clock inputs

are present

*The data output starts from the falling edge of SCK (31th

clock)

By setting CS to high, the device is deselected, and Read

ID cycle is completed. While the device is deselected, the

output pin SO is in a high−impedance state.

The sequence of EDP & RID operation:

CS goes to low → input RID command (ABh) → 3 byte

dummy cycle

Standby

Deep Power−down Standby current (Idsb)

current (Isb)

CS

t _RDP

Mode3

0

1

2

3

4

5

6

7

8

31 32

39

SCK

SI

Mode0

24 Dummy

Bits

8CL

ABh

X

High Impedance

SO

Dev ID

MSB

Figure 26. Read Device ID

Software Reset

When the Software Reset is executed, an internal write

(erase/program) operation is cancel, a suspended status is

reset, and all volatility status register bits (WEN/RDY/SUS)

are reset. After the internal reset time (tRST), the device will

become stand−by state. If the Software Reset is executed

during a write (erase/program) operation, any dates on the

write operation will be broken.

The Reset command must input just after input the Reset

Enable command. If another command input after the Reset

Enable command, the Reset−Enable state will be invalid.

The Software Reset reset the device to the state just after

power−on. This operation consists of two commands: the

Reset Enable (RSTEN) and the Reset command (RST).

“Figure 27. Software Reset” shows the timing waveforms.

The sequence of Software Reset operation:

CS goes to low → input RSTEN command (66h)

→ CS goes to high

→ CS goes to low → input RST command (99h)

→ CS goes to high (be executed by the rising CS edge)

Internal reset time

(tRST)

CS

Mode3

0

1

2

3

4

5

6

7

0 1 2 3

4

5 6 7

SCK

Mode0

8CLK

66h

8CLK

99h

SI

MSB

High Impedance

MSB

SO

Figure 27. Software Reset

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LE25S161

Read SFDP (RSFDP)

→ 1 byte dummy cycle the corresponding parameter out on

The Read SFDP (Serial Flash Discoverable Parameter) is

an operation that reads the parameter about device

configurations, available commands and other features. The

SFDP parameters are stored in internal parameter tables.

These parameter tables can be interrogated by host system

software to enable adjustments needed to accommodate

divergent features from multiple vendors. SFDP is a

standard of JEDEC. JESD216. Rev 1.0.

“Table 14. SFDP Header” shows SFDP Header.

“Table 15. SFDP Parameter Table” shows SFDP

Parameter Table.

“Figure 28. Read SFDP (RSFDP)” shows the timing

waveforms.

SO

→ continuous parameter out (n−byte) →→

→ completed by CS = high

*A10 to A0 are valid address

*The parameter output starts from the falling edge of SCK

(39th clock)

The Address is latched on rising edge of SCK. It is

necessary to add 1 dummy byte cycle after address is

latched, and the corresponding parameter is shifted out on

SO by the falling edge of SCK. The address is automatically

incremented to the next higher address after each byte

parameter is shifted out. By setting CS to high, the device is

deselected, and Read SFDP cycle is completed. While the

device is deselected, the output pin SO is in a

high−impedance state.

The sequence of RSFDP operation:

CS goes to low → input RSFDP command (5Ah) → 3 Byte

address (A23 − A0) input on SI

CS

Mode3

0

1

2

3

4

5

6

7

8

15 16

23 24

31 32

39 40

47 48

55

SCK

SI

Mode0

8CLK

5Ah

Add

X

(A23−A16) (A15−A8)

(A7−A0)

MSB

Byte 1

Byte 2 Byte 3

High Impedance

SO

Param1 Param2 Param3

MSB MSB MSB

Figure 28. Read SFDP (RSFDP)

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LE25S161

Table 14. SFDP HEADER

Byte Address

(Hex)

Description

SFDP HEADER 1st AND 2nd DWORD

SFDP Signature

Comment

Bits

Data (Hex)

50444653h (SFDP)

00h

01h

02h

03h

04h

05h

06h

07h

7:0

53h

46h

44h

50h

05h

01h

02h

FFh

15:8

23:16

31:24

7:0

SFDP Minor Revision Number

SFDP Major Revision Number

Number of Parameter Headers

Unused

Start from 00h

Start from 01h

15:8

02h indicates 3 parameters

23:16

31:24

1st PARAMETER HEADER (JDEC BASIC FLASH PARAMETERS)

ID Number (JEDEC ID)

00h (JEDEC specified header)

Start from 00h

08h

09h

0Ah

0Bh

7:0

00h

01h

10h

Parameter Table Minor Revision Number

Parameter Table Major Revision Number

15:8

Start from 01h

23:16

31:24

Parameter Table Length (in Double Word) How many DWORDs in the Parameter

table 10h indicates 16 DWORDs

Parameter Table Pointer (PTP)

Unused

First address of JEDEC Flash Parameter

table

0Ch

0Dh

0Eh

0Fh

7:0

40h

00h

FFh

15:8

23:16

31:24

2nd PARAMETER HEADER (VENDER PARAMETERS 1)

ID Number (onsemi

Manufacturer ID)

62h (ON Semiconductor manufacturer ID)

10h

7:0

62h

Parameter Table Minor Revision Number

Parameter Table Major Revision Number

Start from 00h

Start from 01h

11h

12h

13h

15:8

23:16

31:24

00h

01h

04h

Parameter Table Length (in Double Word) How many DWORDs in the Parameter

table 04h indicates 4 DWORDs

Parameter Table Pointer (PTP)

Unused

First address of On Semiconductor

Parameter table

14h

15h

16h

17h

7:0

C0h

00h

FFh

15:8

23:16

31:24

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LE25S161

Table 15. SFDP PARAMETER TABLE

Description

Byte

Address

(Hex)

Data

(Binary)

Data

(Hex)

Comment

Bits

JDEC Basic Flash Parameter Tables (from 1st DWORD TO 4th DWORD)

Block/Sector Erase Sizes

00b: Reserved

40h

1:0

01b

E5h

01b: support 4 kB Erase

10b: Reserved

11b: not support 4 kB Erase

Write Granularity

0: 1 Byte, 1:64 Byte or larger

2

3

1b

0b

Volatile Status Register Block Protect

Bits

0: Non−volatile

1: Volatile

Write Enable Instruction Select for Writ- 0: use 50h opcode, 1: use 06h opcode

4

0b

ing to Volatile Status Register

NOTE: If target flash status register is

nonvolatile, then bits 3 and 4 must be

set to 00b.

Unused

Contains 111b and can never be

changed

7:5

111b

4 kB Erase Instruction

(1−1−2) Fast Read

Address Bytes

20h

41h

42h

15:8

16

0010_0000b

20h

91h

0 = not support 1 = support

1b

00: 3 Byte only, 01: 3 or 4 Byte,

10: 4 Byte only, 11: Reserved

18:17

00b

Double Transfer Rate (DTR) Clocking

(1−2−2) Fast Read

(1−4−4) Fast Read

(1−1−4) Fast Read

Unused

0 = not support 1 = support

19

20

0b

1b

21

0b

22

0b

23

1b

1111_1111b

−

Unused

43h

31:24

31:0

FFh

Flash Memory Density

16 M bits

44h

45h

46h

47h

00FFFFFFh

(1−4−4) Fast Read Number of Wait

0 0000b: Wait states (dummy Clocks)

not support

48h

4:0

7:5

0_0000b

000b

00h

States (Dummy Clocks)

(1−4−4) Fast Read Number of Mode

Clocks

000b: Mode Bits not support

(1−4−4) Fast Read Instruction

49h

4Ah

15:8

1111_1111b

0_0000b

FFh

00h

(1−1−4) Fast Read Number of Wait

States (Dummy Clocks)

0 0000b: Wait states (dummy Clocks)

not support

20:16

(1−1−4) Fast Read Number of Mode

Clocks

000b: Mode Bits not support

23:21

000b

(1−1−4) Fast Read Instruction

4Bh

4Ch

31:24

4:0

1111_1111b

0_1000b

FFh

08h

(1−1−2) Fast Read Number of Wait

States (Dummy Clocks)

0 0000b: Wait states (dummy Clocks)

not support

(1−1−2) Fast Read Number of Mode

Clocks

000b: Mode Bits not support

7:5

000b

(1−1−2) Fast Read Instruction

4Dh

4Eh

15:8

0011_1011b

0_0100b

3Bh

04h

(1−2−2) Fast Read Number of Wait

States (Dummy Clocks)

0 0000b: Wait states (dummy Clocks)

not support

20:16

(1−2−2) Fast Read Number of Mode

000b: Mode Bits not support

23:21

31:24

000b

Clocks

(1−2−2) Fast Read Instruction

4Fh

1011_1011b

BBh

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24

LE25S161

Table 15. SFDP PARAMETER TABLE (continued)

Byte

Address

(Hex)

Data

(Binary)

Data

(Hex)

Description

Comment

Bits

JDEC BASIC FLASH PARAMETER TABLES (FROM 5th DWORD TO 8th DWORD)

(2−2−2) Fast Read

Reserved

0 = not support 1 = support

Default all 1’s

50h

0

3:1

4

0b

111b

0b

EEh

(4−4−4) Fast Read

Reserved

0 = not support 1 = support

Default all 1’s

7:5

31:8

111b

−

Reserved

Default all 1’s

51h

52h

53h

FFh

Reserved

Default all 1’s

54h

55h

15:0

−

FFh

(2−2−2) Fast Read Number of Wait

0 0000b: Wait states (dummy Clocks)

not support

56h

20:16

23:21

0_0000b

000b

00h

states (Dummy Clocks)

(2−2−2) Fast Read Number of Mode

Clocks

000b: Mode Bits not support

(2−2−2) Fast Read Instruction

57h

31:24

15:0

1111_1111b

FFh

Reserved

Default all 1’s

58h

59h

−

FFh

(4−4−4) Fast Read Number of Wait

0 0000b: Wait states (dummy Clocks)

not support

5Ah

20:16

23:21

0_0000b

000b

00h

States (Dummy Clocks)

(4−4−4) Fast Read Number of Mode

Clocks

000b: Mode Bits not support

(4−4−4) Fast Read Instruction

5Bh

5Ch

31:24

7:0

1111_1111b

0000_1100b

FFh

0Ch

Sector Type 1 Size

Sector/block size = 2^N bytes

0Ch indicates 4 kbytes

Sector Type 1 Erase Instruction

Sector Type 2 Size

5Dh

5Eh

15:8

0010_0000b

0001_0000b

20h

10h

Sector/block size = 2^N bytes

10h indicates 64 kbytes

23:16

Sector Type 2 Erase Instruction

5Fh

60h

31:24

7:0

1101_1000b

0000_0000b

D8h

00h

JDEC BASIC FLASH PARAMETER TABLES (FROM 9th DWORD TO 12th DWORD)

Sector Type 3 Size

Sector/block size = 2^N bytes

00h indicates not exist

Sector Type 3 Erase Instruction

Sector Type 4 Size

61h

62h

15:8

1111_1111b

0000_0000b

FFh

00h

Sector/block size = 2^N bytes

00h indicates not exist

23:16

Sector Type 4 Erase Instruction

63h

64h

31:24

3:0

1111_1111b

0100b

FFh

94h

Multiplier from Typical Erase Time to

Maximum Erase Time

SE (64 k−Byte erase):

150 ms = 2 x (n + 1) x 15 ms

n = 4

Sector Type 1 Erase, Typical Time

Sector Type 2 Erase, Typical Time

SSE (4 k−Byte erase)

10 ms: ((n + 1) x 1 ms = 10 ms)

n = 9

10:4

00_01001b

00_01110b

65h

70h

SE (64 k−Byte erase)

17:11

15 ms: ((n + 1) x 1 ms = 15 ms)

n = 14

66h

67h

00h

Sector Type 3 Erase, Typical Time

Sector Type 4 Erase, Typical Time

−

24:18

31:25

00_00000b

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25

LE25S161

Table 15. SFDP PARAMETER TABLE (continued)

Byte

Address

(Hex)

Data

(Binary)

Data

(Hex)

Description

Comment

Bits

JDEC BASIC FLASH PARAMETER TABLES (FROM 9th DWORD TO 12th DWORD)

Multiplier from Typical Time to Max

Time for Page or Byte Program

(n + 1) x 0.3 ms

= 0.9 ms: n = 2, 0.9 ms > 0.7 ms (spec)

68h

3:0

0010b

82h

Page Size

256 Bytes =2^8

7:4

1000b

Page Program Typical Time

(n + 1) x 64 ms

69h

6Ah

6Bh

13:8

1_00110b

E6h

07h

0Ch

= 448 ms: n = 6, 448 ms > 400 ms (spec)

Byte Program Typical Time, First Byte

(n + 1) x 8 ms

= 128 ms: n = 15

15:14

18:16

23:19

1_1111b

Byte Program Typical Time, Additional

Byte

(count + 1) x 1 ms/byte

= 1 ms/byte: Count = 0

0_0000b

Chip Erase, Typical Time

(n + 1) x 16 ms

= 208 ms: n = 12, 208 ms = 210 ms

(spec)

30:24

00_01100b

Reserved

−

31

0b

Prohibited Operations During Program

Suspend

xxx0b: May not initiate a new erase

anywhere

6Ch

3:0

1101b

FDh

xxx1b: May not initiate a new erase in

the program suspended page size

xx0xb: May not initiate a new page

program anywhere

xx1xb: May not initiate a new page

program in the program suspended

page size

x0xxb: Refer to vendor datasheet for

read restrictions

x1xxb: May not initiate a read in the

program suspended page size

0xxxb: Additional erase or program

restrictions apply

1xxxb: The erase and program

restrictions in bits 1:0 are sufficient

Prohibited Operations During Erase

Suspend

xxx0b: May not initiate a new erase

anywhere

xxx1b: May not initiate a new erase in

the erase suspended sector size

xx0xb: May not initiate a page program

anywhere

7:4

1111b

xx1xb: May not initiate a page program

in the erase suspended sector size

x0xxb: Refer to vendor datasheet for

read restrictions

x1xxb: May not initiate a read in the

erase suspended sector size

0xxxb: Additional erase or program

restrictions apply

1xxxb: The erase and program

restrictions in bits 5:4 are sufficient

Reserved

−

6Dh

8

0b

80h

Program Resume to Suspend Interval

<64 ms: (count + 1) x 64 ms, count = 0

40 ms: ((4 + 1) x 8 ms = 40 ms)

12:9

0000b

Suspend In−progress

Program Max Latency

15:13

19:16

23:20

30:24

10_00100b

6Eh

6Fh

08h

44h

Erase Resume to Suspend Interval

<64 ms: (count + 1) x 64 ms, count = 0

40 ms: ((4 + 1) x 8 ms = 40 ms)

0000b

Suspend In−progress

Erase Max Latency

10_00100b

Suspend/Resume Supported

0 = support 1 = not support

31

0b

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26

LE25S161

Table 15. SFDP PARAMETER TABLE (continued)

Byte

Address

(Hex)

Data

(Binary)

Data

(Hex)

Description

Comment

Bits

JDEC BASIC FLASH PARAMETER TABLES (FROM 13th DWORD TO 16th DWORD)

Program Resume Instruction

(Program Operation)

30h (as same as erase resume)

B0h (as same as erase suspend)

30h (as same as program resume)

B0h (as same as program suspend)

70h

71h

72h

73h

74h

7:0

0011_0000b

1011_0000b

0011_0000b

1011_0000b

30h

B0h

30h

B0h

04h

Program Suspend Instruction

(Program Operation)

15:8

Resume Instruction

(Write or Erase Type Operation)

23:16

31:24

Suspend Instruction

(Write or Erase Type Operation)

Reserved

1:0

7:2

00b

Status Register Polling

Device Busy

Use legacy polling by reading the

Status Register with 05h instruction

0000_01b

Exit Deep Power Down to Next

Operation Delay

40 ms: ((4+1) x 8 ms = 40 ms)

75h

14:8

10_00100b

1010_1011b

C4h

Exit Deep Power Down Instruction

ABh

15

22:16

23

76h

77h

78h

79h

D5h

5Ch

00h

Enter Deep Power Down Instruction

B9h

1011_1001b

30:24

31

Deep Power Down Supported

(4−4−4) Mode Disable Sequences

(4−4−4) Mode Enable Sequences

0 = support 1 = not support

0b

0000b

0b

−

3:0

7:4

8

(0−4−4) Mode Supported

(0−4−4) Mode Exit Method

(0−4−4) Mode Entry Method

Quad Enable Requirements (QER)

Hold and WP Disable

0 = not support 1 = support

9

0b

−

15:10

19:16

22:20

23

00_0000b

0000b

000b

−

7Ah

00h

00b: not have a QE bit

0: not supported

−

0b

Reserved

7Bh

7Ch

31:24

6:0

0000_0000b

001_1001b

00h

19h

Volatile or Non−Volatile Register and

xxx_xxx1b: Non−Volatile Status

Write Enable Instruction for Status Reg- Register 1, powers−up to last written

ister 1

value, use instruction 06h to enable

write

xx1_xxxxb: Status Register 1 contains

a mix of volatile and non−volatile bits.

The 06h instruction is used to enable

writing of the register.

Reserved

−

7

0b

Soft Reset and

Rescue Sequence Support

Issue reset enable instruction 66h, and

then issue reset instruction 99h.

7Dh

13:8

01_0000b

10h

Exit 4−Byte Addressing

Enter 4−Byte Addressing

15:14

23:16

31:24

00b

7Eh

7Fh

0000_0000b

00h

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27

LE25S161

Table 15. SFDP PARAMETER TABLE (continued)

Byte

Address

(Hex)

Data

(Binary)

Data

(Hex)

Description

Comment

Bits

VENDER (ON SEMICONDUCTOR) PARAMETER 1 TABLES (FROM 1th DWORD TO 4th DWORD)

Supply Maximum Voltage

1900h = 1.900 V

1950h = 1.950 V

2000h = 2.000 V

2200h = 2.200 V

2400h = 2.400 V

2700h = 2.700 V

3000h = 3.000 V

3600h = 3.600 V

C0h

C1h

15:0

−

50h

19h

Supply Minimum Voltage

1600h = 1.600 V

1650h = 1.650 V

1700h = 1.700 V

1800h = 1.800 V

20000h = 2.000 V

22000h = 2.200 V

23000h = 2.300 V

27000h = 2.700 V

C2h

C3h

31:16

50h

16h

RESET Pin

0 = not support

1 = support

C4h

0

1

2

3

4

5

0b

14h

RESET Active Logic Level

HOLD Pin

0 = active logic is 0

1 = active logic is 1

0 = not support

1 = support

1b

HOLD Active Logic Level

WP Pin

0 = active logic is 0

1 = active logic is 1

0b

0 = not support

1 = support

1b

WP Active Logic Level

0 = active logic is 0

1 = active logic is 1

0b

Reserved

00b

7:6

00b

All FFh

C5h

C6h

C7h

31:8

1111_1111b

FFh

JDEC ID Operation Code

9Fh

C8h

C9h

7:0

1001_1111b

0110_0010b

9Fh

62h

JDEC ID Read Data

(Manufacture Code)

62h (ON Semiconductor)

15:8

JDEC ID Read Data

(Memory Type)

16h

CAh

CBh

23:16

31:24

0001_0110b

0001_0101b

16h

15h

JDEC ID Read Data

(Memory Capacity Code)

15h (16 Mbits)

Device ID Operation Code

Device ID Read Data

Reserved

ABh

CCh

CDh

7:0

15:8

31:16

1010_1011b

1000_1000b

ABh

88h

88h (LE25S161)

All FFh

CEh

CFh

1111_1111b

FFh

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28

LE25S161

HOLD FUNCTION

Using the HOLD pin, the hold function suspends serial

high, HOLD must not rise or fall. The hold function takes

effect when the logic level of CS is low, the hold status is

exited and serial communication is reset at the rising CS

edge. In the hold status, the SO output is in the

high−impedance state, and SI and SCK are ”don’t care”.

communication (it places it in the hold status). “Figure 29.

HOLD Function” shows the timing waveforms. The device

is placed in the hold status at the falling HOLD edge while

the logic level of SCK is low, and it exits from the hold status

at the rising HOLD edge. When the logic level of SCK is

Active

CS

HOLD

Active

t_HS

SCK

t_HH

HOLD

t_HHZ

t_HLZ

High Impedance

SO

Figure 29. HOLD Function

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29

LE25S161

POWER−ON

In order to protect against unintentional writing, CS must

be within at V −0.3 to V +0.3 on power−on. After

The device is in the standby state after power is turned on.

DD

power−on, the supply voltage has stabilized at V (min) or

DD

higher, and waits for t

before CS is driven to “Low”.

VSL

V_DD

V_DD(Max)

Program, Erase and Write Commands are Ignored

Chip Select (CS = “L”) is Not Allowed

V_DD(Min)

t_VSL

Read Command is

allowed

Full Access Allowed

Reset

State

V_WI

t_PUW

0 V

time

Figure 30. Power−on Timing

Table 16. POWER−UP TIMING

Spec

Min

300

100

1.0

Max

−

Parameter

Symbol

Unit

ms

V

DD

(Min) to CS Low

t

VSL

Time to Write Operation

Operation Inhibit Voltage

t

500

1.5

ms

PUW

V

WI

V

www.onsemi.com

30

LE25S161

HARDWARE DATA PROTECTION

LE25S161 incorporates a power−on reset function. The

following conditions must be met in order to ensure that the

power reset circuit will operate stably.

No guarantees are given for data in the event of an

instantaneous power failure occurring during the writing

period.

V_DD

V_DD(Max)

V_DD(Min)

t_PD

0 V

vBOT

Figure 31. Power−down Timing

Table 17. POWER−DOWN TIMING

Spec

Min

10

−

Max

−

Parameter

Power−down Time

Power−down Voltage

Symbol

Unit

ms

V

t

PD

V

BOT

0.2

SOFTWARE DATA PROTECTION

DECOUPLING CAPACITOR

0.1 mF ceramic capacitor must be provided to each device

The LE25S161 eliminates the possibility of unintentional

operations by not recognizing commands under the

following conditions.

and connected between V and V in order to ensure that

DD

SS

the device will operate stably.

• When a write command is input and the rising CS edge

timing is not in a byte cycle (8 CLK units of SCK)

• When the Page Program data is not in 1−byte increments

• When the Write Status Register command is input for

2 bytes cycles or more

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31

LE25S161

SPECIFICATIONS

Absolute Maximum Ratings

Table 18. ABSOLUTE MAXIMUM RATINGS

Parameter

Maximum Supply Voltage

DC Voltage (All Pins)

Symbol

Conditions

Rating

Unit

V

With respect to V

−0.5 to +2.6

SS

−0.5 to V + 0.5

V

DD

Storage Temperature

Tstg

−55 to +150

°C

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

Operating Conditions

Table 19. OPERATING CONDITIONS

Parameter

Operating Supply Voltage

Operating Ambient Temperature

Symbol

Conditions

Rating

Unit

V

1.65 to 1.95

−40 to +90

°C

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

Data Retention, Rewriting Cycles

Table 20. DATA RETENTION, REWRITING CYCLES

Parameter

Symbol

Conditions

Status resister write

Program/Erase

Min

100,000

20

Max

−

Unit

Rewrite Cycles

Data Retention

cycRW

cycles/

Sector

−

tDRET

−

year

Pin Capacitance at Ta = 255C, f = 1 MHz

Table 21. PIN CAPACITANCE (Ta = 25°C, f = 1 MHz)

Rating

Max

12

6

Parameter

Output Pin Capacitance

Input Pin Capacitance

Symbol

Conditions

Unit

pF

C

V

= 0 V

SO

C

V = 0 V

IN

pF

IN

NOTE: These parameter values do not represent the results of measurements undertaken for all devices but rather values for some of the

sampled devices.

AC Test Conditions

Input pulse level

Input rising/falling time

Input timing level

Output timing level

Output load

0.2 V to 0.8 V

5 ns

NOTE: As the test conditions for “typ”, the

measurements are conducted using 1.8 V for

DD

0.3 V , 0.7 V

V

DD

at room temperature.

DD

1/2 x V

15 pF

DD

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32

LE25S161

Input level

Input / Output timing level

0.8 V

0.2 V

DD

0.7 V

DD

1/2 V

0.3 V

DD

Figure 32.

DC Characteristics

Table 22. DC CHARACTERISTICS

V

DD

= 1.65 to 1.95 V

Rating

Min

Typ

Max

4.5

Parameter

Symbol

Conditions

Unit

Read Mode Operating Current

I

SCK = 0.1 V

Low−Power

Read

(RDLP: 03h)

33.33 MHz

−

3.5

mA

CCR

DD

/ 0.9 V

,

DD

HOLD = WP =

0.9 V

,

DD

High−Speed

Read

(RDHS: 0Bh)

33.33 MHz

70 MHz

−

4.0

6.0

5.0

5.5

7.0

SO = open

Dual Output

Read

33.33 MHz

(RDDO: 3Bh)

or

Dual I/O Read

(RDIO: BBh)

50 MHz

−

6.0

7.0

Small Sector Erase Operating

Current

I

t

=max

−

3.5

4.0

6.5

5.0

9

4.5

5.0

7.5

6.5

50

mA

CCSSE

SSE

Average current

Sector Erase Operating

Current

I

t

SE

=max

CCSE

Average current

t =max

CHE

Chip Erase Operating Current

I

CCCHE

Average current

t =max

PP

Normal Program Mode

Operating Current

I

CCPP

Average current

t =max

PPL

Low−Power Program Mode

Operating Current

I

CCPPL

Average current

CMOS Standby Current

I

SB

CS = V , HOLD = WP = V

SI = VSS / V , SO = open

,

DD

Deep Power−down Standby

Current

I

CS = V , HOLD = WP = V

SI = VSS / V , SO = open

3.0

12

mA

DSB

DD

Input Leakage Current

Output Leakage Current

Input Low Voltage

I

−

2.0

mA

V

LI

I

LO

V

−0.3

0.3 V

DD

IL

Input High Voltage

V

0.7 V

V + 0.3

DD

V

IH

DD

Output Low Voltage

−

0.2

V

I

= 100 mA, V = V min

DD DD

OL

OH

= 1.6 mA, V = V min

0.4

DD

Output High Voltage

V

OH

= −100 mA, V = V min

V − 0.2

DD

−

V

DD

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

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33

LE25S161

AC Characteristics

Table 23. AC CHARACTERISTICS

Rating

Min

Typ

−

Max

33.33

50

Parameter

Symbol

Unit

Clock Frequency

f

MHz

Low−Power Read (RDLP: 03h)

−

CLK

Dual Output Read (RDDO: 3Bh)

Dual I/O Read (RDIO: BBh)

−

Other Instructions

−

0.1

11

8

−

70

−

Input Signal Rising/Falling Time

SCK Logic High Level Pulse Width

t

V/ns

ns

RF

t

33.33 MHz

50 MHz

−

CLHI

−

70 MHz

6

−

SCK Logic Low Level Pulse Width

t

ns

33.33 MHz

50 MHz

11

8

−

CLLO

−

70 MHz

6

−

CS Active Setup Time

CS Not Active Hold Time

Data Setup Time

t

6

−

ns

SLCH

6

−

CHSL

t

3

−

DS

Data Hold Time

t

3

−

DH

CS Wait Pulse Width

t

20

6

−

CPH

CS Active Hold Time

t

−

CHSH

SHCH

CS Not Active Setup Time

Output High Impedance Time from CS

Output Data Time from SCK

6

−

t

−

8

CHZ

t

V

33.33 MHz

50 MHz

−

10

8

−

70 MHz

−

8

Output Data Hold Time

t

1

−

ns

ms

HO

Output Low Impedance Time from SCK

HOLD Setup Time

t

0

−

CLZ

t

6

−

HS

HH

HOLD Hold Time

t

6

−

Output Low Impedance Time from HOLD

Output High Impedance Time from HOLD

WP Setup Time

t

−

8

HLZ

t

−

8

HHZ

t

20

−

WPS

WPH

WP Hold Time

t

−

Write Status Register Time

Normal Page Programming Cycle Time

t

5

8

WRSR

t

256 Byte

nByte

−

0.40

0.70

PP

−

0.14 + n x 0.26 / 256 0.35 + n x 0.35 / 256

0.60 1.20

0.14 + n x 0.46 / 256 0.50 + n x 0.70 / 256

Low−Power Page Programming

Cycle Time

t

ms

256 Byte

nByte

−

PPL

−

Small Sector Erase Cycle Time

Sector Erase Cycle Time

Chip Erase Cycle Time

t

−

10

15

210

−

120

150

2400

40

ms

SSE

t

−

SE

t

−

CHE

Recovery Time from Suspend

Deep Power−down Time

Deep Power−down Recovery Time

Internal Reset Time

t

−

RSUS

t

−

5

ms

DP

t

−

40

ms

RDP

tRST

−

40

ms

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

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34

LE25S161

TIMING WAVEFORMS

t_CPH

CS

t_SHCH

t_CHSL

t_SLCH

t_CLHI

t_CLLO

t_CHSH

SCK

t_DS

t_DH

SI

DATA VALID

High Impedance

SO

Figure 33. Serial Input Timing

CS

SCK

t_CLZ

t_HO

t_CHZ

SO

SI

DATA VALID

t_V

Figure 34. Serial Output Timing

CS

t_HH

t_HS

t_HH

t_HS

SCK

HOLD

SI

t_HLZ

High Impedance

t_HHZ

Figure 35. Hold Timing

CS

t_WPS

t_WPH

WP

Figure 36. Status Resister Write Timing

www.onsemi.com

35

LE25S161

Small Sector Erase

Start

Write Status Register

Start

Write enable

(WREN)

06h

Set Small Sector

Erase command

(SSE)

20h / D7h

Address 1

Address 2

Address 3

06h

Write enable

(WREN)

01h

Set Write Status

Register command

(WRSR)

Data

Program start on rising

edge of CS

Start erase on rising

edge of CS

Set

05h

Read Status Register

command

(RDSR)

Read Status Register

command

(RDSR)

NO

Bit 0 = “0” ?

YES

Bit 0 = “0” ?

YES

End of Write Status

Register

End of erase

* Automatically placed in write disabled state

at the end of the Write Status Register

* Automatically placed in write disabled

state at the end of the erase

Figure 37. Write Status Register Flowcharts

Figure 38. Small Sector Erase Flowcharts

www.onsemi.com

36

LE25S161

Sector Erase

Start

Write enable

(WREN)

06h

Chip Erase

Start

Set Sector Erase

command

(SE)

D8h

Write enable

(WREN)

Address 1

Address 2

Address 3

06h

Set Chip Erase

command

(CHE)

60h / C7h

Start erase on rising

edge of CS

Start erase on rising

edge of CS

Set

05h

Read Status Register

command

(RDSR)

Set

05h

Read Status Register

command

(RDSR)

Bit 0 = “0” ?

YES

NO

Bit 0 = “0” ?

YES

NO

End of erase

* Automatically placed in write disabled

state at the end of the erase

* Automatically placed in write disabled state at

the end of the erase

Figure 39. Sector Erase Flowcharts

Figure 40. Chip Erase Flowcharts

www.onsemi.com

37

LE25S161

Page Program

Start

06h

Write enable

(WREN)

02h or 0Ah

Address 1

Address 2

Address 3

Data 0

Set Page Program

command

(PP/PPL)

*02h: Normal Program Mode (PP)

*0Ah: Low−Power Program Mode (PPL)

Data n

Start program on rising

edge of CS

Set

05h

Read Status Register

command

(RDSR)

NO

Bit 0 = “0” ?

YES

End of

programming

* Automatically placed in write disabled state at

the end of the programming operation.

Figure 41. Page Program Flowcharts

www.onsemi.com

38

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

WLCSP8 2.92x1.53x0.525

CASE 567YR

ISSUE O

DATE 21 NOV 2019

GENERIC

MARKING DIAGRAM*

XXXX = Specific Device Code

*This information is generic. Please refer to

A

L

= Assembly Location

= Wafer Lot

device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “G”, may

or may not be present. Some products may

not follow the Generic Marking.

XXXXX

ALYW

Y

W

= Year

= Work Week

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98AON14166H

WLCSP8 2.92x1.53x0.525

PAGE 1 OF 1

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the

rights of others.

www.onsemi.com

onsemi,

, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates

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A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any

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


型号：	LE25S161XBTAG
厂家：	ONSEMI
描述：	串行闪存，16 Mb (2048K x 8) 闪存
文件：	总40页 (文件大小：355K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LE25S161XBTAG [ONSEMI]

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