LV8968BBUWR2G [ONSEMI]
Multipurpose Three-Phase Brushless DC Predriver, Developed in Compliance with ISO 26262;
| 型号： | LV8968BBUWR2G |
| 厂家： | 
ONSEMI |
| 描述： | Multipurpose Three-Phase Brushless DC Predriver, Developed in Compliance with ISO 26262 |
| 文件： | 总35页 (文件大小：379K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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Multi-purpose Three-Phase
BLDC Predriver
LV8968BBUW
SPQFP48
CASE 131AN
Overview
The LV8968BB is a multi−purpose three−phase BLDC predriver for
automotive applications and developed in compliance with ISO
26262. This 3−phase peripheral predriver offers a BEMF (Back
ElectroMotive Force) output and the wide operating voltage range and
AEC−Q100 qualification make this device ideal for automotive
applications. Six gate drivers provide 400 mA (typ) gate current to
external power bridges allowing use of low resistance power FETs as
well as logic level FETs. All FETs are protected against overcurrent,
short−circuit, overtemperature and gate undervoltage. A multitude of
protection and monitoring features make this device suitable for
applications with functional safety (FuSa) requirements. Three
independent low−side source pins allow multiple shunt measurement.
The device also includes a programmable linear regulator, a fast
current sense amplifier and a window watchdog for microcontroller
support. The SPI interface allows for real time parameter setup and
diagnostics. Critical system parameters can be programmed into
nonvolatile OTP memory.
MARKING DIAGRAM
MP = Assembly Location
WL = Wafer Lot
= Year
WW = Work Week
Y
ORDERING INFORMATION
Device
LV8968BBUWR2G
Package
Shipping†
SPQFP48K
(Pb−Free /
2500 /
Tape & Reel
Junction temperature tolerance up to 175°C and control via wide
level WAKE and PWM signals make the LV8968BB an ideal motor
predriver for a wide range of ISO 26262 related actuators, fans and
pumps.
Halogen Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Features
• Full Drive Power from 8 V to 28 V Supply Voltage with Transient
Tolerance from 4.5 V to 40 V
SAFETY DESIGN ASIL B
• Extended Voltage Range from 6 V to 33 V Using Logic Level Mode
ASIL B Product developed in compliance with
ISO 26262 for which a complete safety package is
available.
• Up to 30 kHz Motor PWM with Individual Six Gate Control or
Drive−3 Mode with Integrated Programmable Dead Time
• 5 V / 3.3 V Linear Regulator for External Loads up to 50 mA
• Extensive System Protection Features Including:
♦ Drain−Source Short Detection for External FET
♦ Overcurrent Shutoff
Typical Applications
• Suspension, Park Brake, Transmission,
Steering Pump, Vacuum Pump, Battery
Pack Cooling, Sliding Door, Lift Gate etc.
• Robotics
• Light E−mobility and Motive Power
• Industrial Equipment
• White Goods
♦ Low Gate Voltage Warning
♦ Overtemperature Warning and Shutoff
♦ Over / Undervoltage Protection
• SPI Interface for Parameter Setup and Diagnostic Access, Dynamic
Access to Dead Time, Amplifier Gain, and Short−Circuit Levels
• Nonvolatile (OTP) Memory for Storing Critical System Parameters
• Wide Voltage Enable Line and PWM Interface
• Integrated Window Watchdog Timer Function
• AEC−Q100 Qualified and PPAP Capable
• Thermally Efficient Exposed Die 48 Pin SQFP Package for Transient
Operation Up to 175°C
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
© Semiconductor Components Industries, LLC, 2018
1
Publication Order Number:
September, 2022 − Rev. 5
LV8968BBUW/D
LV8968BBUW
INTERNAL EQUIVALENT BLOCK DIAGRAM AND APPLICATION CIRCUIT
Opt.
Reverse Polarity
Protection
BAT
Opt. Charge
Pump
KEY
PWM
V3RO V3RI
WAKE VS
VGIN VG
PWMIN
RX D
BS 1
BS 2
BS 3
VCC
VDH
GH1
GH2
GH3
EN
VMCRES
DIAG
CSB
SCLK
SI
LV8968BB
SH 1
SH 2
SH 3
GL1
SO
AOUT
IH1
IL1
IH2
IL2
GL2
GL3
IH3
IL3
3
SL [1:3]
ISP
ISN
AGND
ISO
GND
Figure 1. Typical Application Diagram
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2
LV8968BBUW
PIN ASSIGNMENT
36
25
24
GH1
BS1
VDH
VG
SL 3
NC
ISP
ISN
NC
VGIN
VS
ISO
AOUT
AGND
NC
LV8968BB
SQFP48K (7 × 7)
7 mm × 7 mm
WAKE
NC
EN
SO
SI
V3RO
V3RI
SCLK
CSB
48
13
1
12
Figure 2. LV8968BB Pinout
Table 1. PIN ASSIGNMENTS & DESCRIPTION
Name
VCC
IH1
No.
1
Description
5 V or 3.3 V linear regulator output. (Selected by SPI register setting)
Active high, digital control input to activate GH1.
Active low, digital control input to activate GL1.
Active high, digital control input to activate GH2.
Active low, digital control input to activate GL2.
Active high, digital control input to activate GH3.
Active low, digital control input to activate GL3.
2
IL1
3
IH2
4
IL2
5
IH3
6
IL3
7
VMCRES
8
Open drain reset output for the microcontroller. Goes low for VCC undervoltage fault, optionally for
watchdog reset and thermal shutdown.
DIAG
9
Open drain error or diagnostic output to be connected to microcontroller interrupt line. DIAG
functionality is defined by internal register settings.
RXD
NC
10
11
12
13
14
Open drain PWM data output to microcontroller.
No connection.
PWMIN
CSB
Input for battery level control signal. The digital level of PWMIN appears on RXD.
High voltage level translator. Digital level is active low, digital SPI interface chip selection pin.
SPI interface clock input pin. SI data is latched during the rising edge.
SCLK
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LV8968BBUW
Table 1. PIN ASSIGNMENTS & DESCRIPTION (continued)
Name
SI
No.
15
16
17
18
19
20
Description
SPI interface serial data input pin.
SO
SPI interface serial data output pin. High level is pulled to VCC.
NC
No connection.
AGND
AOUT
ISO
Ground pin.
Output for various internal analog signals. Actual signal is selected via SPI register.
Output pin for current sense amplifier. Connect to AD converter input of the microcontroller for
current sensing. Gain, reference, and overcurrent threshold is programmable via SPI register.
ISN
ISP
21
22
Current sense amp minus input pin. Connect this pin to the GND side of the shunt resistor with
Kelvin leads.
Current sense amp plus input pin. Connect this through to top side of shunt resistor with Kelvin
leads.
NC
23
24
No connection.
SL3
Low−side source connection of the power stage. Return path for gate current of GL3.
Connect to source of FET controlled by IL3 or to common source of the power stage.
GL3
SH3
GH3
BS3
SL2
GL2
SH2
GH2
BS2
SL1
GL1
SH1
GH1
BS1
VDH
VG
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Gate driver output for low−side FETs. Switches voltage level between VG and SL3.
Use at least 10 W gate resistors to protect against current spikes.
Connection for the motor phase terminal controlled by GH3 and GL3. Return path for high−side
drivers and input for BEMF sensing.
Gate driver output for high−side FETs. Switches voltage level between BS3 and SH3.
Use at least 10 W gate resistors to protect against current spikes.
Supply pin for high−side driver GH3. Needs a bootstrap capacitor to SH3 and a diode in reverse
connection to VG.
Low−side source connection of the power stage. Return path for gate current of GL2.
Connect to source of FET controlled by IL2 or to common source of the power stage.
Gate driver output for low−side FETs. Switches voltage level between VG and SL2.
Use at least 10 W gate resistors to protect against current spikes.
Connection for the motor phase terminal controlled by GH2 and GL2.
Return path for high−side drivers and input for BEMF sensing.
Gate driver output for high−side FETs. Switches voltage level between BS2 and SH2.
Use at least 10 W gate resistors to protect against current spikes.
Supply pin for high−side driver GH2. Needs a bootstrap capacitor to SH2 and a diode in reverse
connection to VG.
Low−side source connection of the power stage. Return path for gate current of GL1.
Connect to source of FET controlled by IL1 or to common source of the power stage.
Gate driver output for low−side FETs. Switches voltage level between VG and SL1.
Use at least 10 W gate resistors to protect against current spikes.
Connection for the motor phase terminal controlled by GH1 and GL1.
Return path for high−side drivers and input for BEMF sensing.
Gate driver output for high−side FETs. Switches voltage level between BS1 and SH1.
Use at least 10 W gate resistors to protect against current spikes.
Supply pin for high−side driver GH1. Needs a bootstrap capacitor to SH1 and a diode in reverse
connection to VG.
Sense input for supply voltage and short−circuit detection of high−side power FETs.
Connect through 100 W resistor to common drain of the power bridge.
Power supply pin for low−side gate drive GL[1−3] directly and GH[1−3] through bootstrap circuit.
Connect decoupling capacitor between VG and GND.
NC
41
42
No Connection.
VGIN
Gate supply input. Normally shorted to VS. Insert a charge pump circuit between VS and VGIN if
low voltage operation is required.
VS
43
Power supply pin.
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LV8968BBUW
Table 1. PIN ASSIGNMENTS & DESCRIPTION (continued)
Name
WAKE
NC
No.
44
Description
WAKE up pin for internal power supply. “H” => Operating mode, “L” or “Open” => Sleep mode.
No connection.
45
EN
46
Active high digital input. A high on EN will activate the outputs. EN can be used as a hold input to
allow an external microcontroller to keep the IC operating even if WAKE is low.
A falling edge on EN clears the error flags.
V3RO
V3RI
47
48
Internal regulator output pin. Connect capacitor between this pin and GND.
Internal regulator feedback pin (Control circuit and Logic power supply).
Connect to V3RO pin.
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LV8968BBUW
PIN FUNCTIONALITY
VS
VS
VS
IH1
IH2
IH3
SCLK
SI
V3RO
VCC
V3RI
100 kW
TYPE1: V3RI
VS
TYPE2: V3RO, VCC
TYPE3: IH1, IH2, IH3, SCLK, SI, EN
BS
VS
VCC
GH[1−3]
VMCRES
DIAG
RXD
30 kW
IL1
IL2
IL3
SH[1−3]
240 kW
TYPE4: VMCRES, DIAG, RXD
VG
TYPE5: IL1, IL2, IL3, CSB
TYPE6: BS[1−3], GH[1−3], SH[1−3]
V3RI
V3RI
AOUT
ISO
GL[1−3]
ISP
ISN
SL[1−3]
TYPE7: GL[1−3], SL[1−3]
TYPE8: AOUT, ISO
TYPE9: ISP, ISN
VS
VS
VS
SO
PWMIN
WAKE
TYPE10: SO
TYPE11: WAKE
TYPE12: PWMIN
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LV8968BBUW
PIN FUNCTIONALITY (continued)
VGIN
VG
VDH
TYPE13: VDH
TYPE14: VGIN, VG
Figure 3. Pin Functionality
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameter
Pins
Ratings
−0.3 to 40
−0.3 to 40
−0.3 to 40
−0.3 to 40
−0.3 to 3.6
−0.3 to 5.5
−0.3 to 40
−0.3 to 40
−0.3 to 40
Unit
V
Supply Voltage
VS, VDH, VGIN
Gate Voltage to GND
Bootstrap to GND
VG
V
BS[1−3]
V
Bootstrap to SH[1−3]
Logic Power Supply
BS[1−3]
V
V3RI, V3RO
V
3.3 V / 5 V Regulator Voltage
VS Level Signal Voltage
Digital Inputs
VCC
V
WAKE, PWMIN
V
CSB, EN, SCLK, SI, IH[1−3], IL[1−3]
V
Open Drain Voltage
VMCRES, RXD, DIAG
SO
V
Digital Output Voltage
Current Sense Input
Analog Output
−0.3 to V
+0.3
V
VCC
ISP, ISN
−3 to V
+0.3
V
V3RI
ISO, AOUT
GH[1−3]
−0.3 to V +0.3
V3RO
V
High−side Output to GND
Motor Phase
−3 to 40
−3 to 40
−3 to 40
−3 to 40
−0.3 to 20
2430
V
SH[1−3]
V
Low−side Output to GND
Low−side Source Pin to GND
Voltage between HS Gate and Phase
Allowable Power SQFP48K
GL[1−3]
V
SL[1−3]]
V
GH[n] to SH[n] for n = {1,2,3}
at 70°C
V
mW
°C/W
°C/W
°C
°C
°C
kV
V
Thermal Resistance
(JESD51−7)
J
J
= Junction Ambient
= Junction Case
33
A
C
2
Storage Temperature
Junction Temperature
−55 to 150
−40 to 150
150 to 175
2
(Note 1)
ESD Human Body Model
ESD Charge Device Model
AEC Q100_002
AEC Q100_011
750
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Operation outside the Operating Junction temperature is not guaranteed. Operation above 150°C should not be considered without a written
agreement from ON Semiconductor Engineering staff.
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LV8968BBUW
Table 3. ELECTRICAL CHARACTERISTICS
(Valid at a junction temperature range from −40°C to 150°C, for supply Voltage 8.0 V ≤ VS ≤ 25 V unless otherwise specified.
Typical values at 25°C and VS = 12 V unless specified otherwise)
Parameter
Symbol
Condition
Min
Typ
Max
Unit
SUPPLY VS RELATED INPUTS
VS supply voltage range
VSLOF
VSNO
Full logic functionality
4.5
8
40 (Note 3)
V
V
Standard FET operation mode
(VGVSEL = 0)
28
(Note 2)
VSLO
ISTBY
Logic level FET operation mode
(VGVSEL = 1)
6
7
33
V
(Note 2)
Standby mode, VS & VGIN shorted
VS = 6 V ~ 25 V
11
25
16
mA
VS supply current
ISLEEP
Sleep mode at 25°C, VS & VGIN shorted
50
1.3
VS
200
1
mA
V
VTHWKL
VTHWKH
RPDWK
TWTPOR
TVCSU
Low level
High level
0
WAKE input voltage
2.7
50
V
WAKE pulldown resistor
WAKE up time for POR
100
kW
ms
ms
WAKE pin high
VCC start−up time to active
state
1.05
VG start−up time to active
state
TVGSU
1.05
ms
OTP download time
TDNLD
VTHPIL
VTHPIH
RPDPI
After POR
Low level
High level
125
0.4×VS
VS
ms
V
0
0.6×VS
50
PWMIN switching levels
V
PWMIN pulldown resistor
PWMIN frequency range
INTERNAL REGULATOR
V3RO output voltage
100
3.3
200
kW
kHz
FPWMIN
0
30
V3RO
V3RO only connect to V3RI
Source, V3RO = V3RI
3.135
3.465
1
V
Max pull-up current Isource
IV3RO
mA
VCC CONSTANT VOLTAGE OUTPUT
Output voltage 5 V
VC5RO
VCVSEL = 1, No load
VCVSEL = 0, No load
4.9
3.23
3.0
5.0
3.3
5.1
V
V
VC3RO
VC3RL
VCCVR
VCCLR
VCCILIM
3.37
Output voltage 3.3 V
VS = 4.5 V, I
=-50 mA
V
VCC
Voltage regulation
50
80
mV
mV
mA
Load regulation
Io = −5 mA to −50 mA
Output current limit
50
180
GATE DRIVERS
Low−side Rdson to SL[1−3]
Low−side Rdson to SH[1−3]
High−side Rdson to SH[1−3]
High−side Rdson to BS[1−3]
Propagation delay ON
Propagation delay OFF
RONLSSK “L” level Io = 10 mA
RONLSSC “H” level Io = −10 mA
RONHSSK “L” level Io = 10 mA
RONHSSC “H” level Io = −10 mA
6
12
6
15
22
W
W
15
W
12
22
W
PDON
50% IHx to 20% GHx. Cload = 0 nF
120
120
20
ns
ns
ns
PDOFF
DPDON
50% IHx to 80% GHx. Cload = 0 nF
Propagation delay ON
Difference GH[1−3], GL[1−3]
a.3 Phase difference of GH1,Gh2 and GH3.
b.3 Phase difference of GL1,GL2 and GL3.
−20
−20
Propagation delay OFF
Difference GH[1−3], GL[1−3]
DPDOFF
a.3 Phase difference of GH1,Gh2 and GH3.
b.3 Phase difference of GL1,GL2 and GL3.
20
ns
Output current limit
IGOLIM
400
mA
FDTI programmable dead time TFDTI
0.2 ms step by FDTI register 4 bits (Note 4)
0.2
3.2
ms
BS PINS
BS internal current
IBSC
800
mA
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LV8968BBUW
Table 3. ELECTRICAL CHARACTERISTICS (continued)
(Valid at a junction temperature range from −40°C to 150°C, for supply Voltage 8.0 V ≤ VS ≤ 25 V unless otherwise specified.
Typical values at 25°C and VS = 12 V unless specified otherwise)
Parameter
Symbol
Condition
Min
Typ
Max
Unit
VG PIN
VGNO
Normal mode, VGVSEL = 0, IVG < 40 mA
Logic level mode, VGVSEL = 1
VS = 6 V, IVG < 30 mA
7.0
5
11.0
6
12.0
7
VG output voltage
V
VGLO
VGOL
VGILIM
5
VG current limit
40
180
mA
ANALOG OUTPUT (AOUT)
BEMF divider ratio
BEMFDR
BEMFDM
BEMFST
VDHDR
VDHST
1/16
BEMF divider mismatch
BEMF divider settling time
VDH divider ratio
−2
2
2
%
for 20% to 80% step
0.5
1/32
0.5
ms
VDH divider settling time
Thermal voltage
for 20% to 80% step
2
ms
mV
mV/°C
V
VTMPH
Tj = 155°C (Note 4)
705
+1.9
Thermal slope
VTEMPSL (Note 4)
AOFLSCR
AOUT full scale range
AOUT output resistance
AOUT output current
2.1
200
100
RONAO
IAO
IAOUT = 100 mA
W
−100
mA
CURRENT SENSING (ISP, ISN, ISO)
ISP, ISN input current
Reference voltage ISO
IISP/N
−0.2V ≤ VISP, VISN ≤ 2 V
CSOFEN = 0, GAIN = 30, ISP = ISN = 0.2 V
CSOFEN = 1, GAIN = 30, ISP = ISN = 0.2 V
CSGAIN = 00
−50
1.425
0.125
6.53
50
mA
V
VRCSA0
VRCSA1
CSAG00
CSAG01
CSAG10
CSAG11
CSACMR
DVCSAIN
CSAFLSCR
CSAOST
1.5
0.2
7.5
15
1.575
0.275
8.63
V
Gain
CSGAIN = 01 (Note 4)
CSGAIN = 10 (Note 4)
22.5
30
CSGAIN = 11
26
−0.2
−200
0.1
34.3
2
Common mode range
ISN, ISP differential voltage
ISO full scale range
1
V
mV
V
200
2.9
Amplifier settling time
overcurrent
Gain = 15, VISN = 0 V, VISP = step
(−200 mV to +200 mV),
VISO transient from 20% to 80% full scale
5400
ns
Amplifier settling time (normal
operation) (Note 5)
CSAOSST VISO = 1 Vpp, settling to 90% (rising edge)
or 10% (falling edge) ISO load = 10 pF
540
ns
ISO output resistance
ISO output current
RCSAO
ICSAO
I
=
100 mA
200
100
220
170
120
3.2
W
ISO
−100
180
130
80
mA
mV
mV
mV
ms
VTHCSA00 OCDL = 00
VTHCSA01 OCDL = 01
VTHCSA1X OCDL = 10,11
200
150
100
Overcurrent voltage level V
−
ISP
V
ISN
OCMASK programmable
Overcurrent Mask time
TOCMASK 0.2 ms step by OCMASK register 4 bits
0.2
(Note 4)
ACTIVE HIGH DIGITAL INPUTS (EN, SCLK, SI, IH[1−3])
High−level input voltage
Low−level input voltage
Pull−down resistance
VTAHH
VTAHL
RPDAH
0.8×V3RO
V
V
0.2×V3RO
50
100
30
200
kW
ACTIVE LOW DIGITAL INPUTS (CSB, IL[1−3])
High−level input voltage
Low−level input voltage
Pull−up resistance to VCC
VTALH
VTALL
RPDAL
V
V
0.8×V3RO
0.2×V3RO
15
60
kW
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LV8968BBUW
Table 3. ELECTRICAL CHARACTERISTICS (continued)
(Valid at a junction temperature range from −40°C to 150°C, for supply Voltage 8.0 V ≤ VS ≤ 25 V unless otherwise specified.
Typical values at 25°C and VS = 12 V unless specified otherwise)
Parameter
DIGITAL OUTPUTS (SO)
Output voltage
Symbol
Condition
Min
Typ
Max
Unit
VSOH
VSOL
Io = −1 mA
V
−0.2
V
V
VCC
Io = 1 mA
0.2
OPEN DRAIN OUTPUTS (VMCRES, DIAG, RXD)
Output voltage
VODL
Io = 1 mA
Vo = 5.5 V
0.2
10
V
Pin leakage current
ILKOD
mA
WARNING AND PROTECTION
TWT0
THTSEL = 0
THTSEL = 1
Hysteresis
125
150
°C
°C
°C
°C
°C
°C
V
Thermal warning
(Junction temperature)
TWT1
HYSTW
TSDT0
TSDT1
HYSTSD
VSOVTH
25
THTSEL = 0
THTSEL = 1
Hysteresis
150
175
Thermal shutdown
(Junction temperature)
25
17
VS high voltage detection, warning/protec-
tion response set by VSOVPS
16
7
18
8
VS voltage warning/protection
VSUVTH
VS low voltage detection, warning/protec-
tion response set by VSUVPS
7.5
V
V
VDH voltage warning/protection VDHOVTH VDH high voltage detection, warning/protec-
tion response set by VDOVPS
25
26.5
28
VGNUVTH Normal mode, VGVSEL = 0
VGLUVTH
5
6
4
7
V
V
VG undervoltage
3.5
4.5
Logic level mode, VGVSEL = 1
VC3UVTH VCVSEL = 0
VC5UVTH VCVSEL = 1
VPOR
2.3
3.8
2.7
4.2
V
V
VCC undervoltage
V3R Power on Reset
2.7
V
FET short detection Level
VFSDL
100 mV step by FSDL register 4 bits
(Note 4)
100
1600
mV
FSDL0000 FSDL = 0000
FSDL0010 FSDL = 0010
FSDL0100 FSDL = 0100
FSDL1000 FSDL = 1000
75
240
400
720
1280
3.2
100
300
500
900
1600
125
360
mV
mV
mV
mV
mV
ms
FET short Detection level
600
1080
1920
12.8
FSDL1111
TFSDT
FSDL = 1111
FET short detection masking
time
3.2 ms step by FSDT register 2 bits (Note 4)
FET short detection debounce TFSFT
filter time,
0.8 ms step by FSFT register 2 bits (Note 4)
0.8
3.2
ms
WATCHDOG
WD first open window
WD closed window time
WD open window time
WD reset duration
WDFOW
WDCW
WDOW
WDRD
WDTWT[2:0] typical values
WDTWT[2:0] typical values
WDTWT[2:0] typical values
3.2
0.8
1.6
409.6
102.4
204.8
ms
ms
ms
ms
400
SPI INTERFACE
SPI clock frequency
BS internal current
FSPI
IBSC
4.5
MHz
800
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. VDH overvoltage warning will be issued for elevated VS supply voltage levels. See the specification of the VDH overvoltage warning
threshold voltage VDHOVTH.
3. Valid for limited time duration of 400 ms (Load dump)
4. Not tested in production. Guaranteed by design and verified during qualification.
5. Not tested in production, verified on bench.
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LV8968BBUW
DETAILED FUNCTIONAL DESCRIPTION
VG
WAKE
VS
V3RI
VGIN
V3RO
VGIN
VDH
PWMIN
RXD
Gate Voltage
Regulator
PWM
Interface
Internal
Regulator
BS1
LDO 3.3 V / 5 V
LVSD
POR
GH1
VCC
SH1
GL1
System State
Machine
EN
OTP
SL1
BS2
Window−Watchdog
VMCRES
Diag Control
SPI Interface
GH2
SH2
GL2
DIAG
CSB
SCLK
SI
Registers
Gate Drive
SL2
BS3
SO
AOUT
IH1
Thermal Monitor
GH3
SH3
IL1
Motor Control
Logic
Short−Circuit
Monitor
IH2
IL2
Drive 3
Drive 6
GL3
SL3
IH3
IL3
Overcurrent
Monitor
Digital Circuit
ISP
ISN
ISO
Current Sense
Amplifier
LV8968BB
AGND
Figure 4. Block Diagram
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11
LV8968BBUW
Chip Activation, System States and Shutdown (EN, WAKE)
Once the supply voltage VS rises above VSLOF(Min.),
the LV8968BB enters Sleep mode. In Sleep mode system
states are controlled with pin WAKE.
Table 4. OPERATION MODES
Mode
Sleep
WAKE
EN
NA
L
V3RO
Disable
Enable
Enable
Logic
Reset
Active
Active
VCC
VG
SPI
Drivers
High−Z
Low
L
H
Disable
Enable
Enable
Disable
Enable
Enable
Disable
Enable
Enable
Standby
Normal
NA
H
Active
A high level on WAKE pin activates the IC from sleep
mode and enables the internal linear regulator at V3RO.
Once the voltage on V3RO as sensed on V3RI has passed the
power on reset (POR) threshold the system oscillator starts,
and releases the internal digital reset. OTP register contents
are loaded into the system registers defining the power on
state of the LV8968BB and the VCC regulator voltage.
VCC is powering up next, holding the CPU reset line
VMCRES low until VCC passes its undervoltage level.
During the entire wake−up sequence, DIAG is masked for
VG undervoltage. After wake−up is complete, the IC enters
Standby mode and DIAG is activated to display internal
errors. During Standby mode full SPI access is possible.
Note that if the CPU watchdog was enabled via OTP, a
VMCRES low will be asserted after the watchdog first open
window (WDFOW) unless the watchdog is being triggered
properly. See section “Watchdog”.
A high on EN takes the LV8968BB from Standby to
Normal mode. Normal mode allows motor control and the
IC accepts control inputs via the motor control pins IH[1−3],
IL[1−3]. A low on EN disables the motor stage regardless of
the PWM input and returns the part back to Standby mode.
The IC is shut down by taking WAKE pin low if EN is low.
If EN is high, a low on WAKE will be ignored until the
microcontroller pulls EN low.
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LV8968BBUW
WAKE
V3RO , V3RI
TWTPOR
Reset
Active
Active
Reset
Power On Reset
Analog &
Driver Standby
Standby
Standby
Execute MRODL Command
OTP Download
VCC Standby
TDNLD
TDNLD
(Protections are masked)
Standby
Active
Standby
VCC
TVCSU
VCC Under
Voltage Mask
Mask
Active
Mask
VMCRES
Standby
Active
Standby
VG Standby
VG
TVGSU
VG Under
Voltage Mask
Mask
Active
Mask
EN
Overcurrent &
FET Short Mask
Mask
Active
Mask
Other Protection
Mask
Mask
Active
Mask
SMOD[1:0]
Register
SMOD[1:0] = 1h
(Start-Up Time) × 1
SO Pin = Hi-Z
(Sleep Mode)
SMOD[1:0] = 2h
(Standby Mode)
SMOD[1:0] = 3h
(Normal Mode)
SMOD[1:0] = 2h
(Standby Mode)
SO Pin = Hi-Z
(Sleep Mode)
OFF
If EN = H,driver can drive according to input
Driver Output
NOTE: Even if EN = H, driver status is not changed to normal mode.
Figure 5. Powerup and Shutdown Timing
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LV8968BBUW
Operating Voltage Range
• The VG regulator for the gate voltages of the inverter
Normal operation with full functionality is guaranteed
from 8 V to 25 V. The device will operate from 4.5 V to 40 V
with limited performance:
stage
Internal Regulator (V3RO, V3RI)
The internal regulator provides 3.3 V at V3RO and takes
its feedback from V3RI. V3RO and V3RI need to be
connected externally and decoupled with capacitor to GND
for stability.
Shutdown: VS < VSLOF
The IC will be off. Gate drivers are Hi−Z.
(min)
Undervoltage: VSLOF < VS < VSUVTH
(min)
VS undervoltage warning/protection will be active
according to VSUVPS. VG undervoltage warning may be
asserted. If VCC is programmed to provide 3.3 V to the
LDO 3.3 / 5 V (VCC)
VCC becomes active during Start−Up, where after
Standby mode is entered. The VCC voltage can be
configured via registers to provide 5 V or 3.3 V. VMCRES
low is asserted if the output voltage drops below the
threshold levels. VCC may power external loads and must
be decoupled to GND with an external capacitor. The
voltage level is programmed in register VCVSEL with OTP
backup.
microcontroller, it will be supplied even if VS < VSLO
.
(min)
If motor operation is required during Undervoltage, see
section below “Motor Operation during Undervoltage”.
Normal VS Drive Mode: VSUVTH < VS < VSOVTH
Normal operation.
VS High Voltage Operation: VSOVTH < VS < VDHOVTH
Normal operation: VS high voltage warning/protection
might be active according to VSOVPS.
Gate Voltage Regulator (VGIN,VG)
The gate voltage regulator is supplied by VGIN and
regulates to either VGNO or VGLO at VG. The voltage level
is programmed in register VGVSEL with OTP backup.
VG provides the drive voltage for the low−side drivers
GL[1−3] directly and for the high−side drivers BS[1−3]
through the bootstrap circuitry. The output is current limited
to 40 mA(min). The output at VG should be decoupled with
VDH High Voltage Operation:
VDHOVTH < VS < VSLOF
(max)
VDH high voltage warning/protection might be active
according to VDOVPS. The driver stage can be
programmed to let the motor freewheel to protect the
bootstrap circuitry at BS[1−3] from overstress. This works
if the motor is not operating in field weakening.
a capacitor C to GND which should be at least 20 times
VG
the maximum gate charge of the power FETs.
In case of active braking, or field weakening operation,
the microcontroller will have to react to a VDH overvoltage
warning by either disabling the driver stage or activating all
low−side FETs to brake the motor. The maximum allowed
VS level for motor operation depends on the driver FET
type: VSNO(Max.) or VSLO(Max.). For additional
protection add zener diodes to the bootstrap pins.
Motor Control Inputs
Once the LV8968BB is in standby mode with the supplies
running, a microcontroller can facilitate motor control via
the inputs EN, IL[1−3], IH[1−3]. All are VS compatible.
PWM Interface (PWMIN, RXD)
The PWM interface translates a VS level signal with a
threshold of 40% and 60% VS to a digital signal appearing
at RXD. This RXD signal can be used for input PWM signal
translation to the microcontroller.
Case of abnormal state such as PWMIN pin is Open or
Short, RXD signal shows Low DC voltage level.
Additionally, PWMIN a supply level compatible level
shifter can bring a high voltage control such as a PWM
signal or a crash indicator to microcontroller supply level.
Motor Operation during Undervoltage
An undervoltage charge pump is not included into the
LV8968BB to save cost. If undervoltage operation of the
motor is desired either an external charge pump must be
inserted between VS and VGIN, or it is possible to use the
device in logic level mode by setting MRCONF0[1]. In the
latter case logic level FETs must be used for the inverter
stage.
Drive Enable (EN)
System Power Supplies
Taking EN high enables the output drivers GH[1−3] and
GL[1−3] for control by the microcontroller, taking EN low
disables them by switching all of them to the sources of the
corresponding external FETs. In addition, a high on EN will
override a low on WAKE allowing the microcontroller to
keep the motor running even after the WAKE line has gone
low.
Three power supplies are integrated into the LV8968BB,
all are supplied by VS:
• An internal 3.3 V regulator which provides power to
the digital and interface section
• A linear regulator to provide 5 V or 3.3 V for external
loads such as a microcontroller
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LV8968BBUW
Motor Control (IL[1−3] IH[1−3])
Drive 6 Mode
The individual motor phases are controlled by inputs
IL[1−3] and IH[1−3]. IH[1−3] are active high, while IL[1−3]
are active low allowing for parallel control with only three
PWM outputs using internal dead time. To control the driver
stage with GH [1−3] and GL[1−3] EN has to be “high”. The
LV8968BB will insert an adjustable dead time during output
transitions to prevent short circuiting the FETs. Two drive
modes exist:
In drive 6 mode, each input independently controls its
corresponding output requiring 6 independent PWM
channels in the microcontroller. A “high” on IH1 will result
in a “high” on GH1. A “high” on IL1 will result in a “low”
on GL1, and so forth. Trying to force a short by driving IH1
high and IL1 low will be ignored by the logic of the
LV8968BB.
Table 5. DRIVE 6 MODE
Input
Output
IH[1−3]
IL[1−3]
GH[1−3]
GL[1−3]
L
L
L
H
L
L
L
H
L
L
L
H
H
L
H
H
Drive 3 Mode
This mode is suitable for small microcontrollers which do
not have 6 dedicated PWM control lines. IL[1−3] serve as
enable signals for the phase drivers GH[1−3] and GL[1−3]
while IH[1− 3] serve as their PWM inputs. Connect the
microcontroller’s PWM line to IH[1−3] and the phase select
lines to the individual IL inputs 1−3 respectively.
Table 6. DRIVE 3 MODE
Input
Output
IH[1−3]
IL[1−3]
GH[1−3]
GL[1−3]
L
L
L
H
L
L
L
L
H
L
H
H
L
H
H
L
Gate Drive
implemented that begins counting after one driver has been
The gate drive circuit of the LV8968BB includes 3
half−bridge drivers which control six external N−Channel
FETs. The high−side gate drivers GH[1−3] switch their gate
connection either to corresponding BS[1−3] pin or the
respective phase connection SH[1−3]. The low−side gate
drivers GL[1−3] are switched from VG to the corresponding
source connection SL[1−3]. Both high− and low−side
switches are hard switching, but saturate around IGOLIM
for pullup/down currents. Slope control has to be
implemented with gate resistors.
turned off, and blocks the turning−on of the complementary
driver for a programmable time t
.
FDTI
Dead Time Counter
The dead time counter uses a fixed minimum dead time
which can be programmed into 4bit parameter FDTILIM.
The dead time is never allowed to fall below that value.
A dynamic dead time register FDTI allows dead time
variation during motor operation. This register is uploaded
at the beginning of every dead time measurement. Flag
FDTIBSY is high when a dead time value has been written
to register FDTI but was not uploaded to the counter, yet.
Two consecutive writes to FDTI before a counter upload are
flagged as an SPI error by setting bit SACF in the SPI status
register GSDAT.
“Through Current Prevention Function”
Current shoot through protection of the bridge drivers is
implemented by ignoring inputs at IH[n] and IL[n] that
would result in turning on of both high−and low−side FET
at the same time. In addition a dead time counter is
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LV8968BBUW
SPI write
FDTIBSY
FDTI
FDTI = 4 H write is ignored by
FDTIBSY = H.
0 h
5 h
2 h
6 h
FDTI and FDTILIM are compared and
smaller (longer dead time) one is selected.
FDTILIM
Gx_FDTI_LT
Gx_EDGE
DEAD TIME
0 h
2 h
5 h
3.2 us
2.8 us
2.2 us
Figure 6. Dead Time Programming
Short Protection
is determined by CSOFEN relative to an internal reference
which can be either 200 mV(typ) for unidirectional current
sensing, or 1.5 V(typ) for sensing current in both directions.
The output of the current sense amplifier appears on the ISO
pin.
To protect against FET shorts the drain−source voltage of
the active external power FETs is monitored. The drain
source voltage of the high−side FETs is monitored between
VDH and the corresponding source SH[1−3]. While the
low−side FETs are monitored between SH[1−3] and
SL[1−3]. After activation of the FET the short detection is
Overcurrent Shutoff
A parallel path implements fast overcurrent shutoff of the
driver stage. Overcurrent shutoff is triggered if the voltage
across ISP − ISN exceeds a programmable level as defined
by register OCDL. In overcurrent shutoff all gate drivers go
to Hi−Z, turning the power FETs high impedance and letting
the motor freewheel – this reaction is maskable. For more
information on masking and recovery see section “System
Errors and Warnings” on page 18.
masked for time t
to allow for signal settling. If after the
FSFT
masking time t
continues for t
the FET voltage exceeding V
FSFT
FSDL
, a FET short error is flagged. For details
FSDT
see “System Errors and Warnings” on page 18.
Four bits register FSDL selects the FET short protection
shutoff voltage VFSDL. The masking time TFSDT is set
with bits FSDT[1:0] and a debounce filter time TFSFT is set
with bits FSFT[1:0]. Both parameters residing in register
MRCONF6. These registers are dynamic and FSDL can be
changed during motor operation, though FSFT and FSDT
can be changed when EN = L.
To suppress switching transients, an overcurrent masking
time can be programmed into register OCMASK.
Temperature Sensing
The LV8968BB monitors internal junction temperature
Current Sensing and Overcurrent Shutoff
T . The voltage representing this temperature (V ) can be
PTAT
j
Single shunt current sensing can be implemented with the
integrated high speed sense amplifier. It amplifies the
voltage across ISP – ISN with a programmable gain defined
by register CSGAIN. Access to this register is dynamic,
allowing gain adjustment during motor operation. The offset
sampled at AOUT as described below. Thermal warnings
and errors are issued if T exceeds the levels defined by
J
THTSEL:
Table 7. THERMAL THRESHOLDS
THTSEL
Thermal Warning
Thermal Shutoff
150°C
0
1
125°C
150°C
175°C
If thermal error shutoff is activated, VG and VCC turn off,
and the driver stage goes high impedance. As a result
VMCRES goes low and SPI communication is disabled as
well. The exact failure modes and masks are described in
section “System Errors and Warnings”.
BEMF and other Measurements
The LV8968BB includes a multiplexer for measuring the
phase voltages, the motor voltage and the IC temperature.
Depending on the state of AOUTSEL the following voltages
appear on AOUT:
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LV8968BBUW
Table 8. AOUT SELECTION
MRAOSEL[2:0]
Pin
Formula
Comment
Motor Supply Voltage
0
1
VDH
SH1
SH2
SH3
−
V
= 32 V
VDH
AOUT
AOUT
AOUT
AOUT
V
V
V
= 16 V
= 16 V
= 16 V
Phase Voltage 1
SH1
SH2
SH2
2
Phase Voltage 2
3
Phase Voltage 3
4, 5
6, 7
T (°C) = 0.53 x V
(mV) − 216
Internal junction temperature
J
AOUT
−
High Impendance
Watchdog
during closed window time or the watchdog time expires.
Watchdog error effects can be customized. For detailed error
behavior a masking see section “System Errors and
Warnings”.
After a watchdog induced microcontroller reset, the error
register contents of registers MRDIAG[0] remain conserved
until an SPI read access. This helps the microcontroller
identify the fault condition.
The LV8968BB includes a window watchdog to monitor
the microcontroller. The size of the watchdog window is
defined by register WDTWT. For detailed timing
information see Figure 7: Window Watchdog Timing.
A write access to register MRRST during open window time
resets the watchdog timer and it starts counting again. The
watchdog will issue an error whenever MRRST is written to
WAKE
MCRES
Twt
Tcw
Tcw
Tfow
Twt
WDT
Status
First Open
Window
Closed
Window
Reset by
Open
Window
Closed
Window
Open
Window
Standby
MRRST= 00h command
DIAG
WAKE
MCRES
Tmr
Tcw
Tcw
Twt (Not reset)
Tfow
WDT
Status
Open
Window
Closed
Window
Open
Window
First Open
Window
Reset
microcontroller
Closed
Window
DIAG
Read MRDIAG0
DIAGS,
WDTPO
Register
WAKE
VMCRES
Tmr
Tcw
Tcw
Tcw
Twt
Tfow
WDT
Status
Closed
Window
Open
Window
Closed
Window
First Open
Window
Reset
microcontroller
Closed
Window
Reset timing
is too first
DIAG
Read MRDIAG0
DIAGS,
WDTPO
Register
Figure 7. Window Watchdog Timing
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LV8968BBUW
Table 9. WINDOW WATCHDOG TIMING OPTIONS (T = −40 to 150 °C, VS = 4.5 to 40 V)
J
Symbol
Characteristic
Min
Typ
Max
Unit
T
FOW
WDT first open window time
WDTWT[2:0] = 0h
WDTWT[2:0] = 1h
: (1/2 step)
ms
390.0
195.0
:
409.6
204.8
: (1/2 step)
3.2
431.2
215.6
:
WDTWT[2:0] = 7h
3.0
3.4
T
CW
WDT closed window time
WDTWT[2:0] = 0h
WDTWT[2:0] = 1h
: (1/2 step)
ms
97.4
48.7
:
102.4
51.2
:(1/2 step)
0.8
107.8
53.9
:
WDTWT[2:0] = 7h
0.7
0.9
T
WT
WDT window time
WDTWT[2:0] = 0h
WDTWT[2:0] = 1h
: (1/2 step)
ms
195.0
97.4
:
204.8
102.4
:(1/2 step)
1.6
215.6
107.8
:
WDTWT[2:0] = 7h
1.4
1.7
T
MR
WDT microcontroller reset time
333
400
422
ms
System Errors and Warnings
case the LV8968BB will keep the output stage disabled until
the latch is cleared by one of the following actions:
• Power on reset
System errors and warnings are always flagged in their
corresponding register MRDIAG0 and MRDIAG1 and their
presence is indicated in SPI status register GSDAT. The
LV8968BB gives great flexibility in modifying the error
response. Error response definition can be backed up into
OTP.
All system errors and warnings can cause a transition on
DIAG. The polarity of this transition is selected in bit
DIAGPOL. DIAG should be connected to an interrupt input
of the microcontroller. Errors that can cause serious damage
such as short−circuit and overcurrent may be latched by
enabling the corresponding latch bit in MRCONF7. In this
• EN low
• SPI write of FFh to MRRST
Table 10 explains the error behaviour. “Error” names the
type of error that is covered. “Reaction Settings Option”
lists which options exists for this error and the
corresponding register. ”Reaction names what happens if
the error occurs. Some reactions depend on the “Setting
Options” and are described in Notes below.
Table 10. SYSTEM ERROR AND WARNING RESPONSE MATRIX
Reaction Setting Options
Reaction
Setup
Register
Mask Report on
Auto
Recover
Latch
Off
MC
RES
Recovery
Condition
Protection
Enabled
Error
DIAG
VG
DRV
VCC
Error
VS
Under
Voltage
VSUVPS
[1:0]
Yes
Yes
Yes
No
ON
(Note 6)
ON
H
VS voltage
recovers
After OTP
download
VS Over
Voltage
VSOVPS
[1:0]
Yes
Yes
Yes
Yes
Yes
Yes
No
No
ON
ON
(Note 6)
(Note 6)
ON
ON
H
H
VS voltage
recovers
After OTP
download
VDH
Over
Voltage
VDOVPS
[1:0]
VDH voltage
recovers
After OTP
download
VG
Under
Voltage
VGUVPS
[1:0]
Yes
No
Yes
No
Yes
Yes
No
No
ON
ON
(Note 6)
OFF
ON
ON
H
L
VG voltage
recovers
After VG
start−up
time
VCC
Under
Voltage
−
VCC voltage
recovers
After VCC
start−up
time
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LV8968BBUW
Table 10. SYSTEM ERROR AND WARNING RESPONSE MATRIX
Reaction Setting Options
Reaction
Setup
Register
Mask Report on Auto
Latch
Off
MC
RES
Recovery
Condition
Protection
Enabled
Error
DIAG
Recover
VG
DRV
VCC
Error
Over
Current
OCPS
[1:0]
Yes
Yes
Yes
Yes
ON
(Note 6)
ON
H
[Latch Off]
EN = H
(Normal
mode)
EN = L or
execute
MRRST = Ffh
command
[Auto Recover]
EN = L or after
ecovery time
[Report]
EN = L or motor
current is down
FET
Short
FSPS
[1:0]
Yes
Yes
Yes
Yes
ON
(Note 6)
ON
H
[Latch Off] EN =
L or execute
MRRST = FFh
command
EN = H
(Normal
mode)
[Auto Recover]
EN = L or after
recovery time
[Report] EN = L
or FET short
current is down
Thermal
Warning
THWPS
THSPS
WDTPS
Yes
Yes
Yes
Yes
No
No
No
Yes
Yes
No
No
No
ON
(Note 7)
ON
ON
ON
(Note 7)
ON
H
Temperature is
down
After OTP
download
Thermal
Shutdown
(Note 7)
(Note 7)
(Note 8)
(Note 9)
Temperature is
down
After OTP
download
Watchdog
Timer
After output
reset pulse from
VMCRES pin
VMCRES
= H
6. Report or Ignore = ON, Latch Off or Auto Recover = OFF
7. Ignore = ON, Auto Recover = OFF
8. Ignore = H, Auto Recover = L
9. Ignore = Fixed H, Auto Recover = Output L pulse
SPI Interface
In the LV8968BB the SPI Interface is used to perform
general communications for status reporting, control and
programming.
CSB
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
1
SCLK
SI
WEN
ADDR [6:0]
GSDAT [6:0]
WDAT [7:0]
SO
Hi-Z
Hi-Z
RDAT [7:0]
(previous data)
Figure 8. SPI Format in Write Mode
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LV8968BBUW
CSB
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
1
SCLK
WDAT [7:0]
(ignored)
SI
WEN
ADDR [6:0]
GSDAT [6:0]
SO
Hi-Z
Hi-Z
RDAT [7:0]
Figure 9. SPI Format in Read Mode
SPI communications with the LV8968BB follows
established industry standard practices including the use of
WEN and start and stop bits as shown above. Data is
transferred MSB first and both clock and data are transferred
as ’true’ data with the higher level indicating a logical 1 or
true state.
• It is important the system master have the clock and
data polarities and phases as shown above. Both the
clock and data on some systems can be inverted for
various reasons but must arrive at the LV8968BB per
the above drawing. Common errors include SCLK
inversion such that the leading edge arrives as
There are two items to be especially careful of with the
general communication scheme:
a downward transition rather than a rising edge,
or having the data to clock phase incorrect. Data phase
must be such that the data only changes during a clock
falling edge and is completely stable during a clock
rising edge. This means a good margin of one half a bit
time exists to eliminate transmission delay hazards.
• Communications must be full duplex and simultaneous.
It is not allowed to send one transaction and then read
data on a second transaction as the status register
information will be updated on the first transaction and
then be out of date for the second. Some systems break
transactions into separate read and write operations
which is not acceptable
The first byte returned on all transactions is always the
status register GSDAT, and contains information such as the
busy flag during programming operations
Table 11.
GSDAT[7:0]
Bit 7
0
6
ORBEN
NA
5
SACF
NA
NA
NA
NA
0
4
DIAGS
NA
3
LATCH
NA
2
OBSY
NA
NA
NA
NA
0
1
Bit 0
SMOD[1:0]
NA
NA
NA
NA
NA
NA
NA
0
NA
1
Sleep mode
Device start−up time
Standby mode
NA
NA
NA
NA
NA
NA
1
0
NA
NA
NA
1
1
Normal mode
0
0
0
NA
NA
NA
NA
Normal Operation
NA
NA
NA
NA
1
OTP download of default
values
NA
NA
NA
NA
NA
NA
NA
1
NA
NA
1
NA
1
1
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Latched shutdown condition
Failure Condition
NA
NA
NA
NA
NA
Last SPI access failed*
OTP integrity test mode
NA
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LV8968BBUW
The following SPI failures are detectable and reported
collectively by a high on SACF in GSDAT[5] as general SPI
failures:
♦ Write access to any of the OTP registers after
OSAENB = 1 (Implies Reg. address 40 h to 43 h are
locked)
♦ Any access to an address which is not assigned.
♦ The number of SCLK edges is not 16 within one
word transfer
♦ Any access to MRCONF and ORCONF while
OBSY = 1, (During write operations)
♦ Write access to MRODL register while OBSY = 1,
(during write operations)
♦ Write access attempt to a read only or locked
register
♦ SI signal changed at positive edge of SCLK
(Incorrect data/sclk phase setup)
♦ Write access to dead time register FDTI while
FDTIBSY is still high (last value has not been
uploaded)
♦ Write access to any of the main registers after
setting MSAENB = 1 (Implies Reg. address 04 h to
07 h are locked)
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LV8968BBUW
SPI Timing
90%
10%
90% 90%
Tcsp
CSB
SCLK
SI
10%
Tcss
1/Tfck
Tckn Tckp Tcsh
90%
Tsih
90% 90%
10%
10%
Tsis
10% 10%
10%
Tcssod
90% 90%
10% 10%
Tcksod
Tcssoo
Tcssoz
90%
10%
SO
10%
Figure 10. SPI Timing Diagram
Table 12. SPI TIMING (T = −40 to 150°C, VS = 4.5 to 40 V, SO load = 50 pF)
J
Symbol
Comment
Min
Typ
Max
Unit
MHz
ns
T
T
SCLK Clock Frequency
SCLK High Pulse Width
SCLK Low Pulse Width
CSB Setup Time
4.5
FCK
CKP
CKN
CSS
CSH
CSP
90
90
90
0
T
T
T
T
ns
ns
CSB Hold Time
ns
CSB High Pulse Width
SI Setup Time
90
45
45
ns
T
SIS
ns
T
SIH
SI Hold Time
ns
T
T
T
SCLK Fall Edge to SO Delay Time
CSB Fall Edge to SO Delay Time
CSB Fall Edge to SO Data Out Time
CSB Rise Edge to SO Hi−Z Out Time
75
75
ns
CKSOD
CSSOD
CSSOO
ns
0
ns
T
75
ns
CSSOZ
NOTE: SPI−Interface can be used after the data download of the OTP has been completed. However it can not be used during VMCRES = L.
OTP Programming
The OTP register data is typically transferred into the
main registers at device start−up (From sleep to standby
transition). This operation takes up to 125 ms. A high OBSY
flag in the first returned byte during a SPI transaction
indicates this.
POR Ready
Download Data
WAKE
OBSY
Figure 11. OTP Data Download Timing at Start−Up
An OTP download can also actively be initiated by
writing 00h to register MRODL. This command requires
monitoring the OBSY flag. Don’t perform specific register
access (MRCONF0 ~ 3, ORCONF0 ~ 3, MRORB,
MRODL) until the OBSY flag is cleared.
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LV8968BBUW
Write MRODL Register
OBSY
Download Data
Figure 12. OTP Data Download Timing after an MRODL Command
OTP Programming Overall
Figure 13 shows overall of the OTP memory write and
verify flow. It consists of preparation, write and three times
of data integrity verification.
START
Set LV8968BB
standby
Apply VS> 14V
Write Data
Set mode to
L-side read check
Verify
Set mode to
H-side read check
Verify
Set mode to
Normal
Verify
END
Figure 13. OTP Memory Write and Verify Flow
OTP Programming
The OBSY flag will be reset at the end of the write cycle.
OBSY is in GSDAT register. To get GSDAT, SPI accesses
to the register MRACK is recommended. MRACK doesn’t
interfere with the programming operation.
MRCONF0 ~ 3, ORCONF0 ~ 3, MRORB, MRODL
registers cannot be accessed during an OTP write cycle.
The OTP registers can be programmed in Standby mode
only while the write lock bit OSAENB is set 0. And, the
supply voltage at pin VS must be more than 14 V. The actual
write operation to the OTP memory will be done, when the
state change from 0 to 1 is commanded. Once the bit state is
changed to 1, it cannot be change back to 0. The number of
writing is limited to one per bit.
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LV8968BBUW
Write OTP Data
OBSY
Internal Write Time
Figure 14. OTP Programming Timing
The programming takes 4 ms maximum. To simplify
operation, a waiting for 4 ms plus margin can be applicable
instead of a polling of the flag OBSY. (Figure 15)
START
WRITE DATA
Write data to address 40h
Wait for 4 ms or more
Write data to address 41h
Wait for 4 ms or more
Write data to address 42h
Wait for 4 ms or more
Write data to address 43h
Wait for 4 ms or more
END
Figure 15. OTP Memory Write and Verify Flow
OTP Data Integrity Verification
3. Verify that the main register contents are
consistent with the programmed OTP data
4. Set OTP readout threshold “high” by setting
ORBEN = 1 and ORBLV = 1 in register MRORB
5. Execute OTP download command by writing 00h
to MRODL
6. Verify that the main register contents are
consistent with the programmed OTP data
7. Return OTP threshold to normal by setting
ORBEN = 0 and ORBLV = 0
In order to verify that the OTP programming operation
was successful. It is strongly recommended to do an OTP
margin check: To do this, the OTP registers are downloaded
into the main register bank with minimum and maximum
readout thresholds. This OTP download is forced by writing
00h to register MRODL. The readout threshold is set in
register MRORB.
OTP Margin read check sequence after programmed:
1. Set OTP readout threshold “low” by setting
ORBEN = 1 and ORBLV = 0 in register MRORB
2. Execute OTP download command by writing 00h
to MRODL
8. Execute OTP download command
9. Verify that the main register contents are
consistent with the programmed OTP data
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LV8968BBUW
Locking OTP Register Contents
CAUTION: Inadvertent writing of these bits will
permanently lock the corresponding register
blocks from any further write access.
Should only be set at end of development
cycles.
MSAENB bit and OSAENB bit are used in order to
prevent write−access of main− and OTP registers
respectively.
Table 13. REGISTER MAP
WENB by
WEN (1bit)
Write Time
Condition
ADDR
[6:0]
Data
Name
D[7]
0
D[6]
D[5]
SACF
THTSEL
0
D[4]
D[3]
D[2]
OBSY
D[1]
SMOD[1:0]
D[0]
Don’t care
Don’t care
EN=L
−
GSDAT
MRCONF0
MRCONF1
MRCONF2
MRCONF3
MRCONF4
MRCONF5
MRCONF6
MRCONF7
MRCONF8
MRAOSEL
MRCSG
ORBEN
DIAGS
DFCSEL
WDTPS
LATCH
DIAGLTO
THSPS
OSAENB
(Note 10)
00h
01h
02h
03h
04h
05h
06h
07h
08h
10h
11h
12h
13h
14h
15h
16h
17h
20h
21h
22h
40h
41h
42h
43h
0
0
0
0
0
DIAGPOL
THWPS
VGVSEL
VCVSEL
0
VGUVPS[1:0]
VSUVPS[1:0]
0
VDOVPS[1:0]
VSOVPS[1:0]
Read Only
Read Only
EN=L
0
0
0
0
0
0
0
OSAENB
D3MDEN
MSAENB
(Note 10)
0
WDTWT[2:0]
CSOFEN
AWODLEN
0
0
0
OCDL[1:0]
OCMASK[3:0]
0
0
0
FSFT[1:0]
FSDT[1:0]
FSPS[1:0]
OCPS[1:0]
FDTILIM[3:0]
EN=L or H
EN=L or H
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MSAENB
EN=L or H
AOUTSEL[2:0] (Default=7h)
CSGAIN[1:0]
MRFSDL
MRFDTI
FSDL[3:0]
FDTI[3:0]
MRFDTIF
MRRST
0
0
0
FDTIBSY
Write 00h: Reset WDT / Write FFh: Reset latch off
EN=L
MRORB
0
0
0
0
0
0
ORBEN
ORBLV
MRODL
Write 00h: Execute OTP data download
Read Only
Read Only
MRDIAG0
MRDIAG1
MRACK
0
0
0
0
0
1
0
WDTPO
VCUVPO
1
THSPO
VGUVPO
0
THWPO
VDOVPO
1
FSPO
VSOVPO
0
OCPO
VSUVPO
1
0
0
OSAENB
(Note 10)
EN=L
ORCONF0
ORCONF1
ORCONF2
ORCONF3
ORCONF0[7:6]
ORCONF1[7:5]
ORCONF2[7:6]
THTSEL
DFCSEL
WDTPS
DIAGLTO
THSPS
DIAGPOL
THWPS
VGVSEL
VCVSEL
VGUVPS[1:0]
VSUVPS[1:0]
OSAENB
VDOVPS[1:0]
ORCONF3[7:1]
VSOVPS[1:0]
NOTE: SPI access to addresses not listed here will result in an SPI access failure error (SACF).
10.At Test mode, ENB = 1 setting is ignored.
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LV8968BBUW
MRCONF0 (Default: 00h)
(Write Access Only when EN = Low. OTP Backup Possible)
ADDR
Data Name
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
00h
MRCONF0
0
0
THTSEL
DFCSEL
DIAGLTO
DIAGPOL
VGVSEL
VCVSEL
THTSEL: THermal Thresholds SELection
Temperature warning threshold and error selection.
♦ THTSEL = 0: Thermal warning = 125°C, Thermal shutdown = 150°C
♦ THTSEL = 1: Thermal warning = 150°C, Thermal shutdown = 175°C
DFCSEL: Diag Flag Clearing SELection
Defines the condition under which the error registers are reset, by error condition removed only, or by error condition
removed and subsequent SPI read access of the register in question.
♦ DFCSEL = 0: If error was cleared, DIAGS flag of GSDAT and MRDIAG0 and MRDIAG1 flags are reset by
MRDIAG0 read, MRDIAG1 read
♦ DFCSEL = 1: DIAGS flag of GSDAT and MRDIAG0 and MRDIAG1 flag are reset by recovery condition
DIAGLTO: DIAG pin Latched errors Transition Only
If this bit is set, only latched errors result in a transition on DIAG. Otherwise all errors (and warnings) will be flagged.
♦ DIAGLTO = 0: At the time of detecting auto recover or latch off error, DIAG output is on
♦ DIAGLTO = 1: At the time of detecting latch off error, DIAG output is on
DIAGPOL: DIAG pin POLarity
Decides the polarity of the DIAG output.
♦ DIAGPOL = 0: At the time of detecting diagnostic error, DIAG output is L
♦ DIAGPOL = 1: At the time of detecting diagnostic error, DIAG output is H
VGVSEL: VG pin Voltage SELection
Selects if the IC is in logic level mode or normal mode which modifies the gate voltage of the drive section.
♦ VGVSEL = 0: VG normal mode (VG = 11 V)
♦ VGVSEL = 1: VG logic level mode (VG = 6 V)
VCVSEL: VCc pin Voltage SELection
Selects the output voltage of VCC to be either 3.3 V or 5 V. The wrong bit selection has a possibility to damage the
microcontroller. Please make sure the appropriate selection.
♦ VCVSEL = 0: VCC = 3.3 V
♦ VCVSEL = 1: VCC = 5.0 V
MRCONF1 (Default: 00h)
(Write Access Only when EN = Low. OTP Backup Possible)
ADDR
Data Name
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
01h
MRCONF1
0
0
0
WDTPS
THSPS
THWPS
VGUVPS[1:0]
WDTPS: WatchDog Timeout Protection Setting
Watchdog error results in error response or is ignored.
♦ WDTPS = 0: Ignore WDT error
♦ WDTPS = 1: Emergency off and report a WDT error (Auto recover)
THSPS: THermal Shutdown Protection Setting
Thermal shutdown error results in error response or is ignored.
♦ THSPS = 0: Ignore thermal shutdown error
♦ THSPS = 1: Emergency off and report at thermal shutdown error (Auto recover)
THWPS: THermal Warning Protection Setting
♦ THWPS = 0: Ignore thermal warning error
♦ THWPS = 1: Report thermal warning error
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LV8968BBUW
VGUVPS[1:0]: VG pin UnderVoltage Protection Setting
♦ VGUVPS[1:0] = 0h: Ignore VG undervoltage error
♦ VGUVPS[1:0] = 1h: Report VG undervoltage error
♦ VGUVPS[1:0] = 2h, 3h: Emergency off and report at VG under voltage error (Auto recover)
MRCONF2 (Default: 00h)
(Write Access Only when EN = Low. OTP Backup Possible)
ADDR
Data Name
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
02h
MRCONF2
0
0
VDOVPS[1:0]
VSOVPS[1:0]
VSUVPS[1:0]
VDOVPS[1:0]: VDh OverVoltage Protection Setting
♦ VDOVPS[1:0] = 0h: Ignore VDH overvoltage error
♦ VDOVPS[1:0] = 1h: Report VDH overvoltage error
♦ VDOVPS[1:0] = 2h, 3h: Emergency off and report at VDH over voltage error (Auto recover)
VSOVPS[1:0]: VS OverVoltage Protection Setting
♦ VSOVPS[1:0] = 0h: Ignore VS overvoltage error
♦ VSOVPS[1:0] = 1h: Report VS overvoltage error
♦ VSOVPS[1:0] = 2h, 3h: Emergency off and report at VS over voltage error (Auto recover)
VSUVPS[1:0]: VS UnderVoltage Protection Setting
♦ VSUVPS[1:0] = 0h: Ignore VS undervoltage error
♦ VSUVPS[1:0] = 1h: Report VS undervoltage error
♦ VSUVPS[1:0] = 2h, 3h: Emergency off and report at VS under voltage error (Auto recover)
MRCONF3 (Default: 00h)
(Read Only)
ADDR
Data Name
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
03h
MRCONF3
0
0
0
0
0
0
0
OSAENB
OSAENB: Otp Spi write Access ENable Bar
Setting this bit disables all write access to the configuration registers MRCONF0, MRCONF1 and MRCONF2 and the OTP
backup register. Set to prevent system parameters from being modified.
♦ OSAENB = 0: Enable write access of MRCONF0~2 and ORCONF0~3
♦ OSAENB = 1: Disable write access of MRCONF0~2 and ORCONF0~3
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LV8968BBUW
MRCONF4 (Default: 00h)
(Write Access Only when EN = Low)
ADDR
Data Name
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
04h
MRCONF4
0
WDTWT[2:0]
0
CSOFEN
AWODLEN
D3MDEN
WDTWT[2:0]: Watchdog Timeout Window Time
Defines the watchdog timer window sizes.
♦ WDTWT[2:0] = 0h: T
= 409.6 ms, T = 102.4 ms, T = 204.8 ms
FOW
CW WT
♦ WDTWT[2:0]=1h: T
= 204.8 ms, T = 51.2 ms, T = 102.4 ms
CW WT
FOW
:
: (1/2 step)
:
♦ WDTWT[2:0] = 7h: T
= 3.2 ms, T = 0.8 ms, T = 1.6 ms
CW WT
FOW
CSOFEN: Current Sensor OFfset Enable
Selects the offset of the current sense amplifier.
♦ CSOFEN = 0: Current sense amp offset = 1.5 V
♦ CSOFEN = 1: Current sense amp offset = 0.2 V
AWODLEN: Automatic Window for Otp DownLoad Enable
Periodical (200 ms) OTP download during EN = H.
♦ AWODLEN = 0: Not download OTP data in normal mode
♦ AWODLEN = 1: Download OTP data periodically in normal mode
D3MDEN: Drive 3 Mode Drivers Enable
Chooses how the output drivers are addressed, with six PWM channels, or with three PWM channels and three enables.
♦ D3MDEN = 0: Drive 6 mode
♦ D3MDEN = 1: Drive 3 mode
MRCONF5 (Default: 00h)
(Write Access Only when EN = Low)
ADDR
Data Name
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
05h
MRCONF5
0
0
OCDL[1:0]
OCMASK[3:0]
OCDL[1:0]: OverCurrent Detection Level
Defines the overcurrent detection threshold voltage between ISN and ISP.
♦ OCDL[1:0] = 0h: Overcurrent detect level = 200 mV
♦ OCDL[1:0] = 1h: Overcurrent detect level = 150 mV
♦ OCDL[1:0] = 2h, 3h: Overcurrent detect level = 100 mV
OCMASK[3:0]: OverCurrent MASKing time
Masking time for the overcurrent detection after every output transition.
♦ OCMASK[3:0] = 0h: Overcurrent mask time = 0.2 ms
♦ OCMASK[3:0] = 1h: Overcurrent mask time = 0.4 ms
:
: (0.2 ms step)
:
♦ OCMASK[3:0] = Eh: Overcurrent mask time = 3.0 ms
♦ OCMASK[3:0] = Fh: Overcurrent mask time = 3.2 ms
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LV8968BBUW
MRCONF6 (Default: 00h)
(Write Access Only when EN = Low)
ADDR
Data Name
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
FSDT[1:0]
D[0]
06h
MRCONF6
0
0
0
0
FSFT[1:0]
FSFT[1:0]: Fet Short detection debounce Filter Time
External FET short detection debounce time. A short condition has to remain valid during this time.
♦ FSFT[1:0] = 0h: FET short detect time = 0.8 ms
♦ FSFT[1:0] = 1h: FET short detect time = 1.6 ms
♦ FSFT[1:0] = 2h: FET short detect time = 2.4 ms
♦ FSFT[1:0] = 3h: FET short detect time = 3.2 ms
FSDT[1:0]: Fet Short Detection masking Time
External FET short−circuit detection masking time, starts after turn−on of the FET.
♦ FSDT[1:0] = 0h: FET short masking time = 3.2 ms
♦ FSDT[1:0] = 1h: FET short masking time = 6.4 ms
♦ FSDT[1:0] = 2h: FET short masking time = 9.6 ms
♦ FSDT[1:0] = 3h: FET short masking time = 12.8 ms
MRCONF7 (Default: 00h)
(Write Access Only when EN = Low)
ADDR
Data Name
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
07h
MRCONF7
FSPS[1:0]
OCPS[1:0]
FDTILIM[3:0]
FSPS[1:0]: Fet Short−circuit error Protection Setting
Short−circuit error decision mask.
♦ FSPS[1:0] = 0h: Ignore FET short error
♦ FSPS[1:0] = 1h: Report FET short error
♦ FSPS[1:0] = 2h: Emergency off and report at FET short error (Auto recover)
♦ FSPS[1:0] = 3h: Emergency off and report at FET short error (Latched off)
OCPS[1:0]: OverCurrent error Protection Setting
Overcurrent error decision mask.
♦ OCPS[1:0] = 0h: Ignore overcurrent error
♦ OCPS[1:0] = 1h: Report overcurrent error
♦ OCPS[1:0] = 2h: Emergency off and report at overcurrent error (Auto recover)
♦ OCPS[1:0] = 3h: Emergency off and report at overcurrent error (Latched off)
FDTILIM[3:0]: Fet Dead TIme LIMit
Minimum Dead time programming register.
♦ FDTILIM[3:0] = 0h: FET dead time = 3.2 ms
♦ FDTILIM[3:0] = 1h: FET dead time = 3.0 ms
:
: (−0.2 ms step)
:
♦ FDTILIM[3:0] = Eh: FET dead time = 0.4 ms
♦ FDTILIM[3:0] = Fh: FET dead time = 0.2 ms
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LV8968BBUW
MRCONF8 (Default: 00h)
(Write access only when EN = Low)
ADDR
Data Name
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
08h
MRCONF8
0
0
0
0
0
0
0
MSAENB
MSAENB: Mrconf Spi write Access ENable Bar
Setting this bit disables all write access to the configuration registers MRCONF4 to MRCONF7.
♦ MSAENB = 0: Enable write access of MRCONF4 ~ 7
♦ MSAENB = 1: Disable write access of MRCONF4 ~ 7
MRAOSEL (Default: 07h)
(Full Dynamic Access)
ADDR
Data Name
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
10h
MRAOSEL
0
0
0
0
0
AOUTSEL[2:0]
AOUTSEL[2:0]: AOUT pin output SELect
Select the internal nodes brought out on AOUT.
♦ AOUTSEL[2:0] = 0h: AOUT = Output VDH voltage level
♦ AOUTSEL[2:0] = 1h: AOUT = Output SH1 voltage level
♦ AOUTSEL[2:0] = 2h: AOUT = Output SH2 voltage level
♦ AOUTSEL[2:0] = 3h: AOUT = Output SH3 voltage level
♦ AOUTSEL[2:0] = 4h, 5h: AOUT = Output thermal monitor voltage level
♦ AOUTSEL[2:0] = 6h, 7h: AOUT = Hi−Z
MRCSG (Default: 00h)
(Full Dynamic Access)
ADDR
Data Name
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
11h
MRCSG
0
0
0
0
0
0
CSGAIN[1:0]
CSGAIN[1:0]: Current Sense GAIN
Programs the gain of the current sense amplifier.
♦ CSGAIN[1:0] = 0h: Current sense amp gain = 7.5
♦ CSGAIN[1:0] = 1h: Current sense amp gain = 15
♦ CSGAIN[1:0] = 2h: Current sense amp gain = 22.5
♦ CSGAIN[1:0] = 3h: Current sense amp gain = 30
MRFSDL (Default: 00h)
(Full Dynamic Access)
ADDR
Data Name
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
FSDL[3:0]
D[0]
12h
MRFSDL
0
0
0
0
FSDL[3:0]: Fet Short Detection Level
Defines the maximum allowable drain source voltage across a power FET.
♦ FSDL[3:0] = 0h: FET short detect level = 100 mV
♦ FSDL[3:0] = 1h: FET short detect level = 200 mV
:
: (100 mV step)
:
♦ FSDL[3:0] = Eh: FET short detect level = 1500 mV
♦ FSDL[3:0] = Fh: FET short detect level = 1600 mV
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LV8968BBUW
MRFDTI (Default: 00h)
(Full Dynamic Access)
ADDR
Data Name
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
FDTI[3:0]
D[0]
13h
MRFDTI
0
0
0
0
FDTI[3:0]: Fet Dead TIme
Dead time programming register. This dead time will be applied unless it is smaller than FDTILIM[3:0] in MRCONF7.
♦ FDTI[3:0] = 0h: FET dead time = 3.2 ms
♦ FDTI[3:0] = 1h: FET dead time = 3.0 ms
:
: (−0.2 ms step)
:
♦ FDTI[3:0] = Eh: FET dead time = 0.4 ms
♦ FDTI[3:0] = Fh: FET dead time = 0.2 ms
MRFDTIF (Default: 00h)
(Full Dynamic Access)
ADDR
Data Name
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
14h
MRFDTIF
0
0
0
0
0
0
0
FDTIBSY
FDTIBSY: Fet Dead TIme BuSY uploading
FDTIBSY goes high after the dead time register was written to via SPI but not uploaded into the dead time counter. Upload
happens at the beginning of every dead time measuring period (falling edge of a gate signal) and clears the FDTIBSY flag.
A write access MRFDTIF = 01h also clears the FDTIBSY flag.
MRRST
(Full Dynamic Access)
ADDR
Data Name
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
15h
MRRST
Write 00h: Reset WDT / Write FFh: Reset latch off
MRRST[7:0]: Master Register ReSeT
Write access to this register resets the Watchdog or the Error latch.
♦ Write MRRST[7:0] = 00h: Reset WDT
♦ Write MRRST[7:0] = FFh: Reset latch off
MRORB (Default: 00h)
(Register for OTP Programming Integrity Check. Write During EN = Low Only)
ADDR
Data Name
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
16h
MRORB
0
0
0
0
0
0
ORBEN
ORBLV
ORBEN: Otp Read Bias mode Enable
Setting this bit puts the device into OTP integrity check mode.
♦ ORBEN = 0: Normal
♦ ORBEN = 1: OTP bias read mode
ORBLV: Otp Read Bias mode LeVel
Changes the OTP readout thresholds to high and low, to verify data integrity.
♦ ORBLV = 0: OTP low bias read mode at ORBEN = 1
♦ ORBLV = 1: OTP high bias read mode at ORBEN = 1
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31
LV8968BBUW
MRODL
(Write Access During EN = Low Only)
ADDR
Data Name
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
17h
MRODL
Write 00h: Execute OTP data download
MRODL[7:0]: Master Register Otp DownLoad
A write initiates an OTP data download into the main registers in standby mode. In Normal mode, OTP download can be
initiated only when AWODLEN is set regardless of MRODL.
♦ Write MRODL[7:0] = 00h: Execute OTP data download
MRDIAG0
(Read Only)
ADDR
Data Name
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
20h
MRDIAG0
0
0
0
WDTPO
THSPO
THWPO
FSPO
OCPO
WDTPO: WatchDog Timeout Protection Output
Watchdog error flag.
♦ WDTPO = 0: Normal
♦ WDTPO = 1: Detect WDT error
THSPO: THermal Shutdown Protection Output
Over temperature shutoff flag.
♦ THSPO = 0: Normal
♦ THSPO = 1: Detect thermal shutdown error
THWPO: THermal Warning Protection Output
Thermal warning flag.
♦ THWPO = 0: Normal
♦ THWPO = 1: Detect thermal warning error
FSPO: FET Short−circuit Protection Output
FET short−circuit detection flag.
♦ FSPO = 0: Normal
♦ FSPO = 1: Detect FET short error
OCPO: OverCurrent Protection Output
Overcurrent error flag.
♦ OCPO = 0: Normal
♦ OCPO = 1: Detect overcurrent error
MRDIAG1
(Read Only)
ADDR
Data Name
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
21h
MRDIAG1
0
0
0
VCUVPO
VGUVPO
VDOVPO
VSOVPO
VSUVPO
VCUVPO: VCc UnderVoltage Protection Output
VCC undervoltage flag.
♦ VCUVPO = 0: Normal
♦ VCUVPO = 1: Detect VCC undervoltage error
VGUVPO: VG UnderVoltage Protection Output
VG undervoltage flag.
♦ VGUVPO = 0: Normal
♦ VGUVPO = 1: Detect VG undervoltage error
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32
LV8968BBUW
VDOVPO: VDh OverVoltage Protection Output
VDH overvoltage flag.
♦ VDOVPO = 0: Normal
♦ VDOVPO = 1: Detect VDH overvoltage error
VSOVPO: VS OverVoltage Protection Output
VS overvoltage flag.
♦ VSOVPO = 0: Normal
♦ VSOVPO = 1: Detect VS overvoltage error
VSUVPO: VS UnderVoltage Protection Output
VS undervoltage flag.
♦ VSUVPO = 0: Normal
♦ VSUVPO = 1: Detect VS undervoltage error
MRACK
(Read Only)
ADDR
Data Name
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
22h
MRACK
0
1
0
1
0
1
0
1
MRACK[7:0]: Master Register ACKnowledge
For SPI data verification. A read must result in 55h.
♦ MRACK[7:0] read data is fixed 55h
ORCONF0 ~ 3 (Default: 00h)
(OTP Backup for Critical System Registers. Programmable During EN = L Only)
ADDR
40h
Data Name
ORCONF0
ORCONF1
ORCONF2
ORCONF3
D[7]
ORCONF0[7:6]
ORCONF1[7:5]
ORCONF2[7:6]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
THTSEL
DFCSEL
WDTPS
DIAGLTO
THSPS
DIAGPOL
THWPS
VGVSEL
VCVSEL
41h
VGUVPS[1:0]
VSUVPS[1:0]
OSAENB
42h
VDOVPS[1:0]
ORCONF3[7:1]
VSOVPS[1:0]
43h
ORCONF0 ~ 3
♦ ORCONF0 ~ 3 data is transferred to MRCONF0 ~ 3 at OTP data download
♦ ORCONF0[7:6], ORCONF1[7:5], ORCONF2[7:6], ORCONF3[7:1] data is not transferred to MRCONF
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33
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SPQFP48 7x7 / SQFP48K
CASE 131AN
ISSUE A
DATE 08 NOV 2013
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON78439F
SPQFP48 7X7 / SQFP48K
PAGE 1 OF 1
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