MC100E137FNR2G [ONSEMI]
5 V ECL 8-Bit Ripple Counter; 5 V ECL 8位异步计数器
| 型号： | MC100E137FNR2G |
| 厂家： | 
ONSEMI |
| 描述： | 5 V ECL 8-Bit Ripple Counter |
| 文件： | 总9页 (文件大小：139K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC10E137, MC100E137
5 VꢀECL 8-Bit Ripple Counter
Description
The MC10E/100E137 is a very high speed binary ripple counter. The
two least significant bits were designed with very fast edge rates while
the more significant bits maintain standard ECLinPS™ output edge
rates. This allows the counter to operate at very high frequencies while
maintaining a moderate power dissipation level.
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The device is ideally suited for multiple frequency clock generation
as well as a counter in a high performance ATE time measurement
board.
Both asynchronous and synchronous enables are available to
maximize the device’s flexibility for various applications. The
asynchronous enable input, A_Start, when asserted enables the counter
while overriding any synchronous enable signals. The E137 features
XORed enable inputs, EN1 and EN2, which are synchronous to the
CLK input. When only one synchronous enable is asserted the counter
becomes disabled on the next CLK transition; all outputs remain in the
previous state poised for the other synchronous enable or A_Start to be
asserted to re-enable the counter. Asserting both synchronous enables
causes the counter to become enabled on the next transition of the CLK.
If EN1 (or EN2) and CLK edges are coincident, sufficient delay has
been inserted in the CLK path (to compensate for the XOR gate delay
and the internal D-flip flop setup time) to insure that the synchronous
enable signal is clocked correctly, hence, the counter is disabled.
All input pins left open will be pulled LOW via an input pulldown
resistor. Therefore, do not leave the differential CLK inputs open.
Doing so causes the current source transistor of the input clock gate to
become saturated, thus upsetting the internal bias regulators and
jeopardizing the stability of the device.
PLCC−28
FN SUFFIX
CASE 776
MARKING DIAGRAM*
1
MCxxxE137FNG
AWLYYWW
xxx
A
WL
YY
WW
G
= 10 or 100
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
The asynchronous Master Reset resets the counter to an all zero state
upon assertion.
The V pin, an internally generated voltage supply, is available to
BB
*For additional marking information, refer to
Application Note AND8002/D.
this device only. For single-ended input conditions, the unused
differential input is connected to V as a switching reference voltage.
BB
V
V
may also rebias AC coupled inputs. When used, decouple V and
via a 0.01 mF capacitor and limit current sourcing or sinking to
BB
BB
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
CC
0.5 mA. When not used, V should be left open.
BB
The 100 Series contains temperature compensation.
Features
• Differential Clock Input and Data Output Pins
• ESD Protection: Human Body Model: > 2 kV,
Machine Model: > 200 V
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC
Latchup Test
• Moisture Sensitivity Level: Pb = 1; Pb−Free = 3
For Additional Information, see Application Note
AND8003/D
• Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
• V Output for Single-Ended Use
BB
• Synchronous and Asynchronous Enable Pins
• Asynchronous Master Reset
• PECL Mode Operating Range: V = 4.2 V to 5.7 V
CC
with V = 0 V
EE
• NECL Mode Operating Range: V = 0 V
CC
with V = −4.2 V to −5.7 V
EE
• Internal Input 50 kW Pull−down Resistors
• Transistor Count = 330 devices
• Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
November, 2006 − Rev. 8
MC10E137/D
MC10E137, MC100E137
Q7
Q6
V
Q5
Q7
Q6
Q5
CCO
Table 1. PIN DESCRIPTION
24
23
22
21
19
25
20
PIN
FUNCTION
18
17
16
15
14
13
12
A_Start
EN1
26
27
Q4
Q4
V
CLK, CLK
ECL Differential Clock Inputs
Q0-Q7, Q0-Q7 ECL Differential Q Outputs
EN2
28
1
CC
A_Start
EN1, EN2
MR
ECL Asynchronous Enable Input
ECL Synchronous Enable Inputs
Asynchronous Master Reset
Reference Voltage Output
Positive Supply
Pinout: 28-Lead PLCC
Q3
Q3
Q2
Q2
V
EE
(Top View)
V
CLK
CLK
2
3
4
BB
V
V
, V
CCO
CC
Negative Supply
EE
V
BB
5
6
7
8
9
10
11
MR
V
Q0 Q0
Q1
Q1
V
CCO
CCO
* All V and V
pins are tied together on the die.
CCO
CC
Warning: All V , V
, and V pins must be externally
CCO EE
CC
connected to Power Supply to guarantee proper operation.
Figure 1. 28−Lead Pinout
A_Start
EN1
EN2
R
Q0 Q0
Q1 Q1
Q7 Q7
D
Q
CLK
Q
CLK
CLK
CLK
Q
Q
CLK
CLK
Q
Q
CLK
CLK
Q
Q
CLK
CLK
D
D
D
R
R
R
V
BB
MR
Figure 2. Logic Diagram
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2
MC10E137, MC100E137
Table 2. SEQUENTIAL TRUTH TABLE
Function
Reset
EN1
EN2
A_Start
MR
CLK
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
X
X
X
H
X
L
L
L
L
L
L
L
L
Count
L
L
L
L
L
L
L
L
L
L
L
L
Z
Z
Z
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
L
H
Stop
H
H
L
L
L
L
L
L
Z
Z
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
Asynch Start
H
H
L
L
L
L
H
H
H
L
L
L
Z
Z
Z
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
L
L
H
L
H
L
Count
L
L
L
L
L
L
L
L
L
L
L
L
Z
Z
Z
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
L
L
H
L
L
H
L
H
Stop
L
L
H
H
L
L
L
L
Z
Z
L
L
L
L
L
L
L
L
H
H
L
L
L
L
H
H
Synch Start
H
H
H
H
H
H
L
L
L
L
L
L
Z
Z
Z
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
L
L
H
H
H
L
L
H
L
Stop
H
H
L
L
L
L
L
L
Z
Z
L
L
L
L
L
L
L
L
H
H
H
H
L
L
L
L
Count
L
L
L
L
L
L
L
L
L
L
L
L
Z
Z
Z
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
L
H
H
H
L
H
Reset
X
X
X
H
X
L
L
L
L
L
L
L
L
Z = Low to High Transition
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
= 0 V
Condition 2
Rating
Unit
V
V
V
PECL Mode Power Supply
NECL Mode Power Supply
V
V
8
V
V
CC
EE
I
EE
CC
= 0 V
−8
PECL Mode Input Voltage
NECL Mode Input Voltage
V
V
= 0 V
= 0 V
V v V
6
−6
V
V
EE
CC
I
CC
V w V
I
EE
I
Output Current
Continuous
Surge
50
100
mA
mA
out
T
Operating Temperature Range
Storage Temperature Range
0 to +85
°C
°C
A
T
−65 to +150
stg
JA
q
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
PLCC−28
PLCC−28
63.5
43.5
°C/W
°C/W
q
Thermal Resistance (Junction−to−Case)
Standard Board
PLCC−28
22 to 26
°C/W
JC
V
PECL Operating Range
NECL Operating Range
4.2 to 5.7
−5.7 to −4.2
V
V
EE
T
sol
Wave Solder
Pb
Pb−Free
265
265
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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3
MC10E137, MC100E137
Table 4. 10E SERIES PECL DC CHARACTERISTICS V
= 5.0 V; V = 0.0 V (Note 1)
EE
CCx
0°C
25°C
85°C
Min
Typ
Max
145
Min
Typ
121
Max
145
Min
Typ
121
Max
145
Unit
mA
mV
Symbol
Characteristic
Power Supply Current
I
121
EE
V
Output HIGH Voltage (Note 2)
3980
40
70
4160
4020
4105
4190
4090
4185
4280
OH
V
V
V
V
V
Output LOW Voltage (Note 2)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
3050
3830
3050
3.62
2.2
3210
3995
3285
3370
4160
3520
3.73
4.6
3050
3870
3050
3.65
2.2
3210
4030
3285
3370
4190
3520
3.75
4.6
3050
3940
3050
3.69
2.2
3227
4110
3302
3405
4280
3555
3.81
4.6
mV
mV
mV
V
OL
IH
IL
BB
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 3)
V
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
IL
0.5
0.3
0.5
0.25
0.3
0.2
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with V . V can vary −0.46 V / +0.06 V.
CC
EE
2. Outputs are terminated through a 50 W resistor to V − 2.0 V.
CC
3. V
min varies 1:1 with V , max varies 1:1 with V
.
IHCMR
EE
CC
Table 5. 10E SERIES NECL DC CHARACTERISTICS V
= 0.0 V; V = −5.0 V (Note 4)
CCx
EE
0°C
Typ
121
−1020 −930
25°C
85°C
Min
Max
145
Min
Typ
121
Max
145
Min
Typ
121
Max
145
Symbol
Characteristic
Power Supply Current
Unit
mA
mV
mV
mV
mV
V
I
EE
V
Output HIGH Voltage (Note 5)
Output LOW Voltage (Note 5)
−840
−980
−895
−810
−910
−815
−720
OH
OL
V
V
V
V
V
−1950 −1790 −1630 −1950 −1790 −1630 −1950 −1773 −1595
−810 −1060 −890 −720
−1950 −1715 −1480 −1950 −1715 −1480 −1950 −1698 −1445
Input HIGH Voltage (Single−Ended) −1170 −1005 −840 −1130 −970
IH
Input LOW Voltage (Single−Ended)
IL
Output Voltage Reference
−1.38
−2.8
−1.27 −1.35
−1.25 −1.31
−1.19
−0.4
BB
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 6)
−0.4
−2.8
−0.4
−2.8
V
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
IL
0.5
0.3
0.5
0.065
0.3
0.2
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Input and output parameters vary 1:1 with V . V can vary −0.46 V / +0.06 V.
CC
EE
5. Outputs are terminated through a 50 W resistor to V − 2.0 V.
CC
6. V
min varies 1:1 with V , max varies 1:1 with V
.
IHCMR
EE
CC
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4
MC10E137, MC100E137
Table 6. 100E SERIES PECL DC CHARACTERISTICS V
= 5.0 V; V = 0.0 V (Note 7)
EE
CCx
0°C
Typ
25°C
Typ
85°C
Typ
Min
Max
145
Min
Max
145
Min
Max
167
Symbol
Characteristic
Power Supply Current
Unit
mA
mV
mV
mV
mV
V
I
121
121
139
EE
V
Output HIGH Voltage (Note 8)
Output LOW Voltage (Note 8)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
3975
3190
3835
3190
3.62
2.2
4050
3295
3975
3355
4120
3380
4120
3525
3.73
4.6
3975
3190
3835
3190
3.62
2.2
4050
3255
3975
3355
4120
3380
4120
3525
3.74
4.6
3975
3190
3835
3190
3.62
2.2
4050
3260
3975
3355
4120
3380
4120
3525
3.74
4.6
OH
OL
V
V
V
V
V
IH
IL
BB
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 9)
V
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
IL
0.5
0.3
0.5
0.25
0.5
0.2
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
7. Input and output parameters vary 1:1 with V . V can vary −0.46 V / +0.8 V.
CC
EE
8. Outputs are terminated through a 50 W resistor to V − 2.0 V.
CC
9. V
min varies 1:1 with V , max varies 1:1 with V
.
IHCMR
EE
CC
Table 7. 100E SERIES NECL DC CHARACTERISTICS V
0°C
= 0.0 V; V = −5.0 V (Note 10)
CCx
EE
25°C
85°C
Typ
139
Min
Typ
Max
Min
Typ
Max
Min
Max
167
Symbol
Characteristic
Unit
mA
mV
mV
mV
I
Power Supply Current
121
145
121
145
EE
V
Output HIGH Voltage (Note 11)
Output LOW Voltage (Note 11)
−1025 −950
−880 −1025 −950
−880 −1025 −950
−880
OH
OL
IH
V
V
−1810 −1705 −1620 −1810 −1745 −1620 −1810 −1740 −1620
−1165 −1025 −880 −1165 −1025 −880 −1165 −1025 −880
Input HIGH Voltage (Single−En-
ded)
V
Input LOW Voltage (Single−En-
ded)
−1810 −1645 −1475 −1810 −1645 −1475 −1810 −1645 −1475
mV
IL
V
V
Output Voltage Reference
−1.38
−3.8
−1.27 −1.38
−1.26 −1.38
−1.26
−0.4
V
V
BB
Input HIGH Voltage Common
Mode Range (Differential Configu-
ration) (Note 12)
−0.4
−3.8
−0.4
−3.8
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
IL
0.5
0.3
0.5
0.25
0.5
0.2
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
10.Input and output parameters vary 1:1 with V . V can vary −0.46 V / +0.8 V.
CC
EE
11. Outputs are terminated through a 50 W resistor to V − 2.0 V.
CC
12.V
min varies 1:1 with V , max varies 1:1 with V
.
IHCMR
EE
CC
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5
MC10E137, MC100E137
Table 8. AC CHARACTERISTICS V
= 5.0 V; V = 0.0 V or V
= 0.0 V; V = −5.0 V (Note 13)
CCx EE
CCx
EE
0°C
25°C
Typ
85°C
Typ
Min
Typ
Max
Min
Max
Min
Max
Symbol
Characteristic
Unit
MHz
ps
f
Maximum Count Frequency
1800
2200
1800
2200
1800
2200
COUNT
t
t
Propagation Delay to Output
PLH
PHL
CLK to Q0 1300
CLK to Q1 1600
CLK to Q2 1950
CLK to Q3 2275
CLK to Q4 2625
CLK to Q5 2950
CLK to Q6 3250
CLK to Q7 3575
1700
2025
2425
2750
3125
3450
3775
4075
1325
1000
2150
2500
2925
3350
3750
4150
4450
4800
1700
1300
1300
1600
1950
2275
2625
2950
3250
3575
950
1700
2050
2450
2775
3150
3475
3800
4125
1325
1000
2150
2500
2925
3350
3750
4150
4450
4800
1700
1300
1350
1650
2025
2350
2700
3050
3375
3700
950
1750
2100
2500
2850
3225
3550
3925
4250
1325
1000
2200
2550
3000
3425
3825
4250
4600
4950
1700
1300
A_Start to Q0
950
700
MR to Q0
700
700
t
t
t
Setup Time (EN1, EN2)
Hold Time (EN1, EN2)
Reset Recovery Time
0
−150
0
−150
0
−150
ps
ps
ps
s
300
150
300
150
300
150
h
RR
MR, A_Start
400
200
< 1
400
200
< 1
400
200
< 1
t
Minimum Pulse Width
ps
V
PW
CLK, MR, A_Start
400
400
400
V
Input Voltage Swing
(Differential Configuration) (Note 14)
CLK/CLK 0.25
1.0
0.25
1.0
0.25
1.0
PP
t
Random Clock Jitter (RMS)
ps
ps
JITTER
t
t
Rise/Fall Times (20%−80%)
r
f
Q0,Q1
Q2 to Q7
150
275
400
600
150
275
400
600
150
275
400
600
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
13.10 Series: V can vary −0.46 V / +0.06 V.
EE
100 Series: V can vary −0.46 V / +0.8 V.
EE
14.Minimum input swing for which AC parameters are guaranteed. Full DC ECL output swings will be generated with only 50 mV input swings.
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6
MC10E137, MC100E137
Z = 50 W
Q
Q
D
D
o
Receiver
Device
Driver
Device
Z = 50 W
o
50 W
50 W
V
TT
V
= V − 2.0 V
TT
CC
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
ORDERING INFORMATION
†
Device
Package
Shipping
MC10E137FN
PLCC−28
37 Units / Rail
37 Units / Rail
MC10E137FNG
PLCC−28
(Pb−Free)
MC10E137FNR2
PLCC−28
500 / Tape & Reel
500 / Tape & Reel
MC10E137FNR2G
PLCC−28
(Pb−Free)
MC100E137FN
PLCC−28
37 Units / Rail
37 Units / Rail
MC100E137FNG
PLCC−28
(Pb−Free)
MC100E137FNR2
MC100E137FNR2G
PLCC−28
500 / Tape & Reel
500 / Tape & Reel
PLCC−28
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
AN1672/D
AND8001/D
AND8002/D
AND8020/D
AND8066/D
AND8090/D
−
−
−
−
−
−
−
−
−
−
−
ECL Clock Distribution Techniques
Designing with PECL (ECL at +5.0 V)
ECLinPSt I/O SPiCE Modeling Kit
Metastability and the ECLinPS Family
Interfacing Between LVDS and ECL
The ECL Translator Guide
Odd Number Counters Design
Marking and Date Codes
Termination of ECL Logic Devices
Interfacing with ECLinPS
AC Characteristics of ECL Devices
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7
MC10E137, MC100E137
PACKAGE DIMENSIONS
PLCC−28
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776−02
ISSUE E
M
S
S
N
0.007 (0.180)
T L−M
B
Y BRK
D
−N−
M
S
S
N
0.007 (0.180)
T L−M
U
Z
−M−
−L−
W
D
S
S
S
N
0.010 (0.250)
T L−M
X
G1
V
28
1
VIEW D−D
M
S
S
S
A
0.007 (0.180)
0.007 (0.180)
T L−M
T L−M
N
M
S
S
N
0.007 (0.180)
T L−M
H
Z
M
S
N
R
K1
C
E
0.004 (0.100)
G
K
SEATING
PLANE
−T−
J
M
S
S
N
0.007 (0.180)
T L−M
F
VIEW S
G1
S
S
S
N
0.010 (0.250)
T L−M
VIEW S
NOTES:
INCHES
MILLIMETERS
1. DATUMS −L−, −M−, AND −N− DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM −T−, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE
MOLD FLASH. ALLOWABLE MOLD FLASH IS
0.010 (0.250) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
DIM MIN
MAX
0.495
0.495
0.180
0.110
0.019
MIN
12.32
12.32
4.20
MAX
12.57
12.57
4.57
A
B
C
E
F
0.485
0.485
0.165
0.090
0.013
2.29
0.33
2.79
0.48
G
H
J
0.050 BSC
1.27 BSC
0.026
0.020
0.025
0.450
0.450
0.042
0.042
0.042
0.032
−−−
−−−
0.66
0.51
0.64
11.43
11.43
1.07
1.07
1.07
−−−
0.81
−−−
K
R
U
V
W
X
Y
Z
−−−
0.456
0.456
0.048
0.048
0.056
11.58
11.58
1.21
1.21
1.42
0.50
10
−−− 0.020
10
2
2
_
_
_
_
G1 0.410
K1 0.040
0.430
−−−
10.42
1.02
10.92
−−−
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
http://onsemi.com
8
MC10E137, MC100E137
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
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Order Literature: http://www.onsemi.com/orderlit
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Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
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