MC100E141FNG [ONSEMI]
5V ECL 8-Bit Shift Register; 5V ECL 8位移位寄存器
| 型号： | MC100E141FNG |
| 厂家： | 
ONSEMI |
| 描述： | 5V ECL 8-Bit Shift Register |
| 文件： | 总8页 (文件大小：130K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC10E141, MC100E141
5VꢀECL 8-Bit Shift Register
Description
The MC10E/100E141 is an 8-bit full-function shift register. The
E141 performs serial/parallel in and serial/parallel out, shifting in
either direction. The eight inputs D − D accept parallel input data,
0
7
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while DL/DR accept serial input data for left/right shifting. The Qn
outputs do not need to be terminated for the shift operation to function.
To minimize noise and power, any Q output not used should be left
unterminated.
The select pins, SEL0 and SEL1, select one of four modes of
operation: Load, Hold, Shift Left, Shift Right, according to the
Function Table.
Input data is accepted a set-up time before the positive clock edge. A
HIGH on the Master Reset (MR) pin asynchronously resets all the
registers to zero.
PLCC−28
FN SUFFIX
CASE 776
The 100 Series contains temperature compensation.
Features
• 700 MHz Min. Shift Frequency
• 8-Bit
MARKING DIAGRAM*
• Full-Function, Bi-Directional
• Asynchronous Master Reset
• Pin-Compatible with E241
1
• PECL Mode Operating Range: V = 4.2 V to 5.7 V
MCxxxE141FNG
AWLYYWW
CC
with V = 0 V
EE
• NECL Mode Operating Range: V = 0 V
CC
with V = −4.2 V to −5.7 V
EE
• Internal Input 50 kW Pulldown Resistors
xxx
= 10 or 100
• ESD Protection: Human Body Model; > 2 kV,
Machine Model; > 200 V
• Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test
A
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
WL
YY
WW
G
• Moisture Sensitivity Level:
Pb = 1
Pb−Free = 3
*For additional marking information, refer to
Application Note AND8002/D.
For Additional Information, see Application Note AND8003/D
• Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
• Transistor Count = 565 devices
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
• Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
November, 2006 − Rev. 7
MC10E141/D
MC10E141, MC100E141
Table 1. PIN DESCRIPTION
SEL0 DL
25 24
D
D
D
V
Q
7
7
6
5
CCO
PIN
D − D
DL, DR
SEL0, SEL1
CLK
FUNCTION
23
22
21
20
19
SEL1
CLK
MR
Q
Q
26
18
17
16
15
14
13
6
ECL Parallel Data Inputs
ECL Serial Data Inputs
ECL Mode Select In Inputs
ECL Clock
0
7
27
28
1
5
V
CC
Q
MR
− Q
ECL Data Outputs
ECL Master Reset
Positive Supply*
0
7
Pinout: 28-Lead
PLCC (Top View)
V
NC
EE
V
V
, V
CCO
CC
Negative Supply
EE
DR
2
3
4
NC
No Connect
V
CCO
*From V pin to each V
pin is an internal 100 W
CC
CCO
D
0
Q
Q
4
3
resistor.
D
1
12
Table 2. FUNCTION TABLE
5
6
7
8
9
10
11
SEL0
SEL1
FUNCTION
D
D
D
V
Q
Q
Q
2
2
3
4
CCO
0
1
L
H
L
Load
Shift Right (D to D
Shift Left (D to D
Hold
L
L
H
H
* All V and V
pins are tied together on the die.
CCO
CC
)
n
n + 1
)
n
n − 1
Warning: All V , V
connected to Power Supply to guarantee proper operation.
, and V pins must be externally
EE
CC
CCO
H
Figure 1. 28-Lead Pinout
DL
BITS 1 − 6
Q
R
D
Q
R
Q
D
D
DR
R
D
7
D
Q
Q
Q
0
7
D
0
SEL1
SEL0
CLK
MR
Figure 2. Logic Diagram
Table 3. EXPANDED FUNCTION TABLE
Function
Load
DL
DR
SEL0 SEL1
MR
CLK
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
X
X
L
L
L
Z
D0
D1
D2
D3
D4
D5
D6
D7
Shift Right
X
X
L
H
L
L
H
H
L
L
Z
Z
L
H
Q0
L
Q1
Q0
Q2
Q1
Q3
Q2
Q4
Q3
Q5
Q4
Q6
Q5
Shift Left
L
H
X
X
H
H
L
L
L
L
Z
Z
L
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q5
Q5
L
L
H
Hold
X
X
X
X
H
H
H
H
L
L
Z
Z
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q5
Q5
L
L
H
H
Reset
X
X
X
X
H
X
L
L
L
L
L
L
L
L
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2
MC10E141, MC100E141
Table 4. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
= 0 V
Condition 2
Rating
Unit
V
V
V
V
PECL Mode Power Supply
NECL Mode Power Supply
V
V
8
CC
EE
I
EE
CC
= 0 V
−8
V
PECL Mode Input Voltage
NECL Mode Input Voltage
V
V
= 0 V
= 0 V
V v V
6
−6
V
V
EE
CC
I
CC
V w V
I
EE
I
Output Current
Continuous
Surge
50
100
mA
mA
out
T
Operating Temperature Range
0 to +85
°C
°C
A
T
Storage Temperature Range
−65 to +150
stg
JA
q
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
PLCC−28
PLCC−28
63.5
43.5
°C/W
°C/W
q
Thermal Resistance (Junction−to−Case)
Standard Board
PLCC−28
22 to 26
°C/W
JC
V
PECL Operating Range
NECL Operating Range
4.2 to 5.7
−5.7 to −4.2
V
V
EE
T
sol
Wave Solder
Pb
Pb−Free
265
265
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 5. 10E SERIES PECL DC CHARACTERISTICS V
= 5.0 V; V = 0.0 V (Note 1)
EE
CCx
0°C
Typ
25°C
Typ
85°C
Typ
Min
Max
181
Min
Max
181
Min
Max
181
Symbol
Characteristic
Power Supply Current
Unit
mA
mV
mV
mV
mV
mA
I
131
131
131
EE
V
Output HIGH Voltage (Note 2)
Output LOW Voltage (Note 2)
Input HIGH Voltage
3980
3050
3830
3050
4070
3210
3995
3285
4160
3370
4160
3520
150
4020
3050
3870
3050
4105
3210
4030
3285
4190
3370
4190
3520
150
4090
3050
3940
3050
4185
3227
4110
3302
4280
3405
4280
3555
150
OH
OL
IH
V
V
V
Input LOW Voltage
IL
I
I
Input HIGH Current
IH
IL
Input LOW Current
0.5
0.3
0.5
0.25
0.3
0.2
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with V . V can vary −0.46 V / +0.06 V.
CC
EE
2. Outputs are terminated through a 50 W resistor to V − 2.0 V.
CC
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3
MC10E141, MC100E141
Table 6. 10E SERIES NECL DC CHARACTERISTICS V
= 0.0 V; V = −5.0 V (Note 3)
EE
CCx
0°C
Typ
131
−1020 −930
25°C
Typ
85°C
Typ
Min
Max
181
Min
Max
181
Min
Max
181
Symbol
Characteristic
Power Supply Current
Unit
mA
mV
mV
mV
mV
mA
I
131
131
EE
V
Output HIGH Voltage (Note 4)
Output LOW Voltage (Note 4)
Input HIGH Voltage
−840
−980
−895
−810
−910
−815
−720
OH
OL
IH
V
V
V
−1950 −1790 −1630 −1950 −1790 −1630 −1950 −1773 −1595
−1170 −1005 −840 −1130 −970 −810 −1060 −890 −720
−1950 −1715 −1480 −1950 −1715 −1480 −1950 −1698 −1445
150 150 150
Input LOW Voltage
IL
I
I
Input HIGH Current
IH
IL
Input LOW Current
0.5
0.3
0.5
0.065
0.3
0.2
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Input and output parameters vary 1:1 with V . V can vary −0.46 V / +0.06 V.
CC
EE
4. Outputs are terminated through a 50 W resistor to V − 2.0 V.
CC
Table 7. 100E SERIES PECL DC CHARACTERISTICS V
= 5.0 V; V = 0.0 V (Note 5)
CCx
EE
0°C
Typ
25°C
85°C
Typ
Min
Max
181
Min
Typ
131
Max
181
Min
Max
181
Symbol
Characteristic
Power Supply Current
Unit
mA
mV
mV
mV
mV
mA
I
131
151
EE
V
Output HIGH Voltage (Note 6)
Output LOW Voltage (Note 6)
Input HIGH Voltage
3975
3190
3835
3190
4050
3295
3975
3355
4120
3380
4120
3525
150
3975
3190
3835
3190
4050
3255
3975
3355
4120
3380
4120
3525
150
3975
3190
3835
3190
4050
3260
3975
3355
4120
3380
4120
3525
150
OH
OL
IH
V
V
V
Input LOW Voltage
IL
I
I
Input HIGH Current
IH
IL
Input LOW Current
0.5
0.3
0.5
0.25
0.5
0.2
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and output parameters vary 1:1 with V . V can vary −0.46 V / +0.8 V.
CC
EE
6. Outputs are terminated through a 50 W resistor to V − 2.0 V.
CC
Table 8. 100E SERIES NECL DC CHARACTERISTICS V
= 0.0 V; V = −5.0 V (Note 7)
CCx
EE
0°C
Typ
131
−1025 −950
25°C
85°C
Typ
151
Min
Max
Min
Typ
Max
Min
Max
181
Symbol
Characteristic
Power Supply Current
Unit
mA
mV
mV
mV
mV
mA
I
181
131
181
EE
V
Output HIGH Voltage (Note 8)
Output LOW Voltage (Note 8)
Input HIGH Voltage
−880 −1025 −950
−880 −1025 −950
−880
OH
OL
IH
V
V
V
−1810 −1705 −1620 −1810 −1745 −1620 −1810 −1740 −1620
−1165 −1025 −880 −1165 −1025 −880 −1165 −880 −1025
−1810 −1645 −1475 −1810 −1645 −1475 −1810 −1475 −1645
Input LOW Voltage
IL
I
I
Input HIGH Current
150
150
150
IH
IL
Input LOW Current
0.5
0.3
0.5
0.25
0.5
0.2
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
7. Input and output parameters vary 1:1 with V . V can vary −0.46 V / +0.8 V.
CC
EE
8. Outputs are terminated through a 50 W resistor to V − 2.0 V.
CC
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4
MC10E141, MC100E141
Table 9. AC CHARACTERISTICS V
= 5.0 V; V = 0.0 V or V
= 0.0 V; V = −5.0 V (Note 9)
CCx EE
CCx
EE
0°C
25°C
Typ
900
85°C
Typ
900
Min
Typ
Max
Min
Max
Min
Max
Symbol
Characteristic
Max. Shift Frequency
Unit
MHz
ps
f
700
900
700
700
SHIFT
t
t
Propagation Delay To Output
PLH
PHL
Clk
MR
625
600
750
725
975
975
625
600
750
725
975
975
625
600
750
725
975
975
t
t
Setup Time
ps
ps
s
D
SEL0
SEL1
175
350
300
25
200
150
175
350
300
25
200
150
175
350
300
25
200
150
Hold Time
h
D
SEL0
SEL1
200
100
100
− 25
− 200
−150
200
100
100
− 25
− 200
−150
200
100
100
− 25
− 200
−150
t
t
Reset Recovery Time
Minimum Pulse Width
900
700
900
700
900
700
ps
ps
RR
PW
Clk, MR
400
400
400
t
t
Within-Device Skew (Note 10)
Random Clock Jitter (RMS)
60
60
60
ps
ps
ps
SKEW
< 1
< 1
< 1
JITTER
t
t
Rise/Fall Times
(20 - 80%)
r
f
300
525
800
300
525
800
300
525
800
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
9. 10 Series: V can vary −0.46 V / +0.06 V.
EE
100 Series: V can vary −0.46 V / +0.8 V.
EE
10.Within-device skew is defined as identical transitions on similar paths through a device.
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5
MC10E141, MC100E141
Z = 50 W
Q
Q
D
D
o
Receiver
Device
Driver
Device
Z = 50 W
o
50 W
50 W
V
TT
V
= V − 2.0 V
TT
CC
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
ORDERING INFORMATION
†
Device
Package
Shipping
MC10E141FN
PLCC−28
37 Units / Rail
37 Units / Rail
MC10E141FNG
PLCC−28
(Pb−Free)
MC10E141FNR2
PLCC−28
500 / Tape & Reel
500 / Tape & Reel
MC10E141FNR2G
PLCC−28
(Pb−Free)
MC100E141FN
PLCC−28
37 Units / Rail
37 Units / Rail
MC100E141FNG
PLCC−28
(Pb−Free)
MC100E141FNR2
MC100E141FNR2G
PLCC−28
500 / Tape & Reel
500 / Tape & Reel
PLCC−28
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
AN1672/D
AND8001/D
AND8002/D
AND8020/D
AND8066/D
AND8090/D
−
−
−
−
−
−
−
−
−
−
−
ECL Clock Distribution Techniques
Designing with PECL (ECL at +5.0 V)
ECLinPSt I/O SPiCE Modeling Kit
Metastability and the ECLinPS Family
Interfacing Between LVDS and ECL
The ECL Translator Guide
Odd Number Counters Design
Marking and Date Codes
Termination of ECL Logic Devices
Interfacing with ECLinPS
AC Characteristics of ECL Devices
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6
MC10E141, MC100E141
PACKAGE DIMENSIONS
PLCC−28
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776−02
ISSUE E
M
S
S
N
0.007 (0.180)
T L−M
B
Y BRK
D
−N−
M
S
S
N
0.007 (0.180)
T L−M
U
Z
−M−
−L−
W
D
S
S
S
N
0.010 (0.250)
T L−M
X
G1
V
28
1
VIEW D−D
M
S
S
S
A
0.007 (0.180)
0.007 (0.180)
T L−M
T L−M
N
M
S
S
N
0.007 (0.180)
T L−M
H
Z
M
S
N
R
K1
C
E
0.004 (0.100)
G
K
SEATING
PLANE
−T−
J
M
S
S
N
0.007 (0.180)
T L−M
F
VIEW S
G1
S
S
S
N
0.010 (0.250)
T L−M
VIEW S
NOTES:
INCHES
MILLIMETERS
1. DATUMS −L−, −M−, AND −N− DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM −T−, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE
MOLD FLASH. ALLOWABLE MOLD FLASH IS
0.010 (0.250) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
DIM MIN
MAX
0.495
0.495
0.180
0.110
0.019
MIN
12.32
12.32
4.20
MAX
12.57
12.57
4.57
A
B
C
E
F
0.485
0.485
0.165
0.090
0.013
2.29
0.33
2.79
0.48
G
H
J
0.050 BSC
1.27 BSC
0.026
0.020
0.025
0.450
0.450
0.042
0.042
0.042
0.032
−−−
−−−
0.66
0.51
0.64
11.43
11.43
1.07
1.07
1.07
−−−
0.81
−−−
K
R
U
V
W
X
Y
Z
−−−
0.456
0.456
0.048
0.048
0.056
11.58
11.58
1.21
1.21
1.42
0.50
10
−−− 0.020
10
2
2
_
_
_
_
G1 0.410
K1 0.040
0.430
−−−
10.42
1.02
10.92
−−−
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
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7
MC10E141, MC100E141
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
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Phone: 81−3−5773−3850
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Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
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For additional information, please contact your local
Sales Representative
MC10E141/D
相关型号：
MC100E142FNR2
100E SERIES, 9-BIT RIGHT PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PQCC28, PLASTIC, LCC-28
MOTOROLA
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