MC100E221FN [ONSEMI]
100E SERIES, LOW SKEW CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC28, PLASTIC, LCC-28;
| 型号： | MC100E221FN |
| 厂家： | 
ONSEMI |
| 描述： | 100E SERIES, LOW SKEW CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC28, PLASTIC, LCC-28 驱动 输出元件 |
| 文件： | 总10页 (文件大小：106K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC10E211, MC100E211
5VꢀECL 1:6 Differential
Clock Distribution Chip
The MC10E/100E211 is a low skew 1:6 fanout device designed
explicitly for low skew clock distribution applications.
The E211 features a multiplexed clock input to allow for the
distribution of a lower speed scan or test clock along with the high speed
system clock. When LOW (or left open in which case it will be pulled
LOW by the input pulldown resistor) the SEL pin will select the
differential clock input.
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MARKING
DIAGRAMS
Both a common enable and individual output enables are provided.
When asserted the positive output will go LOW on the next negative
transition of the CLK (or SCLK) input. The enabling function is
synchronous so that the outputs will only be enabled/disabled when the
outputs are already in the LOW state. In this way the problem of runt
pulse generation during the disable operation is avoided. Note that the
internal flip flop is clocked on the falling edge of the input clock edge,
therefore all associated specifications are referenced to the negative
edge of the CLK input.
128
MC10E211FN
AWLYYWW
PLCC−28
FN SUFFIX
CASE 776
128
The output transitions of the E211 are faster than the standard
ECLinPS edge rates. This feature provides a means of distributing
higher frequency signals than capable with the E111 device. Because of
these edge rates and the tight skew limits guaranteed in the
specification, there are certain termination guidelines which must be
followed. For more details on the recommended termination schemes
please refer to the applications information section of this data sheet.
MC100E211FN
AWLYYWW
A
= Assembly Location
The V
pin, an internally generated voltage supply, is available to
BB
WL
YY
WW
= Wafer Lot
= Year
= Work Week
this device only. For single−ended input conditions, the unused
differential input is connected to V as a switching reference voltage.
BB
V
V
may also rebias AC coupled inputs. When used, decouple V and
BB
CC
BB
via a 0.01 mF capacitor and limit current sourcing or sinking to
should be left open.
0.5 mA. When not used, V
BB
ORDERING INFORMATION
See detailed ordering and shipping information in the package
The 100 Series contains temperature compensation.
dimensions section on page 511 of this data sheet.
• Guaranteed Low Skew Specification
• Synchronous Enabling/Disabling
• Multiplexed Clock Inputs
• V Output for Single−Ended Use
BB
• Common and Individual Enable/Disable Control
• High Bandwidth Output Transistors
• PECL Mode Operating Range: V
= 4.2 V to 5.7 V with V = 0 V
CC
EE
• NECL Mode Operating Range: V = 0 V with V = −4.2 V to −5.7 V
CC
EE
• Internal Input 75 kW Pulldown Resistors
• ESD Protection: Human Body Model; > 2 kV,
Machine Model; > 100 V
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
• Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
• Transistor Count = 457 devices
Semiconductor Components Industries, LLC, 2004
503
Publication Order Number:
March, 2004 − Rev. 8
MC10E211/D
MC10E211, MC100E211
EN4 EN5 V
Q5 Q5 Q4 Q4
CC0
Table 1. PIN DESCRIPTION
PIN
24
25
22
23
21
19
20
FUNCTION
18
17
16
15
14
13
12
EN3
SEL
Q3
Q3
V
26
27
EN0−EN5
SEL
SCLK
CLK, CLK
CEN
Q0−Q5, Q0−Q5
ECL Enable
ECL Select (Clock)
ECL Single Clock
ECL Differential Clock
ECL Common Enable
ECL Differential Outputs
Reference Voltage Output
Positive Supply
SCLK
28
1
CC
V
V
V
BB
CC CCO
EE
V
EE
Q2
, V
Negative Supply
CLK
CLK
2
3
4
Q2
Q1
Q1
NC
No Connect
V
BB
5
6
7
8
9
10
11
CEN EN2 EN1 EN0 V
Q0 Q0
CC0
*All V
CC
and V
pins are tied together on the die.
CCO
Warning: All V , V
CC CCO
, and V pins must be externally con-
EE
nected to Power Supply to guarantee proper operation.
Figure 10. Pinout: PLCC−28 (Top View)
Q0
Q0
Table 2. FUNCTION TABLE
CLK
SCLK
SEL
ENx
Q
EN0
H/L
X
Z*
X
H/L
Z*
L
H
X
L
L
H
CLK
SCLK
L
DQ
*Z = Negative transition of CLK or SCLK
BITS 1−4
CLK
CLK
0
1
Q1−4
Q1−4
SCLK
SEL
DQ
EN1−4
CEN
Q5
Q5
EN5
DQ
V
BB
Figure 11. Logic Diagram
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504
MC10E211, MC100E211
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
V
V
CC
V
EE
V
I
PECL Mode Power Supply
NECL Mode Power Supply
V
V
= 0 V
= 0 V
8
EE
−8
V
CC
PECL Mode Input Voltage
NECL Mode Input Voltage
V
V
= 0 V
= 0 V
V ꢀ V
6
V
V
EE
CC
I
CC
EE
V ꢁ V
−6
I
I
Output Current
Continuous
Surge
50
mA
mA
out
100
I
V
Sink/Source
± 0.5
mA
°C
BB
BB
T
Operating Temperature Range
Storage Temperature Range
0 to +85
A
T
−65 to +150
°C
stg
q
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
PLCC−28
PLCC−28
63.5
43.5
°C/W
°C/W
JA
q
Thermal Resistance (Junction−to−Case)
Standard Board
PLCC−28
22 to 26
°C/W
JC
V
EE
PECL Operating Range
NECL Operating Range
4.2 to 5.7
V
V
−5.7 to −4.2
T
sol
Wave Solder
<2 to 3 sec @ 248°C
265
°C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
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505
MC10E211, MC100E211
Table 4. 10E SERIES PECL DC CHARACTERISTICS V
= 5.0 V; V
= 0.0 V (Note 2)
CCx
EE
0°C
25°C
85°C
Typ
Symbol
Characteristic
Power Supply Current
Min
Typ
119
Max
160
Min
Typ
119
Max
160
Min
Max
160
Unit
mA
mV
mV
mV
mV
V
I
119
EE
V
V
V
V
V
V
Output HIGH Voltage (Note 3)
Output LOW Voltage (Note 3)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
3980
3050
3830
3050
3.62
2.4
4070
3210
3995
3285
4160
3370
4160
3520
3.74
4.6
4020
3050
3870
3050
3.65
2.4
4105
3210
4030
3285
4190
3370
4190
3520
3.75
4.6
4090
3050
3940
3050
3.69
2.4
4185
3227
4110
3302
4280
3405
4280
3555
3.81
4.6
OH
OL
IH
IL
BB
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 4)
V
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
0.5
0.3
0.5
0.25
0.3
0.2
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
2. Input and output parameters vary 1:1 with V . V
CC EE
can vary −0.46 V / +0.06 V.
− 2.0 V.
3. Outputs are terminated through a 50 W resistor to V
CC
4. V
min varies 1:1 with V , max varies 1:1 with V .
IHCMR
EE CC
Table 5. 10E SERIES NECL DC CHARACTERISTICS V
= 0.0 V; V = −5.0 V (Note 5)
E E
CCx
0°C
25°C
85°C
Typ
Symbol
Characteristic
Power Supply Current
Min
Typ
Max
160
Min
Typ
119
Max
Min
Max
160
Unit
mA
mV
mV
mV
mV
V
I
119
160
119
EE
V
V
V
V
V
V
Output HIGH Voltage (Note 6)
Output LOW Voltage (Note 6)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
−1020 −930
−840
−980
−895
−810
−910
−815
−720
OH
−1950 −1790 −1630 −1950 −1790 −1630 −1950 −1773 −1595
−1170 −1005 −840 −1130 −970 −810 −1060 −890 −720
−1950 −1715 −1480 −1950 −1715 −1480 −1950 −1698 −1445
OL
IH
IL
−1.38
−2.6
−1.27 −1.35
−1.25 −1.31
−1.19
−0.4
BB
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 7)
−0.4
150
−2.6
−0.4
150
−2.6
V
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
mA
mA
IH
0.5
0.3
0.5
0.065
0.3
0.2
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and output parameters vary 1:1 with V . V
6. Outputs are terminated through a 50 W resistor to V
can vary −0.46 V / +0.06 V.
− 2.0 V.
CC EE
CC
7. V
min varies 1:1 with V , max varies 1:1 with V .
IHCMR
EE CC
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506
MC10E211, MC100E211
Table 6. 100E SERIES PECL DC CHARACTERISTICS V
CCx
= 5.0 V; V = 0.0 V (Note 8)
EE
0°C
25°C
Typ
85°C
Typ
Symbol
Characteristic
Power Supply Current
Min
Typ
119
Max
160
Min
Max
160
Min
Max
164
Unit
mA
mV
mV
mV
mV
V
I
119
137
EE
V
V
V
V
V
V
Output HIGH Voltage (Note 9)
Output LOW Voltage (Note 9)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
3975
3190
3835
3190
3.62
2.4
4050
3295
3975
3355
4120
3380
4120
3525
3.74
4.6
3975
3190
3835
3190
3.62
2.4
4050
3255
3975
3355
4120
3380
4120
3525
3.74
4.6
3975
3190
3835
3190
3.62
2.4
4050
3260
3975
3355
4120
3380
4120
3525
3.74
4.6
OH
OL
IH
IL
BB
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 10)
V
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
0.5
0.3
0.5
0.25
0.5
0.2
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
8. Input and output parameters vary 1:1 with V . V
CC EE
can vary −0.46 V / +0.8 V.
− 2.0 V.
9. Outputs are terminated through a 50 W resistor to V
CC
10.V
min varies 1:1 with V , max varies 1:1 with V .
IHCMR
EE CC
Table 7. 100E SERIES NECL DC CHARACTERISTICS V
CCx
= 0.0 V; V = −5.0 V (Note 11)
EE
0°C
25°C
85°C
Typ
137
Symbol
Characteristic
Power Supply Current
Min
Typ
Max
Min
Typ
Max
Min
Max
164
Unit
mA
mV
mV
mV
mV
V
I
119
160
119
160
EE
V
V
V
V
V
V
Output HIGH Voltage (Note 12)
Output LOW Voltage (Note 12)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
−1025 −950
−880 −1025 −950
−880 −1025 −950
−880
OH
−1810 −1705 −1620 −1810 −1745 −1620 −1810 −1740 −1620
−1165 −1025 −880 −1165 −1025 −880 −1165 −1025 −880
−1810 −1645 −1475 −1810 −1645 −1475 −1810 −1645 −1475
OL
IH
IL
−1.38
−2.6
−1.26 −1.38
−1.26 −1.38
−1.26
−0.4
BB
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 13)
−0.4
150
−2.6
−0.4
150
−2.6
V
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
mA
mA
IH
0.5
0.3
0.5
0.25
0.5
0.2
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
11. Input and output parameters vary 1:1 with V . V
12.Outputs are terminated through a 50 W resistor to V
can vary −0.46 V / +0.8 V.
− 2.0 V.
CC EE
CC
13.V
min varies 1:1 with V , max varies 1:1 with V .
IHCMR
EE CC
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507
MC10E211, MC100E211
Table 8. AC CHARACTERISTICS V
CCx
= 5.0 V; V = 0.0 V or V
EE
= 0.0 V; V = −5.0 V (Note 14)
EE
CCx
0°C
25°C
85°C
Typ
700
Symbol
Characteristic
Maximum Toggle Frequency
Propagation Delay to Output
Min
Typ
Max
Min
Typ
Max
Min
Max
Unit
MHz
ps
f
700
700
MAX
t
t
PLH
PHL
795
745
650
745
930
930
900
970
1065
1115
1085
1195
805
755
650
755
940
940
910
980
1075
1125
1095
1205
825
775
650
775
960
960
930
1095
1145
1115
1225
CLK to Q (Diff)
CLK to Q (SE)
SCLK to Q
1000
SEL to Q
t
t
Disable Time
CLK or SCLK to Q (Note 16)
ps
ps
PHL
600
800
600
800
600
< 1
800
Part−to−Part Skew
skew
270
370
75
270
370
75
270
370
75
CLK (Diff) to Q
CLK (SE), SCLK to Q
Within−Device Skew (Note 15)
50
50
t
t
Random Clock Jitter (RMS)
< 1
< 1
ps
ps
JITTER
Setup Time
s
200
200
−100
0
200
200
−100
0
200
200
−100
0
ENx to CLK
CEN to CLK (Note 16)
t
h
Hold Time
ps
900
600
900
160
900
600
CLK to ENx, CEN (Note 16)
V
PP
Minimum Input Swing (CLK) (Note 17)
0.25
1.0
0.25
1.0
0.25
1.0
V
t
r
t
f
Rise/Fall Times
(20 − 80%)
ps
150
400
150
400
150
400
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
14.10 Series: V
can vary −0.46 V / +0.06 V.
EE
100 Series: V
can vary −0.46 V / +0.8 V.
EE
15.Within−Device skew is defined for identical transitions on similar paths through a device.
16.Setup, Hold and Disable times are all relative to a falling edge on CLK or SCLK.
17.Minimum input swing for which AC parameters are guaranteed. Full DC ECL output swings will be generated with only 50 mV input swings.
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508
MC10E211, MC100E211
APPLICATIONS INFORMATION
General Description
situations between cards there will be no AC performance or
noise margin loss for the differential CLK inputs.
The MC10E/100E211 is a 1:6 fanout tree designed
explicitly for low skew high speed clock distribution. The
device was targeted to work in conjunction with the E111
device to provide another level of flexibility in the design
and implementation of clock distribution trees. The
individual synchronous enable controls and multiplexed
clock inputs make the device ideal as the first level
distribution unit in a distribution tree. The device provides
the ability to distribute a lower speed scan or test clock along
with the high speed system clock to ease the design of system
diagnostics and self test procedures. The individual enables
could be used to allow for the disabling of individual cards
on a backplane in fault tolerant designs.
For situations where TTL clocks are required the E211 can
be interfaced with the H641 or H643 ECL to TTL Clock
Distribution Chips. The H641 is a single supply 1:9 PECL
to TTL device while the H643 is a 1:8 dual supply standard
ECL to TTL device. By combining the superior skew
performance of the E211, or E111, with the low skew
translating capabilities of the H641 and H643 very low skew
TTL clock distribution networks can be realized.
Handling Open Inputs and Outputs
All of the input pins of the E211 have a 50 kW to 75 kW
pulldown resistor to pull the input to V when left open.
EE
This feature can cause a problem if the differential clock
inputs are left open as the input gate current source transistor
will become saturated. Under these conditions the outputs of
the CLK input buffer will go to an undefined state. It is
recommended, if possible,that the SCLK input should be
selected any time the differential CLK inputs are allowed to
float. The SCLK buffer, under open input conditions, will
maintain a defined output state and thus the Q outputs of the
device will be in a defined state (Q = LOW). Note that if all
of the inputs are left open the differential CLK input will be
selected and the state of the Q outputs will be undefined.
With the simultaneous switching characteristics and the
tight skew specifications of the E211 the handling of the
unused outputs becomes critical. To minimize the noise
generated on the die all outputs should be terminated in
pairs, i.e. both the true and compliment outputs should be
terminated even if only one of the outputs will be used in the
system. With both complimentary pairs terminated the
Because of lower fanout and larger skews the E211 will
not likely be used as an alternative to the E111 for the bulk
of the clock fanout generation. Figure 12 shows a typical
application combining the two devices to take advantage of
the strengths of each.
E111
Q0
E211
Q0
Q8
E111
Q0
Q5
current in the V
thus inductance induced voltage glitches on V
CC
occur. V
CC
pins will remain essentially constant and
will not
glitches will result in distorted output
CC
Q8
waveforms and degradations in the skew performance of the
device.
Figure 12. Standard E211 Application
The package parasitics of the PLCC−28 cause the signals
on a given pin to be influenced by signals on adjacent pins.
The E211 is characterized and tested with all of the outputs
switching, therefore the numbers in the data book are
guaranteed only for this situation. If all of the outputs of the
E211 are not needed and there is a desire to save power the
unused output pairs can be left unterminated. Unterminated
outputs can influence the propagation delay on adjacent pins
by 15 ps − 20 ps. Therefore under these conditions this 15 ps
− 20 ps needs to be added to the overall skew of the device.
Pins which are separated by a package corner are not
considered adjacent pins in the context of propagation delay
influence. Therefore as long as all of the outputs on a single
side of the package are terminated the specification limits in
the data sheet will apply.
Using the E211 in PECL Designs
The E211 device can be utilized very effectively in
designs utilizing only a +5 V power supply. Since the
internal switching reference levels are biased off of the V
supply the input thresholds for the single−ended inputs will
CC
vary with V . As a result the single−ended inputs should be
CC
driven by a device on the same board as the E211. Driving
these inputs across
a backplane where significant
differences between the V ’s of the transmitter and
CC
receiver can occur can lead to AC performance and/or
significant noise margin degradations. Because the
differential I/O does not use a switching reference, and due
to the CMR range of the E211, even under worst case V
CC
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509
MC10E211, MC100E211
APPLICATIONS INFORMATION
Differential versus Single−Ended Use
IN
As can be seen from the data sheet, to minimize the skew
of the E211 the device must be used in the differential mode.
In the single−ended mode the propagation delays are
0.001mF
50 W
IN
dependent on the relative position of the V
switching
BB
reference. Any V offset from the center of the input swing
BB
will add delay to either the T
or T
and subtract delay
PLH
PHL
from the other. This increase and decrease in delay will lead
to an increase in the duty cycle skew and thus part−to−part
skew. The within−device skew will be independent of the
0.01mF
V
and therefore will be the same regardless of whether the
BB
device is driven differentially or single−ended.
For applications where part−to−part skew or duty cycle
skew are not important the advantages of single−ended
clock distribution may lead to its use. Using single−ended
interconnect will reduce the number of signal traces to be
routed, but remember that all of the complimentary outputs
still need to be terminated therefore there will be no
reduction in the termination components required. To use
the E211 with a single−ended input the arrangement pictured
in Figure 14 should be used. If the input to the differential
CLK inputs are AC coupled as pictured in Figure 13 the
V
BB
Figure 13. AC Coupled Input
IN
dependence on a centered V
reference is removed. The
situation pictured will ensure that the input is centered
BB
IN
around the bias set by the V . As a result when AC coupled
BB
the AC specification limits for a differential input can be
used. For more information on AC coupling please refer to
the interfacing section of the design guide in the ECLinPS
data book.
0.01 mF
Using the Enable Pins
Both the common enable (CEN) and the individual
enables (ENx) are synchronous to the CLK or SCLK input
depending on which is selected. The active low signals are
clocked into the enable flip flops on the negative edges of the
E211 clock inputs. In this way the devices will only be
disabled when the outputs are already in the LOW state. The
internal propagation delays are such that the delay to the
output through the distribution buffers is less than that
through the enable flip flops. This will ensure that the
disabling of the device will not slice any time off the clock
pulse. On initial power up the enable flip flops will randomly
attain a stable state, therefore precautions should be taken on
initial power up to ensure the E211 is in the desired state.
V
BB
Figure 14. Single−Ended Input
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510
MC10E211, MC100E211
Z
= 50 W
= 50 W
Q
Q
D
D
o
o
Receiver
Device
Driver
Device
Z
50 W
50 W
V
TT
V
TT
= V
CC
− 2.0 V
Figure 15. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
ORDERING INFORMATION
†
Shipping
Device
MC10E221FN
Package
PLCC−28
PLCC−28
PLCC−28
PLCC−28
37 Units / Rail
500 / Tape & Reel
37 Units / Rail
MC10E221FNR2
MC100E221FN
MC100E221FNR2
500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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511
MC10E211, MC100E211
Resource Reference of Application Notes
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
AN1642/D
AND8001/D
AND8002/D
AND8020/D
AND8066/D
AND8090/D
−
−
−
−
−
−
−
−
−
−
−
ECL Clock Distribution Techniques
Designing with PECL (ECL at +5.0 V)
ECLinPSG I/O SPiCE Modeling Kit
Metastability and the ECLinPS Family
Interfacing Between LVDS and ECL
The ECL Translator Guide
Odd Number Counters Design
Marking and Date Codes
Termination of ECL Logic Devices
Interfacing with ECLinPS
AC Characteristics of ECL Devices
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512
相关型号：
MC100E256FNR2
100E SERIES, LOW LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, PQCC28, PLASTIC, LCC-28
MOTOROLA
MC100E256FNR2
100E SERIES, LOW LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, PQCC28, PLASTIC, LCC-28
ONSEMI
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