MC100E310FNR2 [ONSEMI]
5V ECL Low Voltage 2:8 Differential Fanout Buffer; 5V ECL低电压2 ： 8差分扇出缓冲器
| 型号： | MC100E310FNR2 |
| 厂家： | 
ONSEMI |
| 描述： | 5V ECL Low Voltage 2:8 Differential Fanout Buffer |
| 文件： | 总8页 (文件大小：134K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC100E310
5VꢀECL Low Voltage 2:8
Differential Fanout Buffer
Description
The MC100E310 is a low voltage, low skew 2:8 differential ECL
fanout buffer designed with clock distribution in mind. The device
features fully differential clock paths to minimize both device and
system skew. The E310 offers two selectable clock inputs to allow for
redundant or test clocks to be incorporated into the system clock trees.
The lowest TPD delay time results from terminating only one output
pair, and the greatest TPD delay time results from terminating all the
output pairs. This shift is about 10−20 pS in TPD. The skew between
any two output pairs within a device is typically about 25 nS. If other
output pairs are not terminated, the lowest TPD delay time results
from both output pairs and the skew is typically 25 nS. When all
outputs are terminated, the greatest TPD (delay time) occurs and all
outputs display about the same 10 − 20 ps increase in TPD, so the
relative skew between any two output pairs remains about 25 ns.
For more information on using PECL, designers should refer to
ON Semiconductor Application Note AN1406/D.
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PLCC−28
FN SUFFIX
CASE 776
MARKING DIAGRAM*
1 28
MC100E310FNG
AWLYYWW
The V pin, an internally generated voltage supply, is available to
BB
this device only. For single-ended input conditions, the unused
A
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
differential input is connected to V as a switching reference voltage.
BB
WL
YY
WW
G
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V via a 0.01 mF capacitor and limit current sourcing or sinking
CC
to 0.5 mA. When not used, V should be left open.
BB
The 100 Series Contains Temperature Compensation
*For additional marking information, refer to
Application Note AND8002/D.
Features
• Dual Differential Fanout Buffers
• 200 ps Part−to−Part Skew
• 50 ps Output−to−Output Skew
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
• 28−lead PLCC Packaging
• Q Output will Default LOW with Inputs Open or at V
EE
• PECL Mode Operating Range: V = 4.2 V to 5.7 V
• Moisture Sensitivity Level: Pb = 1; Pb−Free = 3
For Additional Information, see Application Note
AND8003/D
• Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
• Transistor Count = 212 devices
• Pb−Free Packages are Available*
CC
with V = 0 V
EE
• NECL Mode Operating Range: V = 0 V
CC
with V = −4.2 V to −5.7 V
EE
• Internal Input 50 kW Pulldown Resistors
• ESD Protection: Human Body Model; >2 kV,
Machine Model; >200 V
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC
Latchup Test
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
October, 2006 − Rev. 5
MC100E310/D
MC100E310
Q0
Q0
Q0 Q0 Q1 V
Q1 Q2 Q2
CCO
25 24
23 22 21
20
19
Q1
Q1
V
Q3
Q3
26
27
28
18
17
16
15
14
13
12
EE
Q2
Q2
CLK_SEL
CLKa
Q4
V
CLKa
CLKa
Q3
Q3
Pinout: 28−Lead PLCC
V
CC
1
2
CCO
(Top View)
CLKb
CLKb
Q4
Q4
CLKa
Q4
Q5
Q5
3
4
V
BB
Q5
Q5
CLK_SEL
CLKb
Q6
Q6
5
6
7
8
9
10
11
CLKb NC Q7 V
Q7 Q6 Q6
CCO
Q7
Q7
* All V and V
pins are tied together on the die.
CC
CCO
Warning: All V , V
connected to Power Supply to guarantee proper operation.
, and V pins must be externally
EE
CC
CCO
V
BB
Figure 1. Logic Diagram and Pinout Assignment
Figure 2. Logic Symbol
Table 1. PIN DESCRIPTION
Table 2. FUNCTION TABLE
PIN
PIN
Function
Function
CLKa Selected
CLKa, CLKb;
ECL Differential Input Pairs
ECL Differential Input Pairs
ECL Differential Outputs
ECL Input Clock Select
Reference Voltage Output
Positive Supply
0
1
CLKa, CLKb
Q0:7; Q0:7
CLK_SEL
CLKb Selected
V
V
V
BB
CC, CCO
EE
V
Negative Supply
NC
No Connect
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2
MC100E310
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
V
CC
V
I
PECL Mode Power Supply
V
= 0 V
8
V
EE
PECL Mode Input Voltage
NECL Mode Input Voltage
V
EE
V
CC
= 0 V
= 0 V
V v V
6
−6
V
V
I
CC
EE
V w V
I
I
Output Current
Continuous
Surge
50
100
mA
mA
out
I
V
Sink/Source
± 0.5
mA
°C
BB
BB
T
Operating Temperature Range
Storage Temperature Range
0 to +85
A
T
−65 to +150
°C
stg
q
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
PLCC−28
PLCC−28
63.5
43.5
°C/W
°C/W
JA
q
Thermal Resistance (Junction−to−Case)
Standard Board
PLCC−28
22 to 26
°C/W
°C
JC
T
sol
Wave Solder
Pb
Pb−Free
265
265
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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3
MC100E310
Table 4. 100E SERIES PECL DC CHARACTERISTICS V
= 5.0 V; V = 0 V (Note 1)
EE
CCx
−40°C
25°C
Typ
85°C
Typ
Symbol
Characteristic
Power Supply Current
Min
Typ
55
Max
60
Min
Max
60
Min
Max Unit
I
EE
55
65
70
mA
mV
mV
mV
mV
V
V
V
V
V
V
V
Output HIGH Voltage (Note 2)
Output LOW Voltage (Note 2)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
3915
3170
3835
3190
3.62
2.7
3995
3305
3975
3355
4120
3445
4120
3525
3.74
4.6
3975
3190
3835
3190
3.62
2.7
4050
3255
3975
3355
4120
3380
4120
3525
3.74
4.6
3975
3190
3835
3190
3.62
2.7
4050
3260
3975
3355
4120
3380
4120
3525
3.74
4.6
OH
OL
IH
IL
BB
Input HIGH Voltage Common Mode
Range (Differential Configuration) (Note 3)
V
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
0.5
0.3
0.5
0.25
0.5
0.2
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with V . V can vary −0.46 V / +0.8 V.
CC
EE
2. Outputs are terminated through a 50 W resistor to V − 2.0 V.
CC
3. V
min varies 1:1 with V , max varies 1:1 with V
.
IHCMR
EE
CC
Table 5. 100E SERIES NECL DC CHARACTERISTICS V
= 0 V; V = −5.0 V (Note 4)
EE
CCx
−40°C
Typ
55
25°C
Typ
55
85°C
Typ
65
Symbol
Characteristic
Power Supply Current
Min
Max
Min
Max
Min
Max Unit
I
EE
60
60
70
mA
mV
V
V
V
V
V
V
Output HIGH Voltage (Note 5)
Output LOW Voltage (Note 5)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
−1085 −1005 −880 −1025 −950
−880 −1025 −950
−880
OH
OL
−1830 −1695 −1555 −1810 −1745 −1620 −1810 −1740 −1620 mV
−1165 −1025 −880 −1165 −1025 −880 −1165 −1025 −880 mV
−1810 −1645 −1475 −1810 −1645 −1475 −1810 −1645 −1475 mV
IH
IL
−1.38
−2.3
−1.26 −1.38
−1.26 −1.38
−1.26
−0.4
V
V
BB
Input HIGH Voltage Common Mode
Range (Differential Configuration) (Note 6)
−0.4
−2.3
−0.4
−2.3
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
0.5
0.3
0.5
0.25
0.5
0.2
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Input and output parameters vary 1:1 with V . V can vary −0.46 V / +0.8 V.
CC
EE
5. Outputs are terminated through a 50 W resistor to V − 2.0 V.
CC
6. V
min varies 1:1 with V , max varies 1:1 with V
.
IHCMR
EE
CC
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4
MC100E310
Table 6. AC CHARACTERISTICS V
= 5.0 V; V = 0 V or V
= 0 V; V = −5.0 V (Note 7)
CCx EE
CCx
EE
−40°C
25°C
Typ
900
85°C
Typ
900
Symbol
Characteristic
Min
Typ
Max
Min
Max
Min
Max
Unit
MHz
ps
f
Maximum Toggle Frequency
700
900
700
700
MAX
t
t
Propagation Delay to Output
IN (differential) (Note 8)
IN (single−ended) (Note 9)
PLH
PHL
525
500
725
750
550
550
750
800
575
600
775
850
t
Within−Device Skew (Note 10)
Part−to−Part Skew (Diff)
75
250
50
200
50
200
ps
skew
t
Random Clock Jitter (RMS)
< 1
< 1
< 1
ps
JITTER
V
Input Voltage Swing
500
200
500
200
500
200
mV
PP
(Differential Configuration)
t /t
r
Output Rise/Fall Time
600
600
600
ps
f
(20%−80%)
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
7. V can vary −0.46 V / +0.8 V.
EE
8. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the
differential output signals. See Definitions and Testing of ECLinPS AC Parameters in Chapter 1 (page 1−12) of the ON Semiconductor
High Performance ECL Data Book (DL140/D).
9. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal.
10.The within−device skew is defined as the worst case difference between any two similar delay paths within a single device.
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MC100E310
Z = 50 W
Q
Q
D
D
o
Receiver
Device
Driver
Device
Z = 50 W
o
50 W
50 W
V
TT
V
TT
= V − 2.0 V
CC
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
ORDERING INFORMATION
†
Device
MC100E310FN
Package
Shipping
PLCC−28
37 Units / Rail
37 Units / Rail
MC100E310FNG
PLCC−28
(Pb−Free)
MC100E310FNR2
MC100E310FNR2G
PLCC−28
500 / Tape & Reel
500 / Tape & Reel
PLCC−28
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
AN1672/D
AND8001/D
AND8002/D
AND8020/D
AND8066/D
AND8090/D
−
−
−
−
−
−
−
−
−
−
−
ECL Clock Distribution Techniques
Designing with PECL (ECL at +5.0 V)
ECLinPSt I/O SPiCE Modeling Kit
Metastability and the ECLinPS Family
Interfacing Between LVDS and ECL
The ECL Translator Guide
Odd Number Counters Design
Marking and Date Codes
Termination of ECL Logic Devices
Interfacing with ECLinPS
AC Characteristics of ECL Devices
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MC100E310
PACKAGE DIMENSIONS
PLCC−28
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776−02
ISSUE E
0.007 (0.180)
M
S
S
N
T
L −M
B
Y BRK
D
0.007 (0.180)
M
S
S
N
-N-
T
L −M
U
Z
-L-
-M-
D
W
0.010 (0.250)
X
S
S
S
N
G1
H
T
L −M
V
28
1
VIEW D-D
0.007 (0.180)
0.007 (0.180)
A
M
M
S
S
S
T
T
L −M
L −M
N
0.007 (0.180)
M
S
S
N
T
L −M
Z
R
S
N
K1
C
E
0.004 (0.100)
G
K
SEATING
PLANE
-T-
J
0.007 (0.180)
M
S
S
N
T
L −M
F
VIEW S
G1
VIEW S
0.010 (0.250)
S
S
S
T
L −M
N
NOTES:
1. DATUMS -L-, -M-, AND -N- DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIM G1, TRUE POSITION TO BE MEASURED
AT DATUM -T-, SEATING PLANE.
3. DIM R AND U DO NOT INCLUDE MOLD FLASH.
ALLOWABLE MOLD FLASH IS 0.010 (0.250)
PER SIDE.
INCHES
MIN MAX
MILLIMETERS
MIN MAX
DIM
A
0.485 0.495 12.32 12.57
0.485 0.495 12.32 12.57
B
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
C
0.165 0.180
0.090 0.110
0.013 0.019
0.050 BSC
4.20
2.29
0.33
4.57
2.79
0.48
E
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
F
G
H
1.27 BSC
0.026 0.032
0.66
0.51
0.64
0.81
ꢀ
J
0.020
0.025
ꢀ
ꢀ
K
ꢀ
R
0.450 0.456 11.43
0.450 0.456 11.43
11.58
11.58
1.21
1.21
1.42
0.50
10°
U
V
0.042 0.048
0.042 0.048
0.042 0.056
1.07
1.07
1.07
ꢀ
W
X
Y
ꢀ
0.020
10°
Z
2°
2°
G1
K1
0.410 0.430 10.42 10.92
0.040 ꢀꢁ 1.02 ꢀꢁ
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MC100E310
ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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USA/Canada
Europe, Middle East and Africa Technical Support:
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MC100E310/D
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