MC100E431FN [ONSEMI]
5V ECL 3-Bit Differential Flip-Flop; 5V ECL 3位差分触发器
| 型号： | MC100E431FN |
| 厂家： | 
ONSEMI |
| 描述： | 5V ECL 3-Bit Differential Flip-Flop |
| 文件： | 总9页 (文件大小：134K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC10E431, MC100E431
5VꢀECL 3-Bit Differential
Flip-Flop
Description
The MC10E/100E431 is a 3-bit flip-flop with differential clock,
data input and data output.
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The asynchronous Set and Reset controls are edge-triggered rather
than level controlled. This allows the user to rapidly set or reset the
flip-flop and then continue clocking at the next clock edge, without the
necessity of de-asserting the set/reset signal (as would be the case with
a level controlled set/reset).
PLCC−28
FN SUFFIX
CASE 776
The E431 is also designed with larger internal swings, an approach
intended to minimize the time spent crossing the threshold region and
thus reduce the metastability susceptibility window.
MARKING DIAGRAM*
The differential input structures are clamped so that the inputs of
unused registers can be left open without upsetting the bias network of
the device. The clamping action will assert the D and the CLK sides of
the inputs. Because of the edge triggered flip-flop nature of the device
simultaneously opening both the clock and data inputs will result in an
output which reaches an unidentified but valid state. Note that the
1 28
MCxxxE431FNG
AWLYYWW
input clamps only operate when both inputs fall to 2.5 V below V
.
CC
The V pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
BB
xxx
A
WL
YY
WW
G
= 10 or 100
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
differential input is connected to V as a switching reference voltage.
BB
V
may also rebias AC coupled inputs. When used, decouple V
BB
BB
and V via a 0.01 mF capacitor and limit current sourcing or sinking
CC
to 0.5 mA. When not used, V should be left open.
BB
The 100 Series contains temperature compensation.
*For additional marking information, refer to
Application Note AND8002/D.
Features
• Edge-Triggered Asynchronous Set and Reset
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
• Differential D, CLK and Q; V Reference Available
BB
• 1100 MHz Min. Toggle Frequency
• PECL Mode Operating Range: V = 4.2 V to 5.7 V
CC
with V = 0 V
EE
• NECL Mode Operating Range: V = 0 V
• Moisture Sensitivity Level: Pb = 1; Pb−Free = 3
For Additional Information, see Application Note
AND8003/D
• Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
CC
with V = −4.2 V to −5.7 V
EE
• Internal Input 50 kW Pulldown Resistors
• ESD Protection: Human Body Model; > 2 kV,
Machine Model; > 200 V
• Transistor Count = 348 devices
• Pb−Free Packages are Available*
Charged Device Model; > 2 kV
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC
Latchup Test
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
November, 2006 − Rev. 10
MC10E431/D
MC10E431, MC100E431
V
CLK2 CLK2
24 23
D
D
R
S
2
BB
2
2
2
Table 1. PIN DESCRIPTION
PIN
25
22
21
20
19
FUNCTION
CLK1
CLK1
18
17
16
15
14
13
Q
Q
26
27
2
D[0:2], D[0:2]
CLK[0:2], CLK[0:2]
S[0:2]
ECL Differential Data Inputs
ECL Differential Clock
2
ECL Edge Triggered Set Inputs
ECL Edge Triggered Reset Input
ECL Differential Data Outputs
Reference Voltage Output
Positive Supply
R
1
28
V
CC
R[0:2]
1
V
EE
Q[0:2], Q[0:2]
Q
Q
Q
Q
1
1
0
0
MC10E431/MC100E431
V
V
V
BB
CC
EE
S
2
3
4
1
, V
CCO
D
1
D
1
Negative Supply
12
5
6
7
8
9
10
11
CLK0 CLK0
* All V and V
D
D
R
S
V
CCO
0
0
0
0
pins are tied together on the die.
CCO
CC
Warning: All V , V
, and V pins must be externally con-
CCO EE
CC
nected to Power Supply to guarantee proper operation.
Figure 1. Pinout: PLCC−28 (Top View)
S
0
D
D
S
0
0
D
D
Q
Q
Q
Q
0
0
Table 2. FUNCTION TABLE
Dn
L
CLKn
Rn
L
Sn
L
Qn
L
CLK0
CLK0
Z
Z
X
X
R
S
R
0
1
H
X
L
L
H
L
S
Z
L
D
D
1
1
Q
Q
Q
Q
1
1
X
L
Z
H
CLK1
CLK1
Z = Low to high transition
X = Don’t Care
R
S
R
1
2
S
D
D
2
2
D
Q
Q
Q
Q
2
2
CLK2
CLK2
R
R
2
V
BB
Figure 2. Logic Diagram
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2
MC10E431, MC100E431
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
V
V
PECL Mode Power Supply
V
= 0 V
8
V
CC
I
EE
PECL Mode Input Voltage
NECL Mode Input Voltage
V
V
= 0 V
= 0 V
V v V
6
−6
V
V
EE
CC
I
CC
V w V
I
EE
I
I
Output Current
Continuous
Surge
50
100
mA
mA
out
V
Sink/Source
BB
± 0.5
mA
°C
BB
T
A
Operating Temperature Range
0 to +85
T
stg
Storage Temperature Range
−65 to +150
°C
q
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
PLCC−28
PLCC−28
63.5
43.5
°C/W
°C/W
JA
q
Thermal Resistance (Junction−to−Case)
Standard Board
PLCC−28
22 to 26
°C/W
°C
JC
T
sol
Wave Solder
Pb
Pb−Free
265
265
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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3
MC10E431, MC100E431
Table 4. 10E SERIES PECL DC CHARACTERISTICS V = 5.0 V; V = 0.0 V (Note 1)
CCx
EE
0°C
25°C
Typ
85°C
Typ
Characteristic
Power Supply Current
Min
Typ
110
Max
Min
Max
132
Min
Max
132
Unit
mA
mV
mV
mV
mV
V
Symbol
I
132
4160
3370
4160
3520
3.74
5.0
110
110
EE
V
V
V
V
V
V
Output HIGH Voltage (Note 2)
Output LOW Voltage (Note 2)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
3980
3050
3830
3050
3.62
2.7
4070
3210
3995
3285
4020
3050
3870
3050
3.65
2.7
4105
3210
4030
3285
4190
3370
4190
3520
3.75
5.0
4090
3050
3940
3050
3.69
2.7
4185
3227
4110
3302
4280
3405
4280
3555
3.81
5.0
OH
OL
IH
IL
BB
Input HIGH Voltage Common Mode
Range (Differential Configuration) (Note 3)
V
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
IL
0.5
0.3
0.5
0.25
0.3
0.2
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with V . V can vary −0.46 V / +0.06 V.
CC
EE
2. Outputs are terminated through a 50 W resistor to V − 2.0 V.
CC
3. V
min varies 1:1 with V , max varies 1:1 with V
.
IHCMR
EE
CC
Table 5. 10E SERIES NECL DC CHARACTERISTICS V = 0.0 V; V = −5.0 V (Note 4)
CCx
EE
0°C
25°C
85°C
Symbol
Characteristic
Power Supply Current
Min
Typ
Max
Min
Typ
Max
132
Min
Typ
Max
132
Unit
mA
mV
I
110
132
110
110
EE
V
V
V
V
V
V
Output HIGH Voltage (Note 5)
Output LOW Voltage (Note 5)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
−1020 −930
−840
−980
−895
−810
−910
−815
−720
OH
OL
−1950 −1790 −1630 −1950 −1790 −1630 −1950 −1773 −1595 mV
−1170 −1005 −840 −1130 −970 −810 −1060 −890 −720 mV
−1950 −1715 −1480 −1950 −1715 −1480 −1950 −1698 −1445 mV
IH
IL
−1.38
−2.3
−1.27 −1.35
−1.25 −1.31
−1.19
V
V
BB
Input HIGH Voltage Common Mode
Range (Differential Configuration) (Note 6)
0.0
−2.3
0.0
−2.3
0.0
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
IL
0.5
0.3
0.5
0.065
0.3
0.2
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
4. Input and output parameters vary 1:1 with V . V can vary −0.46 V / +0.06 V.
CC
EE
5. Outputs are terminated through a 50 W resistor to V − 2.0 V.
CC
6. V
min varies 1:1 with V , max varies 1:1 with V
.
IHCMR
EE
CC
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4
MC10E431, MC100E431
Table 6. 100E SERIES PECL DC CHARACTERISTICS V = 5.0 V; V = 0.0 V (Note 7)
CCx
EE
0°C
25°C
Typ
85°C
Typ
Symbol
Characteristic
Power Supply Current
Min
Typ
110
Max
132
Min
Max
132
Min
Max
152
Unit
mA
mV
mV
mV
mV
V
I
110
127
EE
V
V
V
V
V
V
Output HIGH Voltage (Note 8)
Output LOW Voltage (Note 8)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
3975
3190
3835
3190
3.62
2.7
4050
3295
3975
3355
4120
3380
4120
3525
3.74
5.0
3975
3190
3835
3190
3.62
2.7
4050
3255
3975
3355
4120
3380
4120
3525
3.74
5.0
3975
3190
3835
3190
3.62
2.7
4050
3260
3975
3355
4120
3380
4120
3525
3.74
5.0
OH
OL
IH
IL
BB
Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 9)
V
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
IL
0.5
0.3
0.5
0.25
0.5
0.2
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
7. Input and output parameters vary 1:1 with V . V can vary −0.46 V / +0.8 V.
CC
EE
8. Outputs are terminated through a 50 W resistor to V − 2.0 V.
CC
9. V
min varies 1:1 with V , max varies 1:1 with V
.
IHCMR
EE
CC
Table 7. 100E SERIES NECL DC CHARACTERISTICS V = 0.0 V; V = −5.0 V (Note 10)
CCx
EE
0°C
25°C
Typ
110
85°C
Typ
127
Symbol
Characteristic
Power Supply Current
Min
Typ
Max
Min
Max
Min
Max
152
Unit
mA
mV
I
110
132
132
EE
V
V
V
V
V
V
Output HIGH Voltage (Note 11)
Output LOW Voltage (Note 11)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
−1025 −950
−880 −1025 −950
−880 −1025 −950
−880
OH
OL
−1810 −1705 −1620 −1810 −1745 −1620 −1810 −1740 −1620 mV
−1165 −1025 −880 −1165 −1025 −880 −1165 −1025 −880 mV
−1810 −1645 −1475 −1810 −1645 −1475 −1810 −1645 −1475 mV
IH
IL
−1.38
−1.26 −1.38
−1.26 −1.38
−1.26
V
V
BB
Input HIGH Voltage Common Mode Range −2.3
(Differential Configuration) (Note 12)
0.0
−2.3
0.0
−2.3
0.0
IHCMR
I
I
Input HIGH Current
150
150
150
mA
mA
IH
IL
Input LOW Current
0.5
0.3
0.5
0.25
0.5
0.2
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
10.Input and output parameters vary 1:1 with V . V can vary −0.46 V / +0.8 V.
CC
EE
11. Outputs are terminated through a 50 W resistor to V − 2.0 V.
CC
12.V
min varies 1:1 with V , max varies 1:1 with V
.
IHCMR
EE
CC
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5
MC10E431, MC100E431
Table 8. AC CHARACTERISTICS V = 5.0 V; V = 0.0 V or V
= 0.0 V; V = −5.0 V (Note 13)
CCx EE
CCx
EE
−40°C
25°C
Typ
1.1
85°C
Min
Typ
Max
Min
Max
Min
Typ
Max
Symbol
Characteristic
Maximum Toggle Frequency
Propagation Delay to Output
Unit
GHz
ps
f
MAX
t
t
CLK
550
500
500
700
725
725
850
975
975
550
550
550
700
725
725
850
925
925
550
550
550
700
725
725
850
925
925
PLH
PHL
R
S
t
Setup Time
D
250
1100
1100
0
700
700
200
1000
1000
0
700
700
200
1000
1000
0
700
700
ps
S
R (Note 14)
S (Note 14)
t
t
t
t
Hold Time
D
250
400
0
200
400
0
200
400
0
ps
ps
H
Minimum Pulse Width
Within-Device Skew (Note 15)
Random Clock Jitter (RMS)
CLK
PW
50
50
ps
skew
JITTER
< 1
< 1
< 1
ps
V
Input Voltage Swing
150
250
1000
700
150
1000
150
275
1000
650
mV
PP
(Differential Configuration)
t /t
r
Rise/Fall Times
450
450
ps
f
(20−80%)
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
13.10 Series: V can vary −0.46 V / +0.06 V.
EE
100 Series: V can vary −0.46 V / +0.8 V.
EE
14.These setup times define the minimum time the CLK or SET/RESET input must wait after the assertion of the RESET/SET input to assure
the proper operation of the flip-flop.
15.Within-device skew is defined as identical transitions on similar paths through a device.
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6
MC10E431, MC100E431
Z = 50 W
Q
Q
D
D
o
Receiver
Device
Driver
Device
Z = 50 W
o
50 W
50 W
V
TT
V
= V − 2.0 V
TT
CC
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
ORDERING INFORMATION
†
Device
Package
Shipping
MC10E431FN
PLCC−28
37 Units / Rail
37 Units / Rail
MC10E431FNG
PLCC−28
(Pb−Free)
MC10E431FNR2
PLCC−28
500 / Tape & Reel
500 / Tape & Reel
MC10E431FNR2G
PLCC−28
(Pb−Free)
MC100E431FN
PLCC−28
37 Units / Rail
37 Units / Rail
MC100E431FNG
PLCC−28
(Pb−Free)
MC100E431FNR2
MC100E431FNR2G
PLCC−28
500 / Tape & Reel
500 / Tape & Reel
PLCC−28
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
AN1672/D
AND8001/D
AND8002/D
AND8020/D
AND8066/D
AND8090/D
−
−
−
−
−
−
−
−
−
−
−
ECL Clock Distribution Techniques
Designing with PECL (ECL at +5.0 V)
ECLinPSt I/O SPiCE Modeling Kit
Metastability and the ECLinPS Family
Interfacing Between LVDS and ECL
The ECL Translator Guide
Odd Number Counters Design
Marking and Date Codes
Termination of ECL Logic Devices
Interfacing with ECLinPS
AC Characteristics of ECL Devices
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7
MC10E431, MC100E431
PACKAGE DIMENSIONS
PLCC−28
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776−02
ISSUE E
M
S
S
0.007 (0.180)
T
L−M
N
B
Y BRK
D
−N−
M
S
S
N
0.007 (0.180)
T
L−M
U
Z
−M−
−L−
W
D
S
S
S
N
0.010 (0.250)
T
L−M
X
G1
V
28
1
VIEW D−D
M
S
S
S
A
0.007 (0.180)
0.007 (0.180)
T
L−M
L−M
N
M
S
S
N
0.007 (0.180)
T
L−M
H
Z
M
S
T
N
R
K1
C
E
0.004 (0.100)
G
K
SEATING
PLANE
−T−
J
M
S
S
N
0.007 (0.180)
T
L−M
F
VIEW S
G1
S
S
S
N
0.010 (0.250)
T
L−M
VIEW S
NOTES:
INCHES
MILLIMETERS
1. DATUMS −L−, −M−, AND −N− DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM −T−, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE
MOLD FLASH. ALLOWABLE MOLD FLASH IS
0.010 (0.250) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
DIM MIN
MAX
0.495
0.495
0.180
0.110
0.019
MIN
12.32
12.32
4.20
MAX
12.57
12.57
4.57
A
B
C
E
F
0.485
0.485
0.165
0.090
0.013
2.29
0.33
2.79
0.48
G
H
J
0.050 BSC
1.27 BSC
0.026
0.020
0.025
0.450
0.450
0.042
0.042
0.042
0.032
−−−
−−−
0.66
0.51
0.64
11.43
11.43
1.07
1.07
1.07
−−−
0.81
−−−
K
R
U
V
W
X
Y
Z
−−−
0.456
0.456
0.048
0.048
0.056
11.58
11.58
1.21
1.21
1.42
0.50
10
−−− 0.020
10
2
2
_
_
_
_
G1 0.410
K1 0.040
0.430
−−−
10.42
1.02
10.92
−−−
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
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8
MC10E431, MC100E431
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
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MC10E431/D
相关型号：
MC100E431FNR2G
100E SERIES, TRIPLE POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PQCC28, LEAD FREE, PLASTIC, LCC-28
ROCHESTER
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