MC100EP05DTR2G [ONSEMI]
3.3V / 5V ECL 2−Input Differential AND/NAND; 3.3V / 5V ECL 2输入差分AND / NAND
| 型号： | MC100EP05DTR2G |
| 厂家： | 
ONSEMI |
| 描述： | 3.3V / 5V ECL 2−Input Differential AND/NAND |
| 文件： | 总11页 (文件大小：108K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC10EP05, MC100EP05
3.3V / 5VꢀECL 2−Input
Differential AND/NAND
Description
The MC10/100EP05 is a 2−input differential AND/NAND gate.
The device is functionally equivalent to the EL05 and LVEL05
devices. With AC performance much faster than the LVEL05 device,
the EP05 is ideal for applications requiring the fastest
AC performance available.
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MARKING DIAGRAMS*
The 100 Series contains temperature compensation.
8
8
8
HEP05
ALYWG
G
KEP05
ALYWG
G
Features
1
• 220 ps Typical Propagation Delay
• Maximum Frequency > 3 GHz Typical
SOIC−8
D SUFFIX
CASE 751
1
1
• PECL Mode Operating Range: V = 3.0 V to 5.5 V
CC
with V = 0 V
EE
• NECL Mode Operating Range: V = 0 V
CC
8
8
1
8
with V = −3.0 V to −5.5 V
EE
1
HP05
KP05
• Open Input Default State
• Safety Clamp on Inputs
• Q Output Will Default LOW with Inputs Open or at V
• Pb−Free Packages are Available
ALYWG
ALYWG
TSSOP−8
DT SUFFIX
CASE 948R
G
G
1
EE
1
4
1
4
DFN8
MN SUFFIX
CASE 506AA
H
K
5I
= MC10
= MC100
= MC10
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
2X = MC100
= Date Code
D
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
November, 2006 − Rev. 8
MC10EP05/D
MC10EP05, MC100EP05
Table 1. PIN DESCRIPTION
Pin
D0*, D1*, D0**, D1**
Q, Q
Function
ECL Data Inputs
1
2
8
7
D
D
V
CC
0
ECL Data Outputs
Positive Supply
Negative Supply
V
Q
Q
CC
0
V
EE
* Pins will default LOW when left open.
** Pins will default to V /2when left open.
CC
6
5
D
1
3
4
Table 2. TRUTH TABLE
D0
D1
D0
D1
Q
Q
L
L
H
H
L
H
L
H
H
L
H
L
H
L
L
L
L
H
H
H
L
D
1
V
EE
H
L
H
Figure 1. 8−Lead Pinout (Top View) and Logic
Diagram
Table 3. ATTRIBUTES
Characteristics
Internal Input Pulldown Resistor
Value
75 kW
Internal Input Pullup Resistor
ESD Protection
37.5 kW
Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Pb Pkg
Pb−Free Pkg
SOIC−8
TSSOP−8
DFN8
Level 1
Level 1
Level 1
Level 1
Level 3
Level 1
Flammability Rating
Transistor Count
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
137 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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2
MC10EP05, MC100EP05
Table 4. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
= 0 V
Condition 2
Rating
Unit
V
V
V
V
PECL Mode Power Supply
NECL Mode Power Supply
V
V
6
CC
EE
I
EE
CC
= 0 V
−6
V
PECL Mode Input Voltage
NECL Mode Input Voltage
V
V
= 0 V
= 0 V
V v V
6
V
V
EE
CC
I
CC
EE
V w V
−6
I
I
Output Current
Continuous
Surge
50
mA
mA
out
100
T
Operating Temperature Range
Storage Temperature Range
−40 to +85
°C
°C
A
T
−65 to +150
stg
JA
q
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
SOIC−8
SOIC−8
190
130
°C/W
°C/W
q
q
Thermal Resistance (Junction−to−Case)
Standard Board
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
Standard Board
Thermal Resistance (Junction−to−Ambient) 0 lfpm
SOIC−8
41 to 44
°C/W
JC
JA
TSSOP−8
TSSOP−8
185
140
°C/W
°C/W
q
q
Thermal Resistance (Junction−to−Case)
TSSOP−8
41 to 44
°C/W
JC
JA
DFN8
DFN8
129
84
°C/W
°C/W
500 lfpm
T
sol
Wave Solder
Pb <2 to 3 sec @ 248°C
Pb−Free <2 to 3 sec @ 260°C
265
265
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 5. 10EP DC CHARACTERISTICS, PECL V = 3.3 V, V = 0 V (Note 2)
CC
EE
−40°C
25°C
Typ
85°C
Typ
Symbol
Characteristic
Power Supply Current
Min
20
Typ
24
Max
29
Min
20
Max
29
Min
20
Max
29
Unit
mA
mV
mV
mV
mV
V
I
24
24
EE
V
Output HIGH Voltage (Note 3)
Output LOW Voltage (Note 3)
2165
1365
2090
1365
2.0
2290
1490
2415
1615
2415
1690
3.3
2230
1430
2155
1460
2.0
2355
1555
2480
1680
2480
1755
3.3
2290
1490
2215
1490
2.0
2415
1615
2540
1740
2540
1815
3.3
OH
OL
V
V
V
V
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
IH
IL
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 4)
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
IL
D
D
0.5
−150
0.5
−150
0.5
−150
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Input and output parameters vary 1:1 with V . V can vary +0.3 V to −2.2 V.
CC
EE
3. All loading with 50 W to V − 2.0 V.
CC
4. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
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3
MC10EP05, MC100EP05
Table 6. 10EP DC CHARACTERISTICS, PECL V = 5.0 V, V = 0 V (Note 5)
CC
EE
−40°C
25°C
Typ
85°C
Typ
Symbol
Characteristic
Power Supply Current
Min
20
Typ
24
Max
29
Min
20
Max
29
Min
20
Max
29
Unit
mA
mV
mV
mV
mV
V
I
24
24
EE
V
Output HIGH Voltage (Note 6)
Output LOW Voltage (Note 6)
3865
3065
3790
3065
2.0
3990
3190
4115
3315
4115
3390
5.0
3930
3130
3855
3130
2.0
4055
3255
4180
3380
4180
3455
5.0
3990
3190
3915
3190
2.0
4115
3315
4240
3440
4240
3515
5.0
OH
OL
V
V
V
V
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
IH
IL
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 7)
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
IL
D
D
0.5
−150
0.5
−150
0.5
−150
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and output parameters vary 1:1 with V . V can vary +2.0 V to −0.5 V.
CC
EE
6. All loading with 50 W to V − 2.0 V.
CC
7. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
Table 7. 10EP DC CHARACTERISTICS, NECL V = 0 V, V = −5.5 V to −3.0 V (Note 8)
CC
EE
−40°C
Typ
24
25°C
Typ
24
85°C
Typ
24
Symbol
Characteristic
Min
20
Max
Min
Max
Min
Max
29
Unit
mA
mV
mV
mV
mV
V
I
Power Supply Current
29
20
29
20
EE
V
Output HIGH Voltage (Note 9)
Output LOW Voltage (Note 9)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
−1135 −1010 −885 −1070 −945
−820 −1010 −885
−760
OH
OL
V
V
V
V
−1935 −1810 −1685 −1870 −1745 −1620 −1810 −1685 −1560
−1210
−1935
−885 −1145
−1610 −1870
−820 −1085
−1545 −1810
−760
−1485
0.0
IH
IL
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 10)
V
+2.0
0.0
V
+2.0
0.0
V
+2.0
EE
IHCMR
EE
EE
I
I
Input HIGH Current
150
150
150
mA
mA
IH
IL
Input LOW Current
D
D
0.5
−150
0.5
−150
0.5
−150
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
8. Input and output parameters vary 1:1 with V
.
CC
9. All loading with 50 W to V − 2.0 V.
CC
10.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
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4
MC10EP05, MC100EP05
Table 8. 100EP DC CHARACTERISTICS, PECL V = 3.3 V, V = 0 V (Note 11)
CC
EE
−40°C
Typ
25°C
Typ
85°C
Typ
Symbol
Characteristic
Power Supply Current
Min
15
Max
Min
17
Max
36
Min
19
Max
38
Unit
mA
mV
mV
mV
mV
V
I
25
32
27
28
EE
V
Output HIGH Voltage (Note 12)
Output LOW Voltage (Note 12)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
2155
1355
2075
1355
2.0
2280
1480
2405
1605
2420
1675
3.3
2155
1355
2075
1355
2.0
2280
1480
2405
1605
2420
1675
3.3
2155
1355
2075
1355
2.0
2280
1480
2405
1605
2420
1675
3.3
OH
OL
V
V
V
V
IH
IL
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 13)
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
IL
D
D
0.5
−150
0.5
−150
0.5
−150
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
11. Input and output parameters vary 1:1 with V . V can vary +0.3 V to −2.2 V.
CC
EE
12.All loading with 50 W to V − 2.0 V.
CC
13.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
Table 9. 100EP DC CHARACTERISTICS, PECL V = 5.0 V, V = 0 V (Note 14)
CC
EE
−40°C
Typ
25°C
Typ
85°C
Typ
Symbol
Characteristic
Power Supply Current
Min
15
Max
Min
17
Max
36
Min
19
Max
38
Unit
mA
mV
mV
mV
mV
V
I
25
32
27
28
EE
V
Output HIGH Voltage (Note 15)
Output LOW Voltage (Note 15)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
3855
3055
3775
3055
2.0
3980
3180
4105
3305
4120
3375
5.0
3855
3055
3775
3055
2.0
3980
3180
4105
3305
4120
3375
5.0
3855
3055
3775
3055
2.0
3980
3180
4105
3305
4120
3375
5.0
OH
OL
V
V
V
V
IH
IL
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 16)
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
IL
D
D
0.5
−150
0.5
−150
0.5
−150
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
14.Input and output parameters vary 1:1 with V . V can vary +2.0 V to −0.5 V.
CC
EE
15.All loading with 50 W to V − 2.0 V.
CC
16.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
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5
MC10EP05, MC100EP05
Table 10. 100EP DC CHARACTERISTICS, NECL V = 0 V, V = −5.5 V to −3.0 V (Note 17)
CC
EE
−40°C
25°C
Typ
27
85°C
Typ
28
Symbol
Characteristic
Min
Typ
Max
Min
Max
Min
Max
Unit
mA
mV
mV
mV
mV
V
I
Power Supply Current
15
25
32
17
36
19
38
EE
V
Output HIGH Voltage (Note 18)
Output LOW Voltage (Note 18)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
−1145 −1020 −895 −1145 −1020 −895 −1145 −1020 −895
−1945 −1820 −1695 −1945 −1820 −1695 −1945 −1820 −1695
OH
OL
V
V
V
V
−1225
−1945
−880 −1225
−1625 −1945
−880 −1225
−1625 −1945
−880
−1625
0.0
IH
IL
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 19)
V
+2.0
0.0
V
+2.0
0.0
V
+2.0
EE
IHCMR
EE
EE
I
I
Input HIGH Current
150
150
150
mA
mA
IH
IL
Input LOW Current
D
0.5
0.5
0.5
D
−150
−150
−150
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
17.Input and output parameters vary 1:1 with V
.
CC
18.All loading with 50 W to V − 2.0 V.
CC
19.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
Table 11. AC CHARACTERISTICS V = 0 V; V = −3.0 V to −5.5 V or V = 3.0 V to 5.5 V; V = 0 V (Note 20)
CC
EE
CC
EE
−40°C
Typ
25°C
Typ
> 3
85°C
Typ
> 3
Symbol
Characteristic
Maximum Frequency
Min
Max
Min
Max
Min
Max
Unit
f
> 3
GHz
max
(Figure 2)
t
t
,
Propagation Delay to
Output Differential
160
210
0.2
260
< 1
170
220
0.2
270
< 1
210
260
0.2
320
1.5
ps
ps
PLH
PHL
t
Random Clock Jitter
(Figure 2)
JITTER
V
Input Voltage Swing (Differential Con-
figuration)
150
70
800
120
1200
170
150
80
800
130
1200
180
150
100
800
150
1200
200
mV
ps
PP
t
t
Output Rise/Fall Times
(20% − 80%)
Q
r
f
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
20.Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to V − 2.0 V.
CC
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6
MC10EP05, MC100EP05
10
9
850
750
650
550
450
350
250
5 V
8
3.3 V
7
6
5
4
3
2
1
0
(JITTER)
1.0
1.5
2.0
2.5
3.0
FREQUENCY (GHz)
Figure 2. Fmax/Jitter @ 255C
Z = 50 W
o
Q
D
Receiver
Device
Driver
Device
Q
Z = 50 W
o
D
50 W
50 W
V
TT
V
= V − 2.0 V
TT
CC
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
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7
MC10EP05, MC100EP05
ORDERING INFORMATION
Device
†
Package
Shipping
MC10EP05D
SOIC−8
98 Units / Rail
98 Units / Rail
MC10EP05DG
SOIC−8
(Pb−Free)
MC10EP05DR2
SOIC−8
2500 / Tape & Reel
2500 / Tape & Reel
MC10EP05DR2G
SOIC−8
(Pb−Free)
MC10EP05DT
TSSOP−8
100 Units / Rail
100 Units / Rail
MC10EP05DTG
TSSOP−8
(Pb−Free)
MC10EP05DTR2
TSSOP−8
2500 / Tape & Reel
2500 / Tape & Reel
MC10EP05DTR2G
TSSOP−8
(Pb−Free)
MC10EP05MNR4
MC10EP05MNR4G
DFN8
1000 / Tape & Reel
1000 / Tape & Reel
DFN8
(Pb−Free)
MC100EP05D
SOIC−8
98 Units / Rail
98 Units / Rail
MC100EP05DG
SOIC−8
(Pb−Free)
MC100EP05DR2
SOIC−8
2500 / Tape & Reel
2500 / Tape & Reel
MC100EP05DR2G
SOIC−8
(Pb−Free)
MC100EP05DT
TSSOP−8
100 Units / Rail
100 Units / Rail
MC100EP05DTG
TSSOP−8
(Pb−Free)
MC100EP05DTR2
MC100EP05DTR2G
TSSOP−8
2500 / Tape & Reel
2500 / Tape & Reel
TSSOP−8
(Pb−Free)
MC100EP05MNR4
MC100EP05MNR4G
DFN8
1000 / Tape & Reel
1000 / Tape & Reel
DFN8
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
AN1672/D
AND8001/D
AND8002/D
AND8020/D
AND8066/D
AND8090/D
−
−
−
−
−
−
−
−
−
−
−
ECL Clock Distribution Techniques
Designing with PECL (ECL at +5.0 V)
ECLinPSt I/O SPiCE Modeling Kit
Metastability and the ECLinPS Family
Interfacing Between LVDS and ECL
The ECL Translator Guide
Odd Number Counters Design
Marking and Date Codes
Termination of ECL Logic Devices
Interfacing with ECLinPS
AC Characteristics of ECL Devices
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8
MC10EP05, MC100EP05
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AH
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−X−
A
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
−Z−
1.27 BSC
0.050 BSC
0.10 (0.004)
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
SOLDERING FOOTPRINT*
1.52
0.060
7.0
4.0
0.275
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
9
MC10EP05, MC100EP05
PACKAGE DIMENSIONS
TSSOP−8
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948R−02
ISSUE A
8x K REF
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
M
S
S
V
0.10 (0.004)
T U
S
0.15 (0.006) T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
2X L/2
8
5
4
0.25 (0.010)
B
−U−
L
1
M
PIN 1
IDENT
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE −W−.
S
0.15 (0.006) T U
A
−V−
F
DETAIL E
MILLIMETERS
INCHES
MIN
DIM MIN
MAX
3.10
3.10
MAX
0.122
0.122
0.043
0.006
0.028
A
B
C
D
F
2.90
2.90
0.80
0.05
0.40
0.114
0.114
C
1.10 0.031
0.15 0.002
0.70 0.016
0.10 (0.004)
−W−
SEATING
D
−T−
G
G
K
L
0.65 BSC
0.026 BSC
PLANE
0.25
0.40 0.010
0.016
4.90 BSC
0.193 BSC
0
DETAIL E
M
0
6
6
_
_
_
_
http://onsemi.com
10
MC10EP05, MC100EP05
PACKAGE DIMENSIONS
DFN8
CASE 506AA−01
ISSUE D
D
A
B
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ASME Y14.5M, 1994 .
2. CONTROLLING DIMENSION:
MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED
BETWEEN 0.25 AND 0.30 MM FROM
TERMINAL.
PIN ONE
REFERENCE
4. COPLANARITY APPLIES TO THE
EXPOSED PAD AS WELL AS THE
TERMINALS.
E
MILLIMETERS
DIM MIN
MAX
1.00
0.05
2 X
A
A1
A3
b
0.80
0.00
0.20 REF
0.10
C
0.20
0.30
2 X
D
2.00 BSC
0.10
C
TOP VIEW
D2
E
1.10
2.00 BSC
1.30
E2
e
0.70
0.50 BSC
0.90
K
L
0.20
0.25
−−−
0.35
A
0.10
0.08
C
C
8 X
(A3)
SIDE VIEW
D2
A1
SEATING
PLANE
C
e
e/2
4
1
8 X L
E2
K
8
5
0.10 C A B
8 X b
0.05
C
NOTE 3
BOTTOM VIEW
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
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