MC100EP08DR2 [ONSEMI]
Differential 2-Input XOR/XNOR; 差2输入XOR / XNOR
| 型号： | MC100EP08DR2 |
| 厂家： | 
ONSEMI |
| 描述： | Differential 2-Input XOR/XNOR |
| 文件： | 总8页 (文件大小：79K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC10EP08, MC100EP08
3.3V / 5VĄECL 2-Input
Differential XOR/XNOR
The MC10/100EP08 is a differential XOR/XNOR gate. The EP08 is
ideal for applications requiring the fastest AC performance available.
The 100 Series contains temperature compensation.
http://onsemi.com
MARKING DIAGRAMS*
• 250 ps Typical Propagation Delay
• Maximum Frequency > 3 GHz Typical
• PECL Mode Operating Range: V = 3.0 V to 5.5 V
CC
8
8
with V = 0 V
EE
8
• NECL Mode Operating Range: V = 0 V
HEP08
ALYW
KEP08
ALYW
CC
1
with V = –3.0 V to –5.5 V
EE
SO–8
• Open Input Default State
• Safety Clamp on Inputs
D SUFFIX
CASE 751
1
1
• Q Output Will Default LOW with Inputs Open or at V
EE
8
1
8
1
8
1
HP08
ALYW
KP08
ALYW
TSSOP–8
DT SUFFIX
CASE 948R
L = Wafer Lot
Y = Year
H = MC10
K = MC100
W = Work Week
A = Assembly Location
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Device
Package
Shipping
MC10EP08D
SO–8
98 Units/Rail
MC10EP08DR2
MC100EP08D
MC100EP08DR2
MC10EP08DT
SO–8
SO–8
2500 Tape & Reel
98 Units/Rail
SO–8
2500 Tape & Reel
100 Units/Rail
TSSOP–8
MC10EP08DTR2 TSSOP–8 2500 Tape & Reel
MC100EP08DT TSSOP–8 100 Units/Rail
MC100EP08DTR2 TSSOP–8 2500 Tape & Reel
Semiconductor Components Industries, LLC, 2001
1
Publication Order Number:
April, 2001 – Rev. 3
MC10EP08/D
MC10EP08, MC100EP08
PIN DESCRIPTION
FUNCTION
D0
D0
1
2
8
7
V
CC
PIN
D0, D1, D0, D1
Q, Q
ECL Data Inputs
ECL Data Outputs
Q
V
CC
Positive Supply
Negative Supply
V
EE
TRUTH TABLE
D1
D1
3
4
6
5
Q
D0*
D1*
D0**
D1**
Q
Q
L
L
H
H
L
H
L
H
H
L
H
L
H
L
L
H
L
L
H
H
L
H
L
H
V
EE
*
Pins will default LOW when left open.
** Pins will default to V /2 when left open.
CC
Figure 1. 8–Lead Pinout (Top View) and Logic Diagram
ATTRIBUTES
Characteristics
Value
75 kW
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
37.5 kW
Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1.)
Level 1
Flammability Rating
Oxygen Index
UL–94 code V–0 A 1/8”
28 to 34
Transistor Count
135
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MAXIMUM RATINGS (Note 2.)
Symbol Parameter
Condition 1
= 0 V
Condition 2
Rating
Units
V
CC
V
EE
V
I
PECL Mode Power Supply
NECL Mode Power Supply
V
V
6
V
V
EE
= 0 V
–6
CC
PECL Mode Input Voltage
NECL Mode Input Voltage
V
EE
V
CC
= 0 V
= 0 V
V ꢀ V
6
–6
V
V
I
CC
EE
V ꢁ V
I
I
Output Current
Continuous
Surge
50
100
mA
mA
out
TA
Operating Temperature Range
–40 to +85
°C
°C
T
stg
Storage Temperature Range
–65 to +150
θ
Thermal Resistance (Junction to Ambient)
0 LFPM
500 LFPM
8 SOIC
8 SOIC
190
130
°C/W
°C/W
JA
θ
θ
Thermal Resistance (Junction to Case)
Thermal Resistance (Junction to Ambient)
std bd
8 SOIC
41 to 44
°C/W
JC
JA
0 LFPM
500 LFPM
8 TSSOP
8 TSSOP
185
140
°C/W
°C/W
θ
Thermal Resistance (Junction to Case)
Wave Solder
std bd
8 TSSOP
41 to 44
265
°C/W
°C
JC
T
<2 to 3 sec @ 248°C
sol
2. Maximum Ratings are those values beyond which device damage may occur.
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2
MC10EP08, MC100EP08
10EP DC CHARACTERISTICS, PECL V = 3.3 V, V = 0 V (Note 3.)
CC
EE
–40°C
Typ
25°C
Typ
85°C
Typ
Symbol
Characteristic
Power Supply Current
Min
Max
36
Min
20
Max
38
Min
20
Max
38
Unit
mA
mV
mV
mV
mV
V
I
EE
20
28
30
32
V
V
V
V
V
Output HIGH Voltage (Note 4.)
Output LOW Voltage (Note 4.)
2165
1365
2090
1365
2.0
2290
1490
2415
1615
2415
1690
3.3
2230
1430
2155
1430
2.0
2355
1555
2480
1680
2480
1755
3.3
2290
1490
2215
1490
2.0
2415
1615
2540
1740
2540
1815
3.3
OH
OL
Input HIGH Voltage (Single Ended)
Input LOW Voltage (Single Ended)
IH
IL
Input HIGH Voltage Common Mode
Range (Differential) (Note 5.)
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
µA
µA
IH
D
D
0.5
–150
0.5
–150
0.5
–150
IL
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with V . V can vary +0.3 V to –2.2 V.
CC
EE
4. All loading with 50 ohms to V –2.0 volts.
CC
5. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
10EP DC CHARACTERISTICS, PECL V = 5.0 V, V = 0 V (Note 6.)
CC
EE
–40°C
Typ
25°C
Typ
85°C
Typ
Symbol
Characteristic
Power Supply Current
Min
Max
36
Min
20
Max
38
Min
20
Max
38
Unit
mA
mV
mV
mV
mV
V
I
EE
20
28
30
32
V
V
V
V
V
Output HIGH Voltage (Note 7.)
Output LOW Voltage (Note 7.)
3865
3065
3790
3065
2.0
3940
3190
4115
3315
4115
3390
5.0
3930
3130
3855
3130
2.0
4055
3255
4180
3380
4180
3455
5.0
3990
3190
3915
3190
2.0
4115
3315
4240
3440
4240
3515
5.0
OH
OL
Input HIGH Voltage (Single Ended)
Input LOW Voltage (Single Ended)
IH
IL
Input HIGH Voltage Common Mode
Range (Differential) (Note 8.)
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
µA
µA
IH
D
D
0.5
–150
0.5
–150
0.5
–150
IL
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
6. Input and output parameters vary 1:1 with V . V can vary +2.0 V to –0.5 V.
CC
EE
7. All loading with 50 ohms to V –2.0 volts.
CC
8. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
10EP DC CHARACTERISTICS, NECL V = 0 V; V = –5.5 V to –3.0 V (Note 9.)
CC
EE
–40°C
Typ
28
25°C
Typ
30
85°C
Typ
32
Symbol
Characteristic
Power Supply Current
Min
20
Max
Min
Max
Min
Max
38
Unit
mA
mV
mV
mV
mV
V
I
EE
36
20
38
20
V
V
V
V
V
Output HIGH Voltage (Note 10.)
Output LOW Voltage (Note 10.)
–1135 –1010 –885 –1070 –945
–820 –1010 –885
–760
OH
OL
–1935 –1810 –1685 –1870 –1745 –1620 –1810 –1685 –1560
Input HIGH Voltage (Single Ended)
Input LOW Voltage (Single Ended)
–1210
–1935
–885 –1145
–1610 –1870
–820 –1085
–1545 –1810
–760
–1485
0.0
IH
IL
Input HIGH Voltage Common Mode
Range (Differential) (Note 11.)
V
EE
+2.0
0.0
V
EE
+2.0
0.0
V
EE
+2.0
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
µA
µA
IH
D
D
0.5
–150
0.5
–150
0.5
–150
IL
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
9. Input and output parameters vary 1:1 with V
.
CC
10.All loading with 50 ohms to V –2.0 volts.
CC
11. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
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3
MC10EP08, MC100EP08
100EP DC CHARACTERISTICS, PECL V = 3.3 V, V = 0 V (Note 12.)
CC
EE
–40°C
Typ
25°C
Typ
85°C
Typ
Symbol
Characteristic
Power Supply Current
Min
Max
36
Min
20
Max
38
Min
20
Max
40
Unit
mA
mV
mV
mV
mV
V
I
EE
20
28
30
32
V
V
V
V
V
Output HIGH Voltage (Note 13.)
Output LOW Voltage (Note 13.)
2155
1355
2075
1355
2.0
2280
1480
2405
1605
2420
1675
3.3
2155
1355
2075
1355
2.0
2280
1480
2405
1605
2420
1675
3.3
2155
1355
2075
1355
2.0
2280
1480
2405
1605
2420
1675
3.3
OH
OL
Input HIGH Voltage (Single Ended)
Input LOW Voltage (Single Ended)
IH
IL
Input HIGH Voltage Common Mode
Range (Differential) (Note 14.)
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
µA
µA
IH
D
D
0.5
–150
0.5
–150
0.5
–150
IL
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
12.Input and output parameters vary 1:1 with V . V can vary +0.3 V to –2.2 V.
CC
EE
13.All loading with 50 ohms to V –2.0 volts.
CC
14.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
100EP DC CHARACTERISTICS, PECL V = 5.0 V, V = 0 V (Note 15.)
CC
EE
–40°C
Typ
25°C
Typ
85°C
Typ
Symbol
Characteristic
Power Supply Current
Min
Max
36
Min
20
Max
38
Min
20
Max
40
Unit
mA
mV
mV
mV
mV
V
I
EE
20
28
30
32
V
V
V
V
V
Output HIGH Voltage (Note 16.)
Output LOW Voltage (Note 16.)
3855
3055
3775
3055
2.0
3980
3180
4105
3305
4120
3375
5.0
3855
3055
3775
3055
2.0
3980
3180
4105
3305
4120
3375
5.0
3855
3055
3775
3055
2.0
3980
3180
4105
3305
4120
3375
5.0
OH
OL
Input HIGH Voltage (Single Ended)
Input LOW Voltage (Single Ended)
IH
IL
Input HIGH Voltage Common Mode
Range (Differential) (Note 17.)
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
µA
µA
IH
D
D
0.5
–150
0.5
–150
0.5
–150
IL
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
15.Input and output parameters vary 1:1 with V . V can vary +2.0 V to –0.5 V.
CC
EE
16.All loading with 50 ohms to V –2.0 volts.
CC
17.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
100EP DC CHARACTERISTICS, NECL V = 0 V; V = –5.5 V to –3.0 V (Note 18.)
CC
EE
–40°C
Typ
28
25°C
Typ
30
85°C
Typ
32
Symbol
Characteristic
Power Supply Current
Min
Max
Min
Max
Min
Max
Unit
mA
mV
mV
mV
mV
V
I
EE
20
36
20
38
20
40
V
V
V
V
V
Output HIGH Voltage (Note 19.)
Output LOW Voltage (Note 19.)
–1145 –1020 –895 –1145 –1020 –895 –1145 –1020 –895
–1945 –1820 –1695 –1945 –1820 –1695 –1945 –1820 –1695
OH
OL
Input HIGH Voltage (Single Ended)
Input LOW Voltage (Single Ended)
–1225
–1945
–880 –1225
–1625 –1945
–880 –1225
–1625 –1945
–880
–1625
0.0
IH
IL
Input HIGH Voltage Common Mode
Range (Differential) (Note 20.)
V
EE
+2.0
0.0
V
EE
+2.0
0.0
V
EE
+2.0
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
µA
µA
IH
D
D
0.5
–150
0.5
–150
0.5
–150
IL
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
18.Input and output parameters vary 1:1 with V
.
CC
19.All loading with 50 ohms to V –2.0 volts.
CC
20.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
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4
MC10EP08, MC100EP08
AC CHARACTERISTICS V = 0 V; V = –3.0 V to –5.5 V or
V = 3.0 V to 5.5 V; V = 0 V (Note 21.)
CC EE
CC
EE
–40°C
25°C
85°C
Typ
> 3
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Max
Unit
f
Maximum Frequency
(See Figure 2. F /JITTER)
> 3
> 3
GHz
max
max
t
t
,
Propagation Delay to
Output Differential
ps
ps
PLH
PHL
D, D to Q, Q
170
220
0.2
280
< 1
180
250
0.2
300
< 1
200
270
0.2
320
< 1
t
Cycle–to–Cycle Jitter
JITTER
(See Figure 2. F
/JITTER)
max
V
Input Voltage Swing (Differential)
150
70
800
120
1200
170
150
80
800
130
1200
180
150
100
800
150
1200
200
mV
ps
PP
t
r
t
f
Output Rise/Fall Times
(20% – 80%)
Q, Q
21.Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 ohms to V –2.0 V.
CC
900
800
700
600
500
400
300
200
9
8
7
6
5
4
3
2
1
100
(JITTER)
0
0
1000
2000
3000
4000
5000
6000
FREQUENCY (MHz)
Figure 2. Fmax/Jitter
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5
MC10EP08, MC100EP08
Q
D
Receiver
Device
Driver
Device
Qb
Db
50
TT
50
W
W
V
TT
V
V
=
– 2.0 V
CC
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 – Termination of ECL Logic Devices.)
Resource Reference of Application Notes
AN1404
AN1405
AN1406
AN1504
AN1568
AN1650
AN1672
AND8001
AND8002
AND8009
AND8020
ECLinPS Circuit Performance at Non–Standard VIH Levels
ECL Clock Distribution Techniques
Designing with PECL (ECL at +5.0 V)
Metastability and the ECLinPS Family
Interfacing Between LVDS and ECL
Using Wire–OR Ties in ECLinPS Designs
The ECL Translator Guide
–
–
–
–
–
–
–
–
–
–
–
Odd Number Counters Design
Marking and Date Codes
ECLinPS Plus Spice I/O Model Kit
Termination of ECL Logic Devices
For an updated list of Application Notes, please see our website at http://onsemi.com.
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6
MC10EP08, MC100EP08
PACKAGE DIMENSIONS
SO–8
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751–07
ISSUE W
–X–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
A
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
8
5
4
S
M
M
B
0.25 (0.010)
Y
1
K
–Y–
G
MILLIMETERS
INCHES
DIM MIN
MAX
5.00
4.00
1.75
0.51
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
4.80
3.80
1.35
0.33
0.189
0.150
0.053
0.013
C
N X 45
_
SEATING
PLANE
–Z–
1.27 BSC
0.050 BSC
0.10 (0.004)
0.10
0.19
0.40
0
0.25
0.25
1.27
8
0.004
0.010
0.010
0.050
8
0.007
0.016
0
M
J
H
D
K
M
N
S
_
_
_
_
0.25
5.80
0.50
6.20
0.010
0.228
0.020
0.244
M
S
S
X
0.25 (0.010)
Z
Y
TSSOP–8
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948R–02
ISSUE A
8x K REF
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
M
S
S
V
0.10 (0.004)
T U
S
0.15 (0.006) T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
2X L/2
8
5
4
0.25 (0.010)
B
–U–
L
1
M
PIN 1
IDENT
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
S
0.15 (0.006) T U
A
–V–
F
DETAIL E
MILLIMETERS
INCHES
MIN
DIM MIN
MAX
3.10
3.10
MAX
0.122
0.122
0.043
0.006
0.028
A
B
C
D
F
2.90
2.90
0.80
0.05
0.40
0.114
0.114
C
1.10 0.031
0.15 0.002
0.70 0.016
0.10 (0.004)
–W–
SEATING
PLANE
D
–T–
G
G
K
L
0.65 BSC
0.026 BSC
0.25
0.40 0.010
0.016
4.90 BSC
0.193 BSC
0
DETAIL E
M
0
6
6
_
_
_
_
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7
MC10EP08, MC100EP08
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
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MC10EP08/D
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