MC100EP14 [ONSEMI]
3.3V / 5V 1:5 Differential ECL/PECL/HSTL Clock Driver; 3.3V / 5V 1 ： 5差分ECL / PECL / HSTL时钟驱动器
| 型号： | MC100EP14 |
| 厂家： | 
ONSEMI |
| 描述： | 3.3V / 5V 1:5 Differential ECL/PECL/HSTL Clock Driver |
| 文件： | 总8页 (文件大小：70K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC100EP14
3.3V / 5Vꢀ1:5 Differential
ECL/PECL/HSTL Clock Driver
The MC100EP14 is a low skew 1−to−5 differential driver, designed with
clock distribution in mind, accepting two clock sources into an input
multiplexer. The ECL/PECL input signals can be either differential or
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single−ended (if the V output is used). HSTL inputs can be used when
BB
the LVEP14 is operating under PECL conditions.
The EP14 specifically guarantees low output−to−output skew. Optimal
design, layout, and processing minimize skew within a device and from
device to device.
To ensure that the tight skew specification is realized, both sides of
any differential output need to be terminated even if only one output is
being used. If an output pair is unused, both outputs may be left open
(unterminated) without affecting skew.
The common enable (EN) is synchronous, outputs are enabled/
disabled in the LOW state. This avoids a runt clock pulse when the
device is enabled/disabled as can happen with an asynchronous
control. The internal flip flop is clocked on the falling edge of the input
clock, therefore all associated specification limits are referenced to the
negative edge of the clock input.
TSSOP−20
DT SUFFIX
CASE 948E
MARKING DIAGRAM*
20
The MC100EP14, as with most other ECL devices, can be operated
from a positive V supply in PECL mode. This allows the EP14 to be
CC
100
used for high performance clock distribution in 5.0 V systems.
Designers can take advantage of the EP14’s performance to distribute
low skew clocks across the backplane or the board.
EP14
ALYW
1
• 400 ps Typical Propagation Delay
• 100 ps Device−to−Device Skew
• 25 ps Within Device Skew
A
L
Y
= Assembly Location
= Wafer Lot
= Year
W
= Work Week
• Maximum Frequency > 2 GHz Typical
• The 100 Series Contains Temperature Compensation
• PECL and HSTL Mode:
*For additional marking information, refer to
Application Note AND8002/D.
V
CC
= 3.0 V to 5.5 V with V = 0 V
EE
• NECL Mode:
= 0 V with V = −3.0 V to −5.5 V
ORDERING INFORMATION
See detailed ordering and shipping information in the package
V
CC
EE
dimensions section on page 6 of this data sheet.
• Open Input Default State
• These are Pb−Free Devices
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
Semiconductor Components Industries, LLC, 2004
1
Publication Order Number:
June, 2004 − Rev. 3
MC100EP14/D
MC100EP14
V
EN
19
V
CLK1
17
CLK1
16
V
CLK0 CLK0 CLK_SEL
V
EE
CC
CC
BB
20
18
15
14
13
12
11
1
0
D
Q
1
2
3
4
5
6
7
8
9
10
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Warning: All V and V pins must be externally connected
CC
EE
to Power Supply to guarantee proper operation.
Figure 1. TSSOP−20 (Top View) and Logic Diagram
Table 1. PIN DESCRIPTION
Pin
Table 2. FUNCTION TABLE
Function
CLK0
CLK1
CLK_SEL
EN
Q
CLK0*, CLK0**
CLK1*, CLK1**
Q0:4, Q0:4
CLK_SEL*
EN*
ECL/PECL/HSTL CLK Input
ECL/PECL/HSTL CLK Input
ECL/PECL Outputs
L
H
X
X
X
X
X
L
H
X
L
L
H
H
X
L
L
L
L
H
L
H
L
H
L*
ECL/PECL Active Clock Select Input
ECL Sync Enable
On next negative transition of CLK0 or CLK1
V
BB
V
CC
V
EE
Reference Voltage Output
Positive Supply
Negative Supply
*Pins will default low when left open.
***Pins will default to V /2 when left open.
CC
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2
MC100EP14
Table 3. ATTRIBUTES
Characteristics
Value
75 kW
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
37.5 kW
Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 100 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Level 1
UL 94 V−0 @ 0.125 in
357
Flammability Rating
Transistor Count
Oxygen Index: 28 to 34
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol
Parameter
PECL Mode Power Supply
NECL Mode Power Supply
Condition 1
= 0 V
Condition 2
Rating
Unit
V
V
CC
V
EE
V
I
V
V
6
EE
= 0 V
−6
V
CC
PECL Mode Input Voltage
NECL Mode Input Voltage
V
V
= 0 V
= 0 V
V ꢀ V
6
V
V
EE
I
CC
V ꢁ V
−6
CC
I
EE
I
I
Output Current
Continuous
Surge
50
mA
mA
out
100
V
BB
Sink/Source
± 0.5
mA
°C
BB
T
Operating Temperature Range
−40 to +85
−65 to +150
A
T
Storage Temperature Range
°C
stg
q
Thermal Resistance (Junction−to−Ambient)
0 lfpm
TSSOP−20
TSSOP−20
140
100
°C/W
°C/W
JA
500 lfpm
q
Thermal Resistance (Junction−to−Case)
Wave Solder
Standard Board
TSSOP−20
23 to 41
265
°C/W
°C
JC
T
sol
<2 to 3 sec @ 248°C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
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3
MC100EP14
Table 5. 100EP DC CHARACTERISTICS, PECL V = 3.3 V, V = 0 V (Note 2)
CC
EE
−40°C
Typ
25°C
Typ
85°C
Typ
Min
45
Max
Min
48
Max
68
Min
52
Max
72
Symbol
Characteristic
Power Supply Current
Unit
mA
mV
mV
mV
mV
mV
V
I
EE
55
65
58
62
V
V
V
V
V
V
Output HIGH Voltage (Note 3)
Output LOW Voltage (Note 3)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
2155
1355
2075
1355
1775
1.2
2280
1480
2405
1605
2420
1675
1975
3.3
2155
1355
2075
1355
1775
1.2
2280
1480
2405
1605
2420
1675
1975
3.3
2155
1355
2075
1355
1775
1.2
2280
1480
2405
1605
2420
1675
1975
3.3
OH
OL
IH
IL
1875
1875
1875
BB
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 4)
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
D
D
0.5
−150
0.5
−150
0.5
−150
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Input and output parameters vary 1:1 with V . V can vary +0.3 V to −2.2 V.
CC
EE
3. All loading with 50 W to V − 2.0 V.
CC
4. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
Table 6. 100EP DC CHARACTERISTICS, PECL V = 5.0 V, V = 0 V (Note 5)
CC
EE
−40°C
Typ
25°C
Typ
85°C
Typ
Min
45
Max
Min
48
Max
68
Min
52
Max
72
Symbol
Characteristic
Power Supply Current
Unit
mA
mV
mV
mV
mV
mV
V
I
EE
55
65
58
62
V
V
V
V
V
V
Output HIGH Voltage (Note 6)
Output LOW Voltage (Note 6)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
3855
3055
3775
3055
3475
1.2
3980
3180
4105
3305
4120
3375
3675
5.0
3855
3055
3775
3055
3475
1.2
3980
3180
4105
3305
4120
3375
3675
5.0
3855
3055
3775
3055
3475
1.2
3980
3180
4105
3305
4120
3375
3675
5.0
OH
OL
IH
IL
3575
3575
3575
BB
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 7)
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
D
D
0.5
−150
0.5
−150
0.5
−150
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and output parameters vary 1:1 with V . V can vary +2.0 V to −0.5 V.
CC
EE
6. All loading with 50 W to V − 2.0 V.
CC
7. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
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4
MC100EP14
Table 7. 100EP DC CHARACTERISTICS, NECL V = 0 V; V = −5.5 V to −3.0 V (Note 8)
CC
EE
−40°C
Typ
55
25°C
Typ
58
85°C
Typ
62
Min
Max
65
Min
Max
Min
Max
Symbol
Characteristic
Power Supply Current
Unit
mA
mV
mV
mV
mV
mV
V
I
EE
45
48
68
52
72
V
V
V
V
V
V
Output HIGH Voltage (Note 9)
Output LOW Voltage (Note 9)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Reference Voltage
−1145 −1020 −895 −1145 −1020 −895 −1145 −1020 −895
−1945 −1820 −1695 −1945 −1820 −1695 −1945 −1820 −1695
OH
OL
−1225
−1945
−880 −1225
−1625 −1945
−880 −1225
−1625 −1945
−880
IH
−1625
IL
−1525 −1425 −1325 −1525 −1425 −1325 −1525 −1425 −1325
BB
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 10)
V
EE
+1.2
0.0
V
EE
+1.2
0.0
V
EE
+1.2
0.0
IHCMR
I
I
Input HIGH Current
150
150
150
mA
mA
IH
Input LOW Current
CLK
0.5
0.5
−150
0.5
−150
IL
CLK −150
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
8. Input and output parameters vary 1:1 with V
.
CC
9. All loading with 50 W to V − 2.0 V.
CC
10.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
Table 8. AC CHARACTERISTICS V = 0 V; V = −3.0 V to −5.5 V or V = 3.0 V to 5.5 V; V = 0 V (Note 11)
CC
EE
CC
EE
−40°C
Typ
25°C
Typ
520
85°C
Typ
480
Min
Max
Min
Max
Min
Max
Symbol
Characteristic
Unit
V
OPP
Output Voltage Amplitude @ 2 GHz
(See Figure 2)
440
540
420
380
GHz
t
t
Propagation Delay to
Output Differential
275
330
400
275
375
450
280
380
480
ps
ps
PLH
PHL
t
Within−Device Skew
Device−to−Device Skew
(Note 12)
25
100
35
125
30
150
45
175
40
175
50
200
skew
t
t
Setup Time to CLK
Hold Time
EN to CLK
EN to CLK
100
200
50
140
100
200
50
140
100
200
50
140
ps
ps
s
h
t
Cycle−to−Cycle Jitter
0.2
< 1
0.2
< 1
0.2
< 1
JITTER
(See Figure 2. F
/JITTER)
max
V
Minimum Input Swing
Output Rise/Fall Time (20%−80%)
150
105
800
155
1200
205
150
145
800
200
1200
270
150
150
800
225
1200
300
mV
ps
PP
t /t
r
f
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
11. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to V − 2.0 V.
CC
12.Skew is measured between outputs under identical transitions.
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5
MC100EP14
9
8
900
850
800
750
700
650
600
550
500
450
400
5.0 V
3.3 V
7
6
5
4
3
2
(JITTER)
1
0.0
0.5
1.0
1.5
2.0
2.5
FREQUENCY (MHz)
Figure 2. Fmax/Jitter
Z = 50 W
Q
Q
D
D
o
Receiver
Device
Driver
Device
Z = 50 W
o
50 W
50 W
V
TT
V
TT
= V − 2.0 V
CC
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
ORDERING INFORMATION
†
Device
Package
TSSOP−20
TSSOP−20
Shipping
MC100EP14DT
MC100EP14DTR2
75 Units / Rail
2500 / Tape & Rail
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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6
MC100EP14
Resource Reference of Application Notes
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
AN1642/D
AND8001/D
AND8002/D
AND8020/D
AND8066/D
AND8090/D
−
−
−
−
−
−
−
−
−
−
−
ECL Clock Distribution Techniques
Designing with PECL (ECL at +5.0 V)
ECLinPSt I/O SPiCE Modeling Kit
Metastability and the ECLinPS Family
Interfacing Between LVDS and ECL
The ECL Translator Guide
Odd Number Counters Design
Marking and Date Codes
Termination of ECL Logic Devices
Interfacing with ECLinPS
AC Characteristics of ECL Devices
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7
MC100EP14
PACKAGE DIMENSIONS
TSSOP−20
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948E−02
ISSUE B
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
20X K REF
3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
M
S
S
V
0.10 (0.004)
T U
S
0.15 (0.006) T U
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER
SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
20
11
2X L/2
B
L
−U−
PIN 1
IDENT
1
10
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
0.15 (0.006) T U
A
−V−
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.260
0.177
0.047
0.006
0.030
A
B
6.40
4.30
−−−
6.60 0.252
4.50 0.169
C
1.20
−−−
D
0.05
0.50
0.15 0.002
0.75 0.020
F
G
H
0.65 BSC
0.026 BSC
0.27
0.09
0.09
0.19
0.19
0.37
0.011
0.015
0.008
0.006
0.012
0.010
J
0.20 0.004
0.16 0.004
0.30 0.007
0.25 0.007
−W−
J1
K
C
K1
L
6.40 BSC
0 8 0 8
0.252 BSC
G
D
M
_
_
_
_
H
DETAIL E
0.100 (0.004)
−T− SEATING
PLANE
ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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MC10EP14/D
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