MC100EP16FDR2G [ONSEMI]
3.3V / 5V ECL Differential Receiver/Driver With Reduced Output Swing; 3.3V / 5V ECL差分接收器/驱动器，具有更低的输出摆幅
| 型号： | MC100EP16FDR2G |
| 厂家： | 
ONSEMI |
| 描述： | 3.3V / 5V ECL Differential Receiver/Driver With Reduced Output Swing |
| 文件： | 总10页 (文件大小：151K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC100EP16F
3.3V / 5VꢀECL Differential
Receiver/Driver With
Reduced Output Swing
Description
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MARKING DIAGRAMS*
The MC100EP16F is a differential receiver/driver. The device is
functionally equivalent to the EP16 device with higher performance
capabilities. With reduced output swings, rise/fall transition times are
significantly faster than on the EP16. The EP16F is ideally suited for
interfacing with high frequency sources.
8
8
KEP60
ALYW
G
The V pin, an internally generated voltage supply, is available to
BB
1
this device only. For single−ended input conditions, the unused
differential input is connected to V as a switching reference voltage.
SOIC−8
D SUFFIX
CASE 751
1
BB
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V via a 0.01 mF capacitor and limit current sourcing or sinking
CC
to 0.5 mA. When not used, V should be left open.
BB
8
1
8
Features
1
KP60
• 100 ps Typical Rise and Fall Time
• Max Frequency >4 GHz Typical
• The 100 Series Contains Temperature Compensation
ALYWG
TSSOP−8
DT SUFFIX
CASE 948R
G
• PECL Mode Operating Range: V = 3.0 V to 5.5 V
CC
with V = 0 V
EE
• NECL Mode Operating Range: V = 0V
CC
with V = −3.0 V to −5.5 V
EE
• Open Input Default State
• Safety Clamp on Inputs
• Pb−Free Packages are Available
1
4
DFN8
MN SUFFIX
CASE 506AA
A
L
= Assembly Location
= Wafer Lot
Y
W
M
G
= Year
= Work Week
= Date Code
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
December, 2006 − Rev. 4
MC100EP16F/D
MC100EP16F
Table 1. PIN DESCRIPTION
NC
D
1
2
8
7
V
CC
PIN
FUNCTION
D*, D**
Q, Q
ECL Data Inputs
ECL Data Outputs
Q
Q
V
BB
V
CC
V
EE
Reference Voltage Output
Positive Supply
Negative Supply
No Connect
D
3
4
6
5
NC
EP
Exposed pad must be connected
to a sufficient thermal conduit.
Electrically connect to the most
negative supply or leave floating
open.
V
BB
V
EE
*
Pins will default LOW when left open.
** Pins will default to V /2 when left open.
CC
Figure 1. 8−Lead Pinout (Top View) and Logic Diagram
Table 2. ATTRIBUTES
Characteristics
Value
75 kW
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
37.5 kW
Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Pb Pkg
Pb−Free Pkg
SOIC−8
TSSOP−8
DFN8
Level 1
Level 1
Level 1
Level 1
Level 3
Level 1
Flammability Rating
Transistor Count
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
139
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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2
MC100EP16F
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
V
V
CC
V
EE
V
I
PECL Mode Power Supply
NECL Mode Power Supply
V
V
= 0 V
= 0 V
6
EE
−6
V
CC
PECL Mode Input Voltage
NECL Mode Input Voltage
V
V
= 0 V
= 0 V
V ꢀ V
6
−6
V
V
EE
I
CC
V ꢁ V
CC
I
EE
I
I
Output Current
Continuous
Surge
50
100
mA
mA
out
V
BB
Sink/Source
± 0.5
mA
°C
BB
T
Operating Temperature Range
Storage Temperature Range
−40 to +85
−65 to +150
A
T
°C
stg
q
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
8 SOIC
8 SOIC
190
130
°C/W
°C/W
JA
q
q
Thermal Resistance (Junction−to−Case)
Standard Board
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
Standard Board
Thermal Resistance (Junction−to−Ambient) 0 lfpm
8 SOIC
41 to 44 ± 5%
°C/W
JC
JA
8 TSSOP
8 TSSOP
185
140
°C/W
°C/W
q
q
Thermal Resistance (Junction−to−Case)
8 TSSOP
41 to 44 ± 5%
°C/W
JC
JA
DFN8
DFN8
129
84
°C/W
°C/W
500 lfpm
T
sol
Wave Solder
Pb <2 to 3 sec @ 248°C
Pb−Free <2 to 3 sec @ 260°C
265
265
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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3
MC100EP16F
Table 4. DC CHARACTERISTICS, PECL V = 3.3 V, V = 0 V (Note 2)
CC
EE
−40°C
25°C
Typ
85°C
Typ
Symbol
Characteristic
Power Supply Current
Min
23
Typ
28
Max
40
Min
25
Max
45
Min
26
Max
45
Unit
mA
mV
mV
mV
mV
I
EE
33
33
V
V
V
V
Output HIGH Voltage (Note 3)
Output LOW Voltage (Note 3)
Input HIGH Voltage (Single−Ended)
2155
1525
2075
1355
2280
1690
2405
1775
2420
1675
2155
1525
2075
1355
2280
1690
2405
1775
2420
1675
2155
1525
2075
1355
2280
1690
2405
1775
2420
1675
OH
OL
IH
Input LOW Voltage (Single−Ended)
IL
(Note 4)
V
V
Output Voltage Reference
1775
2.0
1875
1975
3.3
1775
2.0
1875
1975
3.3
1775
2.0
1875
1975
3.3
mV
V
BB
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 5)
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
D
0.5
0.5
0.5
IL
D
−150
−150
−150
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Input and output parameters vary 1:1 with V . V can vary +0.3 V to −2.2 V.
CC
EE
3. All loading with 50 W to V − 2.0 V.
CC
4. Not recommended for Single−Ended operation when using an EP16F to drive another EP16F. V has reduced output swing and may not
OL
meet the V specification over temperature.
IL
5. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
Table 5. DC CHARACTERISTICS, PECL V = 5.0 V, V = 0 V (Note 6)
CC
EE
−40°C
25°C
Typ
85°C
Typ
Symbol
Characteristic
Power Supply Current
Min
23
Typ
28
Max
40
Min
25
Max
45
Min
26
Max
45
Unit
mA
mV
mV
mV
mV
I
EE
35
33
V
V
V
V
Output HIGH Voltage (Note 7)
Output LOW Voltage (Note 7)
Input HIGH Voltage (Single−Ended)
3855
3225
3775
3055
3980
3390
4105
3475
4120
3375
3855
3225
3775
3055
3980
3390
4105
3475
4120
3375
3855
3225
3775
3055
3980
3390
4105
3475
4120
3375
OH
OL
IH
Input LOW Voltage (Single−Ended)
IL
(Note 8)
V
V
Output Voltage Reference
3475
2.0
3575
3675
5.0
3475
2.0
3575
3675
5.0
3475
2.0
3575
3675
5.0
mV
V
BB
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 9)
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
D
0.5
0.5
0.5
IL
D
−150
−150
−150
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
6. Input and output parameters vary 1:1 with V . V can vary +2.0 V to −0.5 V.
CC
EE
7. All loading with 50 W to V − 2.0 V.
CC
8. Not recommended for Single−Ended operation when using an EP16F to drive another EP16F. V has reduced output swing and may not
OL
meet the V specification over temperature.
IL
9. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
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4
MC100EP16F
Table 6. DC CHARACTERISTICS, NECL V = 0 V; V = −5.5 V to −3.0 V (Note 10)
CC
EE
−40°C
25°C
Typ
34
85°C
Typ
33
Symbol
Characteristic
Power Supply Current
Min
Typ
Max
Min
Max
Min
Max
Unit
mA
mV
mV
mV
mV
I
EE
23
28
40
25
45
26
45
V
V
V
V
Output HIGH Voltage (Note 11)
Output LOW Voltage (Note 11)
Input HIGH Voltage (Single−Ended)
−1145 −1020 −895 −1145 −1020 −895 −1145 −1020 −895
−1775 −1610 −1525 −1775 −1610 −1525 −1775 −1610 −1525
OH
OL
IH
−1225
−1810
−880 −1225
−1625 −1810
−880 −1225
−1625 −1810
−880
Input LOW Voltage (Single−Ended)
−1625
IL
(Note 12)
V
V
Output Voltage Reference
−1525 −1425 −1325 −1525 −1425 −1325 −1525 −1425 −1325
mV
V
BB
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 13)
V
EE
+2.0
0.0
V
EE
+2.0
0.0
V
EE
+2.0
0.0
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
D
0.5
0.5
0.5
IL
D
−150
−150
−150
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
10.Input and output parameters vary 1:1 with V
.
CC
11. All loading with 50 W to V − 2.0 V.
CC
12.Not recommended for Single−Ended operation when using an EP16F to drive another EP16F. V has reduced output swing and may not
OL
meet the V specification over temperature.
IL
13.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
Table 7. AC CHARACTERISTICS V = 0 V; V = −3.0 V to −5.5 V or V = 3.0 V to 5.5 V; V = 0 V (Note 14)
CC
EE
CC
EE
−40°C
Typ
25°C
Typ
> 4
85°C
Typ
> 4
Symbol
Characteristic
Min
Max
Min
Max
Min
Max
Unit
f
Maximum Toggle Frequency
> 4
GHz
max
(See Figure 2. F
/JITTER)
max
t
t
,
Propagation Delay to Output
Differential
170
210
250
180
220
260
200
250
300
ps
PLH
PHL
t
t
Duty Cycle Skew
5.0
0.2
20
5.0
0.2
20
5.0
0.2
20
ps
ps
SKEW
Cycle−to−Cycle Jitter (RMS)
< 1
< 1
< 1
JITTER
(See Figure 2. F
/JITTER)
max
V
Input Voltage Swing
(Differential Configuration)
150
70
800
85
1200
110
150
80
800
100
1200
120
150
90
800
110
1200
130
mV
ps
PP
t
r
t
f
Output Rise/Fall Times
(20% − 80%)
Q
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
14.Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to V −2.0 V.
CC
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5
MC100EP16F
800
700
600
500
400
300
200
100
0
8
7
6
5
4
3
2
1
Measured
Simulated
(JITTER)
0
1000
2000
3000
4000
5000
6000
FREQUENCY (MHz)
Figure 2. Fmax/JITTER
Z = 50 W
Q
D
D
o
Receiver
Device
Driver
Device
Q
Z = 50 W
o
50 W
50 W
V
TT
V
TT
= V − 2.0 V
CC
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
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6
MC100EP16F
ORDERING INFORMATION
Device
†
Package
Shipping
MC100EP16FD
SOIC−8
98 Units / Rail
98 Units / Rail
MC100EP16FDG
SOIC−8
(Pb−Free)
MC100EP16FDR2
MC100EP16FDR2G
SOIC−8
2500 / Tape & Reel
2500 / Tape & Reel
SOIC−8
(Pb−Free)
MC100EP16FDT
TSSOP−8
100 Units / Rail
100 Units / Rail
MC100EP16FDTG
TSSOP−8
(Pb−Free)
MC100EP16FDTR2
MC100EP16FDTR2G
TSSOP−8
2500 / Tape & Reel
2500 / Tape & Reel
TSSOP−8
(Pb−Free)
MC100EP16FMNR4
MC100EP16FMNR4G
DFN8
1000 / Tape & Reel
1000 / Tape & Reel
DFN8
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
AN1672/D
AND8001/D
AND8002/D
AND8020/D
AND8066/D
AND8090/D
−
−
−
−
−
−
−
−
−
−
−
ECL Clock Distribution Techniques
Designing with PECL (ECL at +5.0 V)
ECLinPSt I/O SPiCE Modeling Kit
Metastability and the ECLinPS Family
Interfacing Between LVDS and ECL
The ECL Translator Guide
Odd Number Counters Design
Marking and Date Codes
Termination of ECL Logic Devices
Interfacing with ECLinPS
AC Characteristics of ECL Devices
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7
MC100EP16F
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AH
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−X−
A
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
−Z−
1.27 BSC
0.050 BSC
0.10 (0.004)
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
SOLDERING FOOTPRINT*
1.52
0.060
7.0
4.0
0.275
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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8
MC100EP16F
PACKAGE DIMENSIONS
TSSOP−8
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948R−02
ISSUE A
8x K REF
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
M
S
S
V
0.10 (0.004)
T U
S
0.15 (0.006) T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
2X L/2
8
5
4
0.25 (0.010)
B
−U−
L
1
M
PIN 1
IDENT
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE −W−.
S
0.15 (0.006) T U
A
−V−
F
DETAIL E
MILLIMETERS
INCHES
MIN
DIM MIN
MAX
3.10
3.10
MAX
0.122
0.122
0.043
0.006
0.028
A
B
C
D
F
2.90
2.90
0.80
0.05
0.40
0.114
0.114
C
1.10 0.031
0.15 0.002
0.70 0.016
0.10 (0.004)
−W−
SEATING
PLANE
D
−T−
G
G
K
L
0.65 BSC
0.026 BSC
0.25
0.40 0.010
0.016
4.90 BSC
0.193 BSC
0
DETAIL E
M
0
6
6
_
_
_
_
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9
MC100EP16F
PACKAGE DIMENSIONS
DFN8
CASE 506AA−01
ISSUE D
1
NOTES:
D
A
B
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994 .
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PIN ONE
REFERENCE
MILLIMETERS
DIM MIN
MAX
1.00
0.05
E
A
A1
A3
b
0.80
0.00
0.20 REF
0.20
0.30
2 X
D
D2
E
2.00 BSC
0.10
C
1.10
1.30
2.00 BSC
2 X
E2
0.70
0.90
e
K
0.50 BSC
0.10
C
TOP VIEW
0.20
−−−
L
0.25
0.35
A
0.10
0.08
C
C
8 X
(A3)
SIDE VIEW
D2
A1
SEATING
PLANE
C
e
e/2
4
1
8 X L
E2
K
8
5
0.10 C A B
0.05
8 X b
C
NOTE 3
BOTTOM VIEW
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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