MC100EP40DTR2G [ONSEMI]
3.3V / 5V ECL Differential Phase−Frequency Detector; 3.3V / 5V ECL差分相位频率检测
| 型号： | MC100EP40DTR2G |
| 厂家： | 
ONSEMI |
| 描述： | 3.3V / 5V ECL Differential Phase−Frequency Detector |
| 文件： | 总9页 (文件大小：134K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC100EP40
3.3V / 5VꢀECL Differential
Phase−Frequency Detector
Description
The MC100EP40 is a three−state phase−frequency detector
intended for phase−locked loop applications which require a minimum
amount of phase and frequency difference at lock. Advanced design
significantly reduces the dead zone of the detector. For proper
operation, the input edge rate of the R and V inputs should be less than
5 ns. The device is designed to work with a 3.3 V / 5 V power supply.
When Reference (R) and Feedback (FB) inputs are unequal in
frequency and/or phase the differential UP (U) and DOWN (D)
outputs will provide pulse streams which when subtracted and
integrated provide an error voltage for control of a VCO.
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MARKING
DIAGRAM*
20
20
100
EP40
1
ALYW G
G
When Reference (R) and Feedback (FB) inputs are 80 ps or less in
phase difference, the Phase Lock Detect pin will indicate lock by a
TSSOP−20
DT SUFFIX
CASE 948E
1
high state (V ). The V (V , V , V , V ) pins offer an
OH
TX
TR
TR
TFB
TFB
internal termination network for 50 W line impedance environment
shown in Figure 2. An external sinking supply of V −2 V is required
CC
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
on V pin(s). If you short the two differential V and V (or V
TX
TR
TR
TFB
and V ) together, you provide a 100 W termination resistance that is
TFB
compatible with LVDS signal receiver termination. For more
information on termination of logic devices, see AND8020.
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
The V pin, an internally generated voltage supply, is available to
BB
this device only. For single-ended input conditions, the unused
differential input is connected to V as a switching reference voltage.
BB
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V via a 0.01 mF capacitor and limit current sourcing or sinking
CC
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
to 0.5 mA. When not used, V should be left open.
BB
For more information on Phase Lock Loop operation, refer to
AND8040.
Special considerations are required for differential inputs under No
Signal conditions to prevent instability.
Features
• Maximum Frequency > 2 GHz Typical
• Fully Differential
• Advanced High Band Output Swing of 400 mV
• Theoretical Gain = 1.11
• T 97 ps Typical, F 70 ps Typical
rise
fall
• The 100 Series Contains Temperature Compensation
• PECL Mode Operating Range: V = 3.0 V to 5.5 V
CC
with V = 0 V
EE
• NECL Mode Operating Range: V = 0 V
CC
with V = −3.0 V to −5.5 V
EE
• 50 W Internal Termination Resistor
• These are Pb−Free Devices
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
November, 2006 − Rev. 10
MC100EP40/D
MC100EP40
Table 1. PIN DESCRIPTION
V
PLD
V
D
D
U
U
V
NC
V
EE
CC
CC
CC
PIN
FUNCTION
20
19
18
17
16
15
14
12
13
11
U, U
ECL Up Differential Outputs
D, D
ECL Down Differential Outputs
ECL Feedback Differential Inputs
ECL Reference Differential Inputs
ECL Phase Lock Detect Function
ECL Internal Termination for R
ECL Internal Termination for R
ECL Internal Termination for FB
ECL Internal Termination for FB
Reference Voltage Output
Positive Supply
FB, FB
R, R
PLD
1
2
3
4
5
6
7
9
8
10
VTR
V
VTFB VTFB FB
FB
R
R
VTR VTR V
BB
EE
VTR
Warning: All V and V pins must be externally connected
CC
EE
to Power Supply to guarantee proper operation.
VTFB
VTFB
Figure 1. 20−Lead Pinout (Top View)
V
V
V
BB
CC
EE
Negative Supply
NC
No Connect
V
V
TR
U
50 W
50 W
C
A
U
U
A
R
R
A
C
D
S
R
U
D
FF
FF
A
Reset
C
TR
Reset
Reset
D
B
V
TFB
R
S
Reset
B
B
50 W
50 W
(V) FB
FB
D
D
B
D
D
V
TFB
V
BB
Figure 2. Logic Diagram
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2
MC100EP40
Table 2. ATTRIBUTES
Characteristics
Value
N/A
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
N/A
Human Body Model
Machine Model
> 4 kV
> 100 V
> 2 kV
Charged Device Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Pb Pkg
Level 1
Pb−Free Pkg
Level 3
TSSOP−20
Flammability Rating
Transistor Count
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
699 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 3. MAXIMUM RATINGS
Symbol
Parameter
PECL Mode Power Supply
NECL Mode Power Supply
Condition 1
= 0 V
Condition 2
Rating
Unit
V
V
V
V
V
V
6
CC
EE
I
EE
CC
= 0 V
−6
V
PECL Mode Input Voltage
NECL Mode Input Voltage
V
V
= 0 V
= 0 V
V v V
6
−6
V
V
EE
CC
I
CC
V w V
I
EE
I
Output Current
Continuous
Surge
50
100
mA
mA
out
I
V
Sink/Source
BB
± 0.5
mA
°C
BB
T
Operating Temperature Range
−40 to +85
−65 to +150
A
T
Storage Temperature Range
°C
stg
q
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
TSSOP−20
TSSOP−20
140
100
°C/W
°C/W
JA
q
Thermal Resistance (Junction−to−Case)
Standard Board
TSSOP−20
23 to 41
°C/W
°C
JC
T
sol
Wave Solder
Pb
Pb−Free
265
265
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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3
MC100EP40
Table 4. 100EP DC CHARACTERISTICS, PECL V = 3.3 V, V = 0 V (Note 2)
CC
EE
−40°C
25°C
85°C
Min
Typ
128
Max
160
Min
100
Typ
130
Max
160
Min
110
Typ
140
Max
170
Symbol
Characteristic
Power Supply Current
Unit
mA
mV
mV
I
100
EE
V
V
Output HIGH Voltage (Note 3) U, U, B, B 2225
2350
2475
2275
2400
2525
2300
2425
2550
OH
OL
Output LOW Voltage (Note 3)
1775
PLD 1355
1900
1480
2025
1605
1800
1355
1925
1480
2050
1605
1825
1355
1950
1480
2075
1605
V
V
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
2075
1355
1775
2.0
2420
1675
1975
3.3
2075
1355
1775
2.0
2420
1675
1975
3.3
2075
1355
1775
2.0
2420
1675
1975
3.3
mV
mV
mV
V
IH
IL
V
V
1875
1875
1875
BB
Input HIGH Voltage Common Mode
Range (Differential Configuration) (Note 4)
IHCMR
I
I
Input HIGH Current
150
150
150
mA
mA
IH
IL
Input LOW Current
−150
−150
−150
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Input and output parameters vary 1:1 with V . V can vary +0.3 V to −2.2 V.
CC
EE
3. All loading with 50 W to V − 2.0 V.
CC
4. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
Table 5. 100EP DC CHARACTERISTICS, PECL V = 3.3 V, V = 0 V (Note 5)
CC
EE
−40°C
Typ
25°C
Typ
85°C
Typ
Min
100
Max
160
Min
100
Max
160
Min
110
Max
170
Symbol
Characteristic
Power Supply Current (Note 6)
Output HIGH Voltage (Note 7)
Unit
mA
mV
mV
I
128
130
140
EE
V
V
3925
4050
4175
3975
4100
4225
4000
4125
4250
OH
OL
Output LOW Voltage (Note 7) U, U, B, B 3475
PLD 3055
3600
3180
3725
3305
3500
3055
3625
3180
3750
3305
3525
3055
3650
3180
3775
3305
V
V
V
V
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
3775
3055
3475
2.0
4120
3375
3675
5.0
3775
3055
3475
2.0
4120
3375
3675
5.0
3775
3055
3475
2.0
4120
3375
3675
5.0
mV
mV
mV
V
IH
IL
3575
3575
3575
BB
Input HIGH Voltage Common Mode
Range (Differential Configuration) (Note 8)
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
IL
−150
−150
−150
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and output parameters vary 1:1 with V . V can vary +0.3 V to −2.2 V.
CC
EE
6. For (V − V ) > 3.3 V, 5 W to 10 W in line with V required for maximum thermal protection at elevated temperatures. Recommend
CC
EE
EE
EE
V
−V operation at ꢀ 3.3 V.
CC
7. All loading with 50 W to V − 2.0 V.
CC
8. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
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4
MC100EP40
Table 6. 100EP DC CHARACTERISTICS, NECL V = 0 V; V = −5.5 V to −3.0 V (Note 9)
CC
EE
−40°C
Typ
25°C
Typ
130
85°C
Typ
140
Min
100
Max
Min
Max
Min
Max
170
Symbol
Characteristic
Unit
mA
mV
mV
I
Power Supply Current (Note 10)
Output HIGH Voltage (Note 11)
Output LOW Voltage (Note 11)
128
160
100
160
110
EE
V
V
−1075 −950
−825 −1025 −900
−775 −1000 −875
−750
OH
OL
U, U, B, B −1525 −1400 −1275 −1500 −1375 −1250 −1475 −1350 −1225
PLD −1945 −1820 −1695 −1945 −1820 −1945 −1945 −1820 −1945
V
V
V
V
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
−1225
−1945
−880 −1225
−1625 −1945
−880 −1225
−1625 −1945
−880
mV
IH
−1625 mV
IL
−1525 −1425 −1325 −1525 −1425 −1325 −1525 −1425 −1325 mV
BB
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 12)
V
+ 2.0
0.0
V
+ 2.0
0.0
V + 2.0
EE
0.0
V
IHCMR
EE
EE
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
IL
−150
−150
−150
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
9. Input and output parameters vary 1:1 with V
.
CC
10.For (V − V ) > 3.3 V, 5 W to 10 W in line with V required for maximum thermal protection at elevated temperatures. Recommend
CC
EE
EE
EE
V
−V operation at ꢀ 3.3 V.
CC
11. All loading with 50 W to V − 2.0 V.
CC
12.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
Table 7. AC CHARACTERISTICS V = 0 V; V = −3.0 V to −5.5 V or V = 3.0 V to 5.5 V; V = 0 V (Note 13)
CC
EE
CC
EE
Max
750
−40°C
Typ
25°C
Typ
> 2
85°C
Typ
> 2
Min
Max
Min
Min
Max
Symbol
Characteristic
Unit
GHz
ps
f
Maximum Frequency (Figure 3)
> 2
max
t
t
,
Propagation Delay to
Output Differential
FB to D/U
R to D/U
400
525
700
410
550
450
575
775
PLH
PHL
t
Random Clock Jitter (Figure 3)
0.2
< 1
0.2
< 1
0.2
< 1
ps
JITTER
V
Input Voltage Swing (Differential Configu-
ration)
150
60
800
1200
150
60
800
1200
150
80
800
1200
mV
PP
t
t
Output Rise/Fall Times
Q, Q
85
130
110
150
120
160
ps
r
f
(20% − 80%)
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
13.Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to V − 2.0 V.
CC
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5
MC100EP40
10
9
550
500
450
400
350
300
250
8
5 V
7
6
3.3 V
5
4
3
2
1
0
(JITTER)
2.0
1.0
1.5
2.5
FREQUENCY (GHz)
Figure 3. Fmax/Jitter @ 255C
Z = 50 W
o
Q
D
Receiver
Device
Driver
Device
Q
Z = 50 W
o
D
50 W
50 W
V
TT
V
= V − 2.0 V
TT
CC
Figure 4. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
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6
MC100EP40
ORDERING INFORMATION
Device
†
Package
Shipping
MC100EP40DT
TSSOP−20*
TSSOP−20*
TSSOP−20*
TSSOP−20*
75 Units / Rail
75 Units / Rail
MC100EP40DTG
MC100EP40DTR2
MC100EP40DTR2G
2500 / Tape & Reel
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
Resource Reference of Application Notes
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
AN1672/D
AND8001/D
AND8002/D
AND8020/D
AND8066/D
AND8090/D
−
−
−
−
−
−
−
−
−
−
−
ECL Clock Distribution Techniques
Designing with PECL (ECL at +5.0 V)
ECLinPSt I/O SPiCE Modeling Kit
Metastability and the ECLinPS Family
Interfacing Between LVDS and ECL
The ECL Translator Guide
Odd Number Counters Design
Marking and Date Codes
Termination of ECL Logic Devices
Interfacing with ECLinPS
AC Characteristics of ECL Devices
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MC100EP40
PACKAGE DIMENSIONS
TSSOP−20
CASE 948E−02
ISSUE C
NOTES:
20X K REF
1. DIMENSIONING AND TOLERANCING PER
K
K1
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
M
S
S
V
0.10 (0.004)
T
U
S
U
0.15 (0.006) T
3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
J J1
20
11
2X L/2
B
SECTION N−N
L
−U−
PIN 1
IDENT
0.25 (0.010)
N
1
10
M
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
0.15 (0.006) T
U
A
−V−
N
MILLIMETERS
INCHES
DIM MIN
MAX
6.60
4.50
1.20
0.15
0.75
MIN
MAX
0.260
0.177
F
A
B
6.40
4.30
−−−
0.252
0.169
DETAIL E
C
−−− 0.047
0.006
0.030
D
0.05
0.50
0.002
0.020
F
G
H
0.65 BSC
0.026 BSC
−W−
0.27
0.09
0.09
0.19
0.19
0.37
0.20
0.16
0.30
0.25
0.011
0.004
0.004
0.007
0.007
0.015
0.008
0.006
0.012
0.010
C
J
J1
K
G
D
H
K1
L
DETAIL E
6.40 BSC
0.252 BSC
0
0.100 (0.004)
−T− SEATING
M
0
8
8
_
_
_
_
PLANE
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
01.36X6
16X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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8
MC100EP40
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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MC100EP40/D
相关型号：
MC100EP445MNG
Serial to Parallel Converter, 3.3 V / 5 V, 8-bit ECL, QFN32, 5x5, 0.5P, 3.1x3.1EP, 74-TUBE
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